mirror of
https://github.com/plappermaul/realtek-doc.git
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491 lines
14 KiB
C
491 lines
14 KiB
C
/*
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* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _QCA8075_PHY_H_
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#define _QCA8075_PHY_H_
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#define QCA8075_PHY_CONTROL 0
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#define QCA8075_PHY_STATUS 1
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#define QCA8075_PHY_ID1 2
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#define QCA8075_PHY_ID2 3
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#define QCA8075_AUTONEG_ADVERT 4
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#define QCA8075_LINK_PARTNER_ABILITY 5
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#define QCA8075_AUTONEG_EXPANSION 6
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#define QCA8075_NEXT_PAGE_TRANSMIT 7
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#define QCA8075_LINK_PARTNER_NEXT_PAGE 8
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#define QCA8075_1000BASET_CONTROL 9
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#define QCA8075_1000BASET_STATUS 10
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#define QCA8075_MMD_CTRL_REG 13
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#define QCA8075_MMD_DATA_REG 14
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#define QCA8075_EXTENDED_STATUS 15
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#define QCA8075_PHY_SPEC_CONTROL 16
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#define QCA8075_PHY_SPEC_STATUS 17
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#define QCA8075_PHY_INTR_MASK 18
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#define QCA8075_PHY_INTR_STATUS 19
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#define QCA8075_PHY_CDT_CONTROL 22
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#define QCA8075_PHY_CDT_STATUS 28
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#define QCA8075_DEBUG_PORT_ADDRESS 29
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#define QCA8075_DEBUG_PORT_DATA 30
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#define COMBO_PHY_ID 4
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#define PSGMII_ID 5
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#define QCA8075_DEBUG_PHY_HIBERNATION_CTRL 0xb
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#define QCA8075_DEBUG_PHY_POWER_SAVING_CTRL 0x29
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#define QCA8075_PHY_MMD7_ADDR_8023AZ_EEE_CTRL 0x3c
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#define QCA8075_PHY_MMD3_ADDR_REMOTE_LOOPBACK_CTRL 0x805a
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#define QCA8075_PHY_MMD3_WOL_MAGIC_MAC_CTRL1 0x804a
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#define QCA8075_PHY_MMD3_WOL_MAGIC_MAC_CTRL2 0x804b
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#define QCA8075_PHY_MMD3_WOL_MAGIC_MAC_CTRL3 0x804c
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#define QCA8075_PHY_MMD3_WOL_CTRL 0x8012
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#define QCA8075_PSGMII_FIFI_CTRL 0x6e
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#define QCA8075_PSGMII_CALIB_CTRL 0x27
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#define QCA8075_PSGMII_MODE_CTRL 0x6d
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#define QCA8075_PHY_PSGMII_MODE_CTRL_ADJUST_VALUE 0x220c
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#define QCA8075_PHY_MMD7_NUM 7
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#define QCA8075_PHY_MMD3_NUM 3
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#define QCA8075_PHY_MMD1_NUM 1
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#define QCA8075_PHY_SGMII_STATUS 0x1a /* sgmii_status Register */
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#define QCA8075_PHY4_AUTO_SGMII_SELECT 0x40
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#define QCA8075_PHY4_AUTO_COPPER_SELECT 0x20
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#define QCA8075_PHY4_AUTO_BX1000_SELECT 0x10
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#define QCA8075_PHY4_AUTO_FX100_SELECT 0x8
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#define QCA8075_MODE_RESET_REG 0x0
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#define QCA8075_MODE_CHANAGE_RESET 0x0
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#define QCA8075_MODE_RESET_DEFAULT_VALUE 0x5f
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#define QCA8075_PHY_MAX_ADDR_INC 0x4
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#define QCA8075_PHY_PSGMII_ADDR_INC 0x5
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#define QCA8075_PHY_CHIP_CONFIG 0x1f /* Chip Configuration Register */
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#define BT_BX_SG_REG_SELECT BIT_15
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#define BT_BX_SG_REG_SELECT_OFFSET 15
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#define BT_BX_SG_REG_SELECT_LEN 1
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#define QCA8075_SG_BX_PAGES 0x0
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#define QCA8075_SG_COPPER_PAGES 0x1
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#define QCA8075_PHY_PSGMII_BASET 0x0
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#define QCA8075_PHY_PSGMII_BX1000 0x1
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#define QCA8075_PHY_PSGMII_FX100 0x2
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#define QCA8075_PHY_PSGMII_AMDET 0x3
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#define QCA8075_PHY_SGMII_BASET 0x4
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#define QCA8075_PHY4_PREFER_FIBER 0x400
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#define PHY4_PREFER_COPPER 0x0
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#define PHY4_PREFER_FIBER 0x1
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#define QCA8075_PHY4_FIBER_MODE_1000BX 0x100
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#define AUTO_100FX_FIBER 0x0
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#define AUTO_1000BX_FIBER 0x1
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#define QCA8075_PHY_MDIX 0x0020
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#define QCA8075_PHY_MDIX_AUTO 0x0060
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#define QCA8075_PHY_MDIX_STATUS 0x0040
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#define MODE_CFG_QUAL BIT_4
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#define MODE_CFG_QUAL_OFFSET 4
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#define MODE_CFG_QUAL_LEN 4
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#define MODE_CFG BIT_0
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#define MODE_CFG_OFFSET 0
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#define MODE_CFG_LEN 4
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#define QCA8075_PHY_MMD3_ADDR_8023AZ_CLD_CTRL 0x8007
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#define QCA8075_PHY_MMD3_ADDR_8023AZ_TIMER_CTRL 0x804e
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#define QCA8075_PHY_MMD3_ADDR_CLD_CTRL5 0x8005
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#define QCA8075_PHY_MMD3_ADDR_CLD_CTRL3 0x8003
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#define AZ_TIMER_CTRL_DEFAULT_VALUE 0x3062
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#define AZ_CLD_CTRL_DEFAULT_VALUE 0x83f6
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#define AZ_TIMER_CTRL_ADJUST_VALUE 0x7062
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#define AZ_CLD_CTRL_ADJUST_VALUE 0x8396
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/*debug port */
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#define QCA8075_DEBUG_PORT_RGMII_MODE 18
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#define QCA8075_DEBUG_PORT_RGMII_MODE_EN 0x0008
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#define QCA8075_DEBUG_PORT_RX_DELAY 0
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#define QCA8075_DEBUG_PORT_RX_DELAY_EN 0x8000
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#define QCA8075_DEBUG_PORT_TX_DELAY 5
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#define QCA8075_DEBUG_PORT_TX_DELAY_EN 0x0100
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/* PHY Registers Field */
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/* Control Register fields offset:0 */
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/* bits 6,13: 10=1000, 01=100, 00=10 */
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#define QCA8075_CTRL_SPEED_MSB 0x0040
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/* Collision test enable */
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#define QCA8075_CTRL_COLL_TEST_ENABLE 0x0080
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/* FDX =1, half duplex =0 */
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#define QCA8075_CTRL_FULL_DUPLEX 0x0100
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/* Restart auto negotiation */
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#define QCA8075_CTRL_RESTART_AUTONEGOTIATION 0x0200
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/* Isolate PHY from MII */
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#define QCA8075_CTRL_ISOLATE 0x0400
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/* Power down */
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#define QCA8075_CTRL_POWER_DOWN 0x0800
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/* Auto Neg Enable */
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#define QCA8075_CTRL_AUTONEGOTIATION_ENABLE 0x1000
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/* Local Loopback Enable */
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#define QCA8075_LOCAL_LOOPBACK_ENABLE 0x4000
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/* bits 6,13: 10=1000, 01=100, 00=10 */
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#define QCA8075_CTRL_SPEED_LSB 0x2000
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/* 0 = normal, 1 = loopback */
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#define QCA8075_CTRL_LOOPBACK 0x4000
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#define QCA8075_CTRL_SOFTWARE_RESET 0x8000
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#define QCA8075_CTRL_SPEED_MASK 0x2040
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#define QCA8075_CTRL_SPEED_1000 0x0040
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#define QCA8075_CTRL_SPEED_100 0x2000
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#define QCA8075_CTRL_SPEED_10 0x0000
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#define QCA8075_RESET_DONE(phy_control) \
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(((phy_control) & (QCA8075_CTRL_SOFTWARE_RESET)) == 0)
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/* Status Register fields offset:1 */
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/* Extended register capabilities */
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#define QCA8075_STATUS_EXTENDED_CAPS 0x0001
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/* Jabber Detected */
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#define QCA8075_STATUS_JABBER_DETECT 0x0002
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/* Link Status 1 = link */
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#define QCA8075_STATUS_LINK_STATUS_UP 0x0004
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/* Auto Neg Capable */
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#define QCA8075_STATUS_AUTONEG_CAPS 0x0008
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/* Remote Fault Detect */
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#define QCA8075_STATUS_REMOTE_FAULT 0x0010
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/* Auto Neg Complete */
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#define QCA8075_STATUS_AUTO_NEG_DONE 0x0020
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/* Preamble may be suppressed */
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#define QCA8075_STATUS_PREAMBLE_SUPPRESS 0x0040
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/* Ext. status info in Reg 0x0F */
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#define QCA8075_STATUS_EXTENDED_STATUS 0x0100
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/* 100T2 Half Duplex Capable */
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#define QCA8075_STATUS_100T2_HD_CAPS 0x0200
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/* 100T2 Full Duplex Capable */
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#define QCA8075_STATUS_100T2_FD_CAPS 0x0400
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/* 10T Half Duplex Capable */
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#define QCA8075_STATUS_10T_HD_CAPS 0x0800
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/* 10T Full Duplex Capable */
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#define QCA8075_STATUS_10T_FD_CAPS 0x1000
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/* 100X Half Duplex Capable */
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#define QCA8075_STATUS_100X_HD_CAPS 0x2000
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/* 100X Full Duplex Capable */
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#define QCA8075_STATUS_100X_FD_CAPS 0x4000
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/* 100T4 Capable */
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#define QCA8075_STATUS_100T4_CAPS 0x8000
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/* extended status register capabilities */
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#define QCA8075_STATUS_1000T_HD_CAPS 0x1000
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#define QCA8075_STATUS_1000T_FD_CAPS 0x2000
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#define QCA8075_STATUS_1000X_HD_CAPS 0x4000
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#define QCA8075_STATUS_1000X_FD_CAPS 0x8000
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#define QCA8075_AUTONEG_DONE(ip_phy_status) \
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(((ip_phy_status) & (QCA8075_STATUS_AUTO_NEG_DONE)) == \
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(QCA8075_STATUS_AUTO_NEG_DONE))
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/* PHY identifier1 offset:2 */
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//Organizationally Unique Identifier bits 3:18
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/* PHY identifier2 offset:3 */
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//Organizationally Unique Identifier bits 19:24
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/* Auto-Negotiation Advertisement register. offset:4 */
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/* indicates IEEE 802.3 CSMA/CD */
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#define QCA8075_ADVERTISE_SELECTOR_FIELD 0x0001
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/* 10T Half Duplex Capable */
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#define QCA8075_ADVERTISE_10HALF 0x0020
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/* 10T Full Duplex Capable */
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#define QCA8075_ADVERTISE_10FULL 0x0040
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/* 100TX Half Duplex Capable */
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#define QCA8075_ADVERTISE_100HALF 0x0080
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/* 100TX Full Duplex Capable */
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#define QCA8075_ADVERTISE_100FULL 0x0100
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/* 100T4 Capable */
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#define QCA8075_ADVERTISE_100T4 0x0200
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/* Pause operation desired */
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#define QCA8075_ADVERTISE_PAUSE 0x0400
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/* Asymmetric Pause Direction bit */
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#define QCA8075_ADVERTISE_ASYM_PAUSE 0x0800
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/* Remote Fault detected */
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#define QCA8075_ADVERTISE_REMOTE_FAULT 0x2000
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/* Next Page ability supported */
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#define QCA8075_ADVERTISE_NEXT_PAGE 0x8000
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/* 100TX Half Duplex Capable */
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#define QCA8075_ADVERTISE_1000HALF 0x0100
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/* 100TX Full Duplex Capable */
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#define QCA8075_ADVERTISE_1000FULL 0x0200
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#define QCA8075_ADVERTISE_ALL \
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(QCA8075_ADVERTISE_10HALF | QCA8075_ADVERTISE_10FULL | \
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QCA8075_ADVERTISE_100HALF | QCA8075_ADVERTISE_100FULL | \
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QCA8075_ADVERTISE_1000FULL)
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#define QCA8075_ADVERTISE_MEGA_ALL \
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(QCA8075_ADVERTISE_10HALF | QCA8075_ADVERTISE_10FULL | \
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QCA8075_ADVERTISE_100HALF | QCA8075_ADVERTISE_100FULL)
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#define QCA8075_BX_ADVERTISE_1000FULL 0x0020
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#define QCA8075_BX_ADVERTISE_1000HALF 0x0040
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#define QCA8075_BX_ADVERTISE_PAUSE 0x0080
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#define QCA8075_BX_ADVERTISE_ASYM_PAUSE 0x0100
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#define QCA8075_BX_ADVERTISE_ALL \
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(QCA8075_BX_ADVERTISE_ASYM_PAUSE | QCA8075_BX_ADVERTISE_PAUSE | \
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QCA8075_BX_ADVERTISE_1000HALF | QCA8075_BX_ADVERTISE_1000FULL)
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/* Link Partner ability offset:5 */
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/* Same as advertise selector */
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#define QCA8075_LINK_SLCT 0x001f
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/* Can do 10mbps half-duplex */
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#define QCA8075_LINK_10BASETX_HALF_DUPLEX 0x0020
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/* Can do 10mbps full-duplex */
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#define QCA8075_LINK_10BASETX_FULL_DUPLEX 0x0040
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/* Can do 100mbps half-duplex */
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#define QCA8075_LINK_100BASETX_HALF_DUPLEX 0x0080
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/* Can do 100mbps full-duplex */
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#define QCA8075_LINK_100BASETX_FULL_DUPLEX 0x0100
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/* Can do 1000mbps full-duplex */
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#define QCA8075_LINK_1000BASETX_FULL_DUPLEX 0x0800
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/* Can do 1000mbps half-duplex */
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#define QCA8075_LINK_1000BASETX_HALF_DUPLEX 0x0400
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/* 100BASE-T4 */
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#define QCA8075_LINK_100BASE4 0x0200
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/* PAUSE */
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#define QCA8075_LINK_PAUSE 0x0400
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/* Asymmetrical PAUSE */
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#define QCA8075_LINK_ASYPAUSE 0x0800
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/* Link partner faulted */
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#define QCA8075_LINK_RFAULT 0x2000
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/* Link partner acked us */
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#define QCA8075_LINK_LPACK 0x4000
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/* Next page bit */
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#define QCA8075_LINK_NPAGE 0x8000
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/* Auto-Negotiation Expansion Register offset:6 */
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/* Next Page Transmit Register offset:7 */
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/* Link partner Next Page Register offset:8 */
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/* 1000BASE-T Control Register offset:9 */
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/* Advertise 1000T HD capability */
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#define QCA8075_CTL_1000T_HD_CAPS 0x0100
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/* Advertise 1000T FD capability */
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#define QCA8075_CTL_1000T_FD_CAPS 0x0200
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/* 1=Repeater/switch device port 0=DTE device */
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#define QCA8075_CTL_1000T_REPEATER_DTE 0x0400
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/* 1=Configure PHY as Master 0=Configure PHY as Slave */
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#define QCA8075_CTL_1000T_MS_VALUE 0x0800
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/* 1=Master/Slave manual config value 0=Automatic Master/Slave config */
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#define QCA8075_CTL_1000T_MS_ENABLE 0x1000
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/* Normal Operation */
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#define QCA8075_CTL_1000T_TEST_MODE_NORMAL 0x0000
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/* Transmit Waveform test */
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#define QCA8075_CTL_1000T_TEST_MODE_1 0x2000
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/* Master Transmit Jitter test */
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#define QCA8075_CTL_1000T_TEST_MODE_2 0x4000
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/* Slave Transmit Jitter test */
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#define QCA8075_CTL_1000T_TEST_MODE_3 0x6000
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/* Transmitter Distortion test */
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#define QCA8075_CTL_1000T_TEST_MODE_4 0x8000
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#define QCA8075_CTL_1000T_SPEED_MASK 0x0300
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#define QCA8075_CTL_1000T_DEFAULT_CAP_MASK 0x0300
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/* 1000BASE-T Status Register offset:10 */
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/* LP is 1000T HD capable */
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#define QCA8075_STATUS_1000T_LP_HD_CAPS 0x0400
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/* LP is 1000T FD capable */
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#define QCA8075_STATUS_1000T_LP_FD_CAPS 0x0800
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/* Remote receiver OK */
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#define QCA8075_STATUS_1000T_REMOTE_RX_STATUS 0x1000
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/* Local receiver OK */
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#define QCA8075_STATUS_1000T_LOCAL_RX_STATUS 0x2000
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/* 1=Local TX is Master, 0=Slave */
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#define QCA8075_STATUS_1000T_MS_CONFIG_RES 0x4000
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#define QCA8075_STATUS_1000T_MS_CONFIG_FAULT 0x8000
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/* Master/Slave config fault */
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#define QCA8075_STATUS_1000T_REMOTE_RX_STATUS_SHIFT 12
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#define QCA8075_STATUS_1000T_LOCAL_RX_STATUS_SHIFT 13
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/* Phy Specific Control Register offset:16 */
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/* 1=Jabber Function disabled */
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#define QCA8075_CTL_JABBER_DISABLE 0x0001
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/* 1=Polarity Reversal enabled */
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#define QCA8075_CTL_POLARITY_REVERSAL 0x0002
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/* 1=SQE Test enabled */
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#define QCA8075_CTL_SQE_TEST 0x0004
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#define QCA8075_CTL_MAC_POWERDOWN 0x0008
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/* 1=CLK125 low, 0=CLK125 toggling
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#define QCA8075_CTL_CLK125_DISABLE 0x0010
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*/
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/* MDI Crossover Mode bits 6:5 */
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/* Manual MDI configuration */
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#define QCA8075_CTL_MDI_MANUAL_MODE 0x0000
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/* Manual MDIX configuration */
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#define QCA8075_CTL_MDIX_MANUAL_MODE 0x0020
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/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
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#define QCA8075_CTL_AUTO_X_1000T 0x0040
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/* Auto crossover enabled all speeds */
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#define QCA8075_CTL_AUTO_X_MODE 0x0060
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/* 1=Enable Extended 10BASE-T distance
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* (Lower 10BASE-T RX Threshold)
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* 0=Normal 10BASE-T RX Threshold */
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#define QCA8075_CTL_10BT_EXT_DIST_ENABLE 0x0080
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/* 1=5-Bit interface in 100BASE-TX
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* 0=MII interface in 100BASE-TX */
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#define QCA8075_CTL_MII_5BIT_ENABLE 0x0100
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/* 1=Scrambler disable */
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#define QCA8075_CTL_SCRAMBLER_DISABLE 0x0200
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/* 1=Force link good */
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#define QCA8075_CTL_FORCE_LINK_GOOD 0x0400
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/* 1=Assert CRS on Transmit */
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#define QCA8075_CTL_ASSERT_CRS_ON_TX 0x0800
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#define QCA8075_CTL_POLARITY_REVERSAL_SHIFT 1
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#define QCA8075_CTL_AUTO_X_MODE_SHIFT 5
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#define QCA8075_CTL_10BT_EXT_DIST_ENABLE_SHIFT 7
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/* Phy Specific status fields offset:17 */
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/* 1=Speed & Duplex resolved */
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#define QCA8075_STATUS_LINK_PASS 0x0400
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#define QCA8075_STATUS_RESOVLED 0x0800
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/* 1=Duplex 0=Half Duplex */
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#define QCA8075_STATUS_FULL_DUPLEX 0x2000
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/* Speed, bits 14:15 */
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#define QCA8075_STATUS_SPEED 0xC000
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#define QCA8075_STATUS_SPEED_MASK 0xC000
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/* 00=10Mbs */
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#define QCA8075_STATUS_SPEED_10MBS 0x0000
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/* 01=100Mbs */
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#define QCA8075_STATUS_SPEED_100MBS 0x4000
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/* 10=1000Mbs */
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#define QCA8075_STATUS_SPEED_1000MBS 0x8000
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#define QCA8075_SPEED_DUPLEX_RESOVLED(phy_status) \
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(((phy_status) & \
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(QCA8075_STATUS_RESOVLED)) == \
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(QCA8075_STATUS_RESOVLED))
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/*phy debug port1 register offset:29 */
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/*phy debug port2 register offset:30 */
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/*QCA8075 interrupt flag */
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#define QCA8075_INTR_SPEED_CHANGE 0x4000
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#define QCA8075_INTR_DUPLEX_CHANGE 0x2000
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#define QCA8075_INTR_STATUS_UP_CHANGE 0x0400
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#define QCA8075_INTR_STATUS_DOWN_CHANGE 0x0800
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#define QCA8075_INTR_BX_FX_STATUS_DOWN_CHANGE 0x0100
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#define QCA8075_INTR_BX_FX_STATUS_UP_CHANGE 0x0080
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#define QCA8075_INTR_MEDIA_STATUS_CHANGE 0x1000
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#define QCA8075_INTR_WOL 0x0001
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#define QCA8075_INTR_POE 0x0002
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#define QCA8075_PHY_PSGMII_REDUCE_SERDES_TX_AMP 0x8a
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#define QCA8075_DAC_CTRL_MASK 0x380
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#define QCA8075_PHY_MMD7_DAC_CTRL 0x801a
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#define QCA8075_DAC_CTRL_VALUE 0x280
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#define QCA8075_PHY_MMD7_NUM 7
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#define QCA8075_PSGMII_TX_DRIVER_1_CTRL 0xb
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#define QCA8075_PHY_MMD7_LED_1000_CTRL1 0x8076
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#define QCA8075_LED_1000_CTRL1_100_10_MASK 0x30
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#define RUN_CDT 0x8000
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#define CABLE_LENGTH_UNIT 0x0400
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#define QCA8075_MAX_TRIES 100
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#endif /* _QCA8075_PHY_H_ */
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