mirror of
https://github.com/plappermaul/realtek-doc.git
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630 lines
25 KiB
C
630 lines
25 KiB
C
/*
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* Copyright (c) 2015-2016, 2020 The Linux Foundation. All rights reserved.
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*
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* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _ATHRS17_PHY_H
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#define _ATHRS17_PHY_H
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/*****************/
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/* PHY Registers */
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/*****************/
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#define ATHR_PHY_CONTROL 0
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#define ATHR_PHY_STATUS 1
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#define ATHR_PHY_ID1 2
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#define ATHR_PHY_ID2 3
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#define ATHR_AUTONEG_ADVERT 4
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#define ATHR_LINK_PARTNER_ABILITY 5
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#define ATHR_AUTONEG_EXPANSION 6
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#define ATHR_NEXT_PAGE_TRANSMIT 7
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#define ATHR_LINK_PARTNER_NEXT_PAGE 8
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#define ATHR_1000BASET_CONTROL 9
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#define ATHR_1000BASET_STATUS 10
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#define ATHR_PHY_SPEC_CONTROL 16
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#define ATHR_PHY_SPEC_STATUS 17
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#define ATHR_DEBUG_PORT_ADDRESS 29
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#define ATHR_DEBUG_PORT_DATA 30
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/* ATHR_PHY_CONTROL fields */
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#define ATHR_CTRL_SOFTWARE_RESET 0x8000
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#define ATHR_CTRL_SPEED_LSB 0x2000
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#define ATHR_CTRL_AUTONEGOTIATION_ENABLE 0x1000
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#define ATHR_CTRL_RESTART_AUTONEGOTIATION 0x0200
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#define ATHR_CTRL_SPEED_FULL_DUPLEX 0x0100
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#define ATHR_CTRL_SPEED_MSB 0x0040
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#define ATHR_RESET_DONE(phy_control) \
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(((phy_control) & (ATHR_CTRL_SOFTWARE_RESET)) == 0)
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/* Phy status fields */
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#define ATHR_STATUS_AUTO_NEG_DONE 0x0020
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#define ATHR_AUTONEG_DONE(ip_phy_status) \
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(((ip_phy_status) & \
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(ATHR_STATUS_AUTO_NEG_DONE)) == \
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(ATHR_STATUS_AUTO_NEG_DONE))
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/* Link Partner ability */
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#define ATHR_LINK_100BASETX_FULL_DUPLEX 0x0100
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#define ATHR_LINK_100BASETX 0x0080
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#define ATHR_LINK_10BASETX_FULL_DUPLEX 0x0040
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#define ATHR_LINK_10BASETX 0x0020
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/* Advertisement register. */
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#define ATHR_ADVERTISE_NEXT_PAGE 0x8000
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#define ATHR_ADVERTISE_ASYM_PAUSE 0x0800
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#define ATHR_ADVERTISE_PAUSE 0x0400
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#define ATHR_ADVERTISE_100FULL 0x0100
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#define ATHR_ADVERTISE_100HALF 0x0080
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#define ATHR_ADVERTISE_10FULL 0x0040
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#define ATHR_ADVERTISE_10HALF 0x0020
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#define ATHR_ADVERTISE_ALL (ATHR_ADVERTISE_ASYM_PAUSE | ATHR_ADVERTISE_PAUSE | \
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ATHR_ADVERTISE_10HALF | ATHR_ADVERTISE_10FULL | \
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ATHR_ADVERTISE_100HALF | ATHR_ADVERTISE_100FULL)
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/* 1000BASET_CONTROL */
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#define ATHR_ADVERTISE_1000FULL 0x0200
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/* Phy Specific status fields */
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#define ATHER_STATUS_LINK_MASK 0xC000
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#define ATHER_STATUS_LINK_SHIFT 14
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#define ATHER_STATUS_FULL_DEPLEX 0x2000
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#define ATHR_STATUS_LINK_PASS 0x0400
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#define ATHR_STATUS_RESOVLED 0x0800
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/*phy debug port register */
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#define ATHER_DEBUG_SERDES_REG 5
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/* Serdes debug fields */
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#define ATHER_SERDES_BEACON 0x0100
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/* S17 CSR Registers */
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#define S17_ENABLE_CPU_BROADCAST (1 << 26)
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#define S17_PHY_LINK_CHANGE_REG 0x4
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#define S17_PHY_LINK_UP 0x400
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#define S17_PHY_LINK_DOWN 0x800
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#define S17_PHY_LINK_DUPLEX_CHANGE 0x2000
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#define S17_PHY_LINK_SPEED_CHANGE 0x4000
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#define S17_PHY_LINK_INTRS (PHY_LINK_UP | PHY_LINK_DOWN | PHY_LINK_DUPLEX_CHANGE | PHY_LINK_SPEED_CHANGE)
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#define S17_MASK_CTRL_REG 0x0000
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#define S17_P0PAD_MODE_REG 0x0004
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#define S17_P5PAD_MODE_REG 0x0008
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#define S17_P6PAD_MODE_REG 0x000c
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#define S17_PWS_REG 0x0010
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#define S17_GLOBAL_INT0_REG 0x0020
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#define S17_GLOBAL_INT1_REG 0x0024
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#define S17_GLOBAL_INTMASK0 0x0028
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#define S17_GLOBAL_INTMASK1 0x002c
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#define S17_MODULE_EN_REG 0x0030
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#define S17_MIB_REG 0x0034
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#define S17_INTF_HIADDR_REG 0x0038
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#define S17_MDIO_CTRL_REG 0x003c
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#define S17_BIST_CTRL_REG 0x0040
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#define S17_BIST_REC_REG 0x0044
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#define S17_SERVICE_REG 0x0048
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#define S17_LED_CTRL0_REG 0x0050
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#define S17_LED_CTRL1_REG 0x0054
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#define S17_LED_CTRL2_REG 0x0058
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#define S17_LED_CTRL3_REG 0x005c
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#define S17_MACADDR0_REG 0x0060
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#define S17_MACADDR1_REG 0x0064
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#define S17_MAX_FRAME_SIZE_REG 0x0078
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#define S17_P0STATUS_REG 0x007c
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#define S17_P1STATUS_REG 0x0080
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#define S17_P2STATUS_REG 0x0084
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#define S17_P3STATUS_REG 0x0088
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#define S17_P4STATUS_REG 0x008c
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#define S17_P5STATUS_REG 0x0090
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#define S17_P6STATUS_REG 0x0094
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#define S17_HDRCTRL_REG 0x0098
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#define S17_P0HDRCTRL_REG 0x009c
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#define S17_P1HDRCTRL_REG 0x00A0
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#define S17_P2HDRCTRL_REG 0x00a4
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#define S17_P3HDRCTRL_REG 0x00a8
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#define S17_P4HDRCTRL_REG 0x00ac
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#define S17_P5HDRCTRL_REG 0x00b0
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#define S17_P6HDRCTRL_REG 0x00b4
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#define S17_SGMII_CTRL_REG 0x00e0
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#define S17_MAC_PWR_REG 0x00e4
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#define S17_EEE_CTRL_REG 0x0100
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/* ACL Registers */
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#define S17_ACL_FUNC0_REG 0x0400
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#define S17_ACL_FUNC1_REG 0x0404
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#define S17_ACL_FUNC2_REG 0x0408
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#define S17_ACL_FUNC3_REG 0x040c
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#define S17_ACL_FUNC4_REG 0x0410
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#define S17_ACL_FUNC5_REG 0x0414
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#define S17_PRIVATE_IP_REG 0x0418
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#define S17_P0VLAN_CTRL0_REG 0x0420
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#define S17_P0VLAN_CTRL1_REG 0x0424
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#define S17_P1VLAN_CTRL0_REG 0x0428
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#define S17_P1VLAN_CTRL1_REG 0x042c
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#define S17_P2VLAN_CTRL0_REG 0x0430
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#define S17_P2VLAN_CTRL1_REG 0x0434
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#define S17_P3VLAN_CTRL0_REG 0x0438
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#define S17_P3VLAN_CTRL1_REG 0x043c
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#define S17_P4VLAN_CTRL0_REG 0x0440
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#define S17_P4VLAN_CTRL1_REG 0x0444
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#define S17_P5VLAN_CTRL0_REG 0x0448
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#define S17_P5VLAN_CTRL1_REG 0x044c
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#define S17_P6VLAN_CTRL0_REG 0x0450
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#define S17_P6VLAN_CTRL1_REG 0x0454
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/* Table Lookup Registers */
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#define S17_ATU_DATA0_REG 0x0600
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#define S17_ATU_DATA1_REG 0x0604
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#define S17_ATU_DATA2_REG 0x0608
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#define S17_ATU_FUNC_REG 0x060C
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#define S17_VTU_FUNC0_REG 0x0610
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#define S17_VTU_FUNC1_REG 0x0614
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#define S17_ARL_CTRL_REG 0x0618
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#define S17_GLOFW_CTRL0_REG 0x0620
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#define S17_GLOFW_CTRL1_REG 0x0624
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#define S17_GLOLEARN_LIMIT_REG 0x0628
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#define S17_TOS_PRIMAP_REG0 0x0630
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#define S17_TOS_PRIMAP_REG1 0x0634
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#define S17_TOS_PRIMAP_REG2 0x0638
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#define S17_TOS_PRIMAP_REG3 0x063c
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#define S17_TOS_PRIMAP_REG4 0x0640
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#define S17_TOS_PRIMAP_REG5 0x0644
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#define S17_TOS_PRIMAP_REG6 0x0648
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#define S17_TOS_PRIMAP_REG7 0x064c
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#define S17_VLAN_PRIMAP_REG0 0x0650
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#define S17_LOOP_CHECK_REG 0x0654
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#define S17_P0LOOKUP_CTRL_REG 0x0660
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#define S17_P0PRI_CTRL_REG 0x0664
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#define S17_P0LEARN_LMT_REG 0x0668
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#define S17_P1LOOKUP_CTRL_REG 0x066c
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#define S17_P1PRI_CTRL_REG 0x0670
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#define S17_P1LEARN_LMT_REG 0x0674
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#define S17_P2LOOKUP_CTRL_REG 0x0678
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#define S17_P2PRI_CTRL_REG 0x067c
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#define S17_P2LEARN_LMT_REG 0x0680
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#define S17_P3LOOKUP_CTRL_REG 0x0684
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#define S17_P3PRI_CTRL_REG 0x0688
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#define S17_P3LEARN_LMT_REG 0x068c
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#define S17_P4LOOKUP_CTRL_REG 0x0690
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#define S17_P4PRI_CTRL_REG 0x0694
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#define S17_P4LEARN_LMT_REG 0x0698
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#define S17_P5LOOKUP_CTRL_REG 0x069c
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#define S17_P5PRI_CTRL_REG 0x06a0
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#define S17_P5LEARN_LMT_REG 0x06a4
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#define S17_P6LOOKUP_CTRL_REG 0x06a8
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#define S17_P6PRI_CTRL_REG 0x06ac
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#define S17_P6LEARN_LMT_REG 0x06b0
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#define S17_GLO_TRUNK_CTRL0_REG 0x0700
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#define S17_GLO_TRUNK_CTRL1_REG 0x0704
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#define S17_GLO_TRUNK_CTRL2_REG 0x0708
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/* Queue Management Registers */
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#define S17_PORT0_HOL_CTRL0 0x0970
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#define S17_PORT0_HOL_CTRL1 0x0974
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#define S17_PORT1_HOL_CTRL0 0x0978
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#define S17_PORT1_HOL_CTRL1 0x097c
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#define S17_PORT2_HOL_CTRL0 0x0980
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#define S17_PORT2_HOL_CTRL1 0x0984
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#define S17_PORT3_HOL_CTRL0 0x0988
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#define S17_PORT3_HOL_CTRL1 0x098c
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#define S17_PORT4_HOL_CTRL0 0x0990
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#define S17_PORT4_HOL_CTRL1 0x0994
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#define S17_PORT5_HOL_CTRL0 0x0998
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#define S17_PORT5_HOL_CTRL1 0x099c
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#define S17_PORT6_HOL_CTRL0 0x09a0
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#define S17_PORT6_HOL_CTRL1 0x09a4
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/* Port flow control registers */
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#define S17_P0_FLCTL_REG 0x09b0
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#define S17_P1_FLCTL_REG 0x09b4
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#define S17_P2_FLCTL_REG 0x09b8
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#define S17_P3_FLCTL_REG 0x09bc
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#define S17_P4_FLCTL_REG 0x09c0
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#define S17_P5_FLCTL_REG 0x09c4
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/* Packet Edit registers */
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#define S17_PKT_EDIT_CTRL 0x0c00
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#define S17_P0Q_REMAP_REG0 0x0c40
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#define S17_P0Q_REMAP_REG1 0x0c44
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#define S17_P1Q_REMAP_REG0 0x0c48
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#define S17_P2Q_REMAP_REG0 0x0c4c
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#define S17_P3Q_REMAP_REG0 0x0c50
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#define S17_P4Q_REMAP_REG0 0x0c54
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#define S17_P5Q_REMAP_REG0 0x0c58
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#define S17_P5Q_REMAP_REG1 0x0c5c
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#define S17_P6Q_REMAP_REG0 0x0c60
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#define S17_P6Q_REMAP_REG1 0x0c64
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#define S17_ROUTER_VID0 0x0c70
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#define S17_ROUTER_VID1 0x0c74
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#define S17_ROUTER_VID2 0x0c78
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#define S17_ROUTER_VID3 0x0c7c
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#define S17_ROUTER_EG_VLAN_MODE 0x0c80
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/* L3 Registers */
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#define S17_HROUTER_CTRL_REG 0x0e00
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#define S17_HROUTER_PBCTRL0_REG 0x0e04
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#define S17_HROUTER_PBCTRL1_REG 0x0e08
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#define S17_HROUTER_PBCTRL2_REG 0x0e0c
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#define S17_WCMP_HASH_TABLE0_REG 0x0e10
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#define S17_WCMP_HASH_TABLE1_REG 0x0e14
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#define S17_WCMP_HASH_TABLE2_REG 0x0e18
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#define S17_WCMP_HASH_TABLE3_REG 0x0e1c
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#define S17_WCMP_NHOP_TABLE0_REG 0x0e20
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#define S17_WCMP_NHOP_TABLE1_REG 0x0e24
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#define S17_WCMP_NHOP_TABLE2_REG 0x0e28
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#define S17_WCMP_NHOP_TABLE3_REG 0x0e2c
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#define S17_ARP_ENTRY_CTRL_REG 0x0e30
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#define S17_ARP_USECNT_REG 0x0e34
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#define S17_HNAT_CTRL_REG 0x0e38
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#define S17_NAPT_ENTRY_CTRL0_REG 0x0e3c
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#define S17_NAPT_ENTRY_CTRL1_REG 0x0e40
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#define S17_NAPT_USECNT_REG 0x0e44
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#define S17_ENTRY_EDIT_DATA0_REG 0x0e48
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#define S17_ENTRY_EDIT_DATA1_REG 0x0e4c
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#define S17_ENTRY_EDIT_DATA2_REG 0x0e50
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#define S17_ENTRY_EDIT_DATA3_REG 0x0e54
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#define S17_ENTRY_EDIT_CTRL_REG 0x0e58
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#define S17_HNAT_PRIVATE_IP_REG 0x0e5c
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/* MIB counters */
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#define S17_MIB_PORT0 0x1000
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#define S17_MIB_PORT1 0x1100
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#define S17_MIB_PORT2 0x1200
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#define S17_MIB_PORT3 0x1300
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#define S17_MIB_PORT4 0x1400
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#define S17_MIB_PORT5 0x1500
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#define S17_MIB_PORT6 0x1600
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#define S17_MIB_COUNTER_ENABLE (1 << 0)
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#define S17_MIB_NON_CLEAR (1 << 20)
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#define S17_MIB_RXBROAD 0x0
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#define S17_MIB_RXPAUSE 0x4
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#define S17_MIB_RXMULTI 0x8
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#define S17_MIB_RXFCSERR 0xC
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#define S17_MIB_RXALIGNERR 0x10
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#define S17_MIB_RXUNDERSIZE 0x14
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#define S17_MIB_RXFRAG 0x18
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#define S17_MIB_RX64B 0x1C
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#define S17_MIB_RX128B 0x20
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#define S17_MIB_RX256B 0x24
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#define S17_MIB_RX512B 0x28
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#define S17_MIB_RX1024B 0x2C
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#define S17_MIB_RX1518B 0x30
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#define S17_MIB_RXMAXB 0x34
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#define S17_MIB_RXTOOLONG 0x38
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#define S17_MIB_RXBYTE1 0x3C
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#define S17_MIB_RXBYTE2 0x40
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#define S17_MIB_RXOVERFLOW 0x4C
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#define S17_MIB_FILTERED 0x50
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#define S17_MIB_TXBROAD 0x54
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#define S17_MIB_TXPAUSE 0x58
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#define S17_MIB_TXMULTI 0x5C
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#define S17_MIB_TXUNDERRUN 0x60
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#define S17_MIB_TX64B 0x64
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#define S17_MIB_TX128B 0x68
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#define S17_MIB_TX256B 0x6c
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#define S17_MIB_TX512B 0x70
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#define S17_MIB_TX1024B 0x74
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#define S17_MIB_TX1518B 0x78
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#define S17_MIB_TXMAXB 0x7C
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#define S17_MIB_TXOVERSIZE 0x80
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#define S17_MIB_TXBYTE1 0x84
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#define S17_MIB_TXBYTE2 0x88
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#define S17_MIB_TXCOL 0x8C
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#define S17_MIB_TXABORTCOL 0x90
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#define S17_MIB_TXMULTICOL 0x94
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#define S17_MIB_TXSINGLECOL 0x98
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#define S17_MIB_TXEXCDEFER 0x9C
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#define S17_MIB_TXDEFER 0xA0
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#define S17_MIB_TXLATECOL 0xA4
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/* Register fields */
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#define S17_CHIPID_V1_0 0x1201
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#define S17_CHIPID_V1_1 0x1202
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#define S17_MASK_CTRL_SOFT_RET (1 << 31)
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#define S17_GLOBAL_INT0_ACL_INI_INT (1<<29)
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#define S17_GLOBAL_INT0_LOOKUP_INI_INT (1<<28)
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#define S17_GLOBAL_INT0_QM_INI_INT (1<<27)
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#define S17_GLOBAL_INT0_MIB_INI_INT (1<<26)
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#define S17_GLOBAL_INT0_OFFLOAD_INI_INT (1<<25)
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#define S17_GLOBAL_INT0_HARDWARE_INI_DONE (1<<24)
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#define S17_GLOBAL_INITIALIZED_STATUS \
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( \
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S17_GLOBAL_INT0_ACL_INI_INT | \
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S17_GLOBAL_INT0_LOOKUP_INI_INT | \
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S17_GLOBAL_INT0_QM_INI_INT | \
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S17_GLOBAL_INT0_MIB_INI_INT | \
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S17_GLOBAL_INT0_OFFLOAD_INI_INT | \
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S17_GLOBAL_INT0_HARDWARE_INI_DONE \
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)
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#define S17_MAC0_MAC_MII_RXCLK_SEL (1 << 0)
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#define S17_MAC0_MAC_MII_TXCLK_SEL (1 << 1)
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#define S17_MAC0_MAC_MII_EN (1 << 2)
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#define S17_MAC0_MAC_GMII_RXCLK_SEL (1 << 4)
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#define S17_MAC0_MAC_GMII_TXCLK_SEL (1 << 5)
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#define S17_MAC0_MAC_GMII_EN (1 << 6)
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#define S17_MAC0_SGMII_EN (1 << 7)
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#define S17_MAC0_PHY_MII_RXCLK_SEL (1 << 8)
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#define S17_MAC0_PHY_MII_TXCLK_SEL (1 << 9)
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#define S17_MAC0_PHY_MII_EN (1 << 10)
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#define S17_MAC0_PHY_MII_PIPE_SEL (1 << 11)
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#define S17_MAC0_PHY_GMII_RXCLK_SEL (1 << 12)
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#define S17_MAC0_PHY_GMII_TXCLK_SEL (1 << 13)
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#define S17_MAC0_PHY_GMII_EN (1 << 14)
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#define S17_MAC0_RGMII_RXCLK_SHIFT 20
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#define S17_MAC0_RGMII_TXCLK_SHIFT 22
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#define S17_MAC0_RGMII_RXCLK_DELAY (1 << 24)
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#define S17_MAC0_RGMII_TXCLK_DELAY (1 << 25)
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#define S17_MAC0_RGMII_EN (1 << 26)
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#define S17_MAC5_MAC_MII_RXCLK_SEL (1 << 0)
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#define S17_MAC5_MAC_MII_TXCLK_SEL (1 << 1)
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#define S17_MAC5_MAC_MII_EN (1 << 2)
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#define S17_MAC5_PHY_MII_RXCLK_SEL (1 << 8)
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#define S17_MAC5_PHY_MII_TXCLK_SEL (1 << 9)
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#define S17_MAC5_PHY_MII_EN (1 << 10)
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#define S17_MAC5_PHY_MII_PIPE_SEL (1 << 11)
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#define S17_MAC5_RGMII_RXCLK_SHIFT 20
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#define S17_MAC5_RGMII_TXCLK_SHIFT 22
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#define S17_MAC5_RGMII_RXCLK_DELAY (1 << 24)
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#define S17_MAC5_RGMII_TXCLK_DELAY (1 << 25)
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#define S17_MAC5_RGMII_EN (1 << 26)
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#define S17_MAC6_MAC_MII_RXCLK_SEL (1 << 0)
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#define S17_MAC6_MAC_MII_TXCLK_SEL (1 << 1)
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#define S17_MAC6_MAC_MII_EN (1 << 2)
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#define S17_MAC6_MAC_GMII_RXCLK_SEL (1 << 4)
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#define S17_MAC6_MAC_GMII_TXCLK_SEL (1 << 5)
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#define S17_MAC6_MAC_GMII_EN (1 << 6)
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#define S17_MAC6_SGMII_EN (1 << 7)
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#define S17_MAC6_PHY_MII_RXCLK_SEL (1 << 8)
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#define S17_MAC6_PHY_MII_TXCLK_SEL (1 << 9)
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#define S17_MAC6_PHY_MII_EN (1 << 10)
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#define S17_MAC6_PHY_MII_PIPE_SEL (1 << 11)
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#define S17_MAC6_PHY_GMII_RXCLK_SEL (1 << 12)
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#define S17_MAC6_PHY_GMII_TXCLK_SEL (1 << 13)
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#define S17_MAC6_PHY_GMII_EN (1 << 14)
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#define S17_PHY4_GMII_EN (1 << 16)
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#define S17_PHY4_RGMII_EN (1 << 17)
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#define S17_PHY4_MII_EN (1 << 18)
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#define S17_MAC6_RGMII_RXCLK_SHIFT 20
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#define S17_MAC6_RGMII_TXCLK_SHIFT 22
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#define S17_MAC6_RGMII_RXCLK_DELAY (1 << 24)
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#define S17_MAC6_RGMII_TXCLK_DELAY (1 << 25)
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#define S17_MAC6_RGMII_EN (1 << 26)
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#define S17_SPEED_10M (0 << 0)
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#define S17_SPEED_100M (1 << 0)
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#define S17_SPEED_1000M (2 << 0)
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#define S17_TXMAC_EN (1 << 2)
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#define S17_RXMAC_EN (1 << 3)
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#define S17_TX_FLOW_EN (1 << 4)
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#define S17_RX_FLOW_EN (1 << 5)
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#define S17_DUPLEX_FULL (1 << 6)
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#define S17_DUPLEX_HALF (0 << 6)
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#define S17_TX_HALF_FLOW_EN (1 << 7)
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#define S17_LINK_EN (1 << 9)
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#define S17_FLOW_LINK_EN (1 << 12)
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#define S17_PORT_STATUS_DEFAULT (S17_SPEED_1000M | S17_TXMAC_EN | \
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S17_RXMAC_EN | S17_TX_FLOW_EN | \
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S17_RX_FLOW_EN | S17_DUPLEX_FULL | \
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S17_TX_HALF_FLOW_EN)
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#define S17_PORT_STATUS_AZ_DEFAULT (S17_SPEED_1000M | S17_TXMAC_EN | \
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S17_RXMAC_EN | S17_TX_FLOW_EN | \
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S17_RX_FLOW_EN | S17_DUPLEX_FULL)
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#define S17_HDRLENGTH_SEL (1 << 16)
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#define S17_HDR_VALUE 0xAAAA
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#define S17_TXHDR_MODE_NO 0
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#define S17_TXHDR_MODE_MGM 1
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#define S17_TXHDR_MODE_ALL 2
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#define S17_RXHDR_MODE_NO (0 << 2)
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#define S17_RXHDR_MODE_MGM (1 << 2)
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#define S17_RXHDR_MODE_ALL (2 << 2)
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#define S17_CPU_PORT_EN (1 << 10)
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#define S17_PPPOE_REDIR_EN (1 << 8)
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#define S17_MIRROR_PORT_SHIFT 4
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#define S17_IGMP_COPY_EN (1 << 3)
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#define S17_RIP_COPY_EN (1 << 2)
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#define S17_EAPOL_REDIR_EN (1 << 0)
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#define S17_IGMP_JOIN_LEAVE_DP_SHIFT 24
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#define S17_BROAD_DP_SHIFT 16
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#define S17_MULTI_FLOOD_DP_SHIFT 8
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#define S17_UNI_FLOOD_DP_SHIFT 0
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#define S17_IGMP_JOIN_LEAVE_DPALL (0x7f << S17_IGMP_JOIN_LEAVE_DP_SHIFT)
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#define S17_BROAD_DPALL (0x7f << S17_BROAD_DP_SHIFT)
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#define S17_MULTI_FLOOD_DPALL (0x7f << S17_MULTI_FLOOD_DP_SHIFT)
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#define S17_UNI_FLOOD_DPALL (0x7f << S17_UNI_FLOOD_DP_SHIFT)
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|
|
|
#define S17_PWS_CHIP_AR8327 (1 << 30)
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|
#define S17c_PWS_SERDES_ANEG_DISABLE (1 << 7)
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|
|
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/* S17_PHY_CONTROL fields */
|
|
#define S17_CTRL_SOFTWARE_RESET 0x8000
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|
#define S17_CTRL_SPEED_LSB 0x2000
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|
#define S17_CTRL_AUTONEGOTIATION_ENABLE 0x1000
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|
#define S17_CTRL_RESTART_AUTONEGOTIATION 0x0200
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|
#define S17_CTRL_SPEED_FULL_DUPLEX 0x0100
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|
#define S17_CTRL_SPEED_MSB 0x0040
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|
|
|
/* For EEE_CTRL_REG */
|
|
#define S17_LPI_DISABLE_P1 (1 << 4)
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|
#define S17_LPI_DISABLE_P2 (1 << 6)
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|
#define S17_LPI_DISABLE_P3 (1 << 8)
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|
#define S17_LPI_DISABLE_P4 (1 << 10)
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|
#define S17_LPI_DISABLE_P5 (1 << 12)
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|
#define S17_LPI_DISABLE_ALL 0x1550
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|
|
|
/* For MMD register control */
|
|
#define S17_MMD_FUNC_ADDR (0 << 14)
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|
#define S17_MMD_FUNC_DATA (1 << 14)
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|
#define S17_MMD_FUNC_DATA_2 (2 << 14)
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|
#define S17_MMD_FUNC_DATA_3 (3 << 14)
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|
|
|
/* For phyInfo_t azFeature */
|
|
#define S17_8023AZ_PHY_ENABLED (1 << 0)
|
|
#define S17_8023AZ_PHY_LINKED (1 << 1)
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|
|
|
/* Queue Management registe fields */
|
|
#define S17_HOL_CTRL0_LAN 0x2a008888 /* egress priority 8, eg_portq = 0x2a */
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|
#define S17_HOL_CTRL0_WAN 0x2a666666 /* egress priority 6, eg_portq = 0x2a */
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|
#define S17_HOL_CTRL1_DEFAULT 0xc6 /* enable HOL control */
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|
|
|
/* Packet Edit register fields */
|
|
#define S17_ROUTER_EG_UNMOD 0x0 /* unmodified */
|
|
#define S17_ROUTER_EG_WOVLAN 0x1 /* without VLAN */
|
|
#define S17_ROUTER_EG_WVLAN 0x2 /* with VLAN */
|
|
#define S17_ROUTER_EG_UNTOUCH 0x3 /* untouched */
|
|
#define S17_ROUTER_EG_MODE_DEFAULT 0x01111111 /* all ports without VLAN */
|
|
|
|
#define S17_RESET_DONE(phy_control) \
|
|
(((phy_control) & (S17_CTRL_SOFTWARE_RESET)) == 0)
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|
|
|
/* Phy status fields */
|
|
#define S17_STATUS_AUTO_NEG_DONE 0x0020
|
|
|
|
#define S17_AUTONEG_DONE(ip_phy_status) \
|
|
(((ip_phy_status) & \
|
|
(S17_STATUS_AUTO_NEG_DONE)) == \
|
|
(S17_STATUS_AUTO_NEG_DONE))
|
|
|
|
/* Link Partner ability */
|
|
#define S17_LINK_100BASETX_FULL_DUPLEX 0x0100
|
|
#define S17_LINK_100BASETX 0x0080
|
|
#define S17_LINK_10BASETX_FULL_DUPLEX 0x0040
|
|
#define S17_LINK_10BASETX 0x0020
|
|
|
|
/* Advertisement register. */
|
|
#define S17_ADVERTISE_NEXT_PAGE 0x8000
|
|
#define S17_ADVERTISE_ASYM_PAUSE 0x0800
|
|
#define S17_ADVERTISE_PAUSE 0x0400
|
|
#define S17_ADVERTISE_100FULL 0x0100
|
|
#define S17_ADVERTISE_100HALF 0x0080
|
|
#define S17_ADVERTISE_10FULL 0x0040
|
|
#define S17_ADVERTISE_10HALF 0x0020
|
|
|
|
#define S17_ADVERTISE_ALL (S17_ADVERTISE_ASYM_PAUSE | S17_ADVERTISE_PAUSE | \
|
|
S17_ADVERTISE_10HALF | S17_ADVERTISE_10FULL | \
|
|
S17_ADVERTISE_100HALF | S17_ADVERTISE_100FULL)
|
|
|
|
/* 1000BASET_CONTROL */
|
|
#define S17_ADVERTISE_1000FULL 0x0200
|
|
|
|
/* Phy Specific status fields */
|
|
#define S17_STATUS_LINK_MASK 0xC000
|
|
#define S17_STATUS_LINK_SHIFT 14
|
|
#define S17_STATUS_FULL_DEPLEX 0x2000
|
|
#define S17_STATUS_LINK_PASS 0x0400
|
|
#define S17_STATUS_RESOLVED 0x0800
|
|
#define S17_STATUS_LINK_10M 0
|
|
#define S17_STATUS_LINK_100M 1
|
|
#define S17_STATUS_LINK_1000M 2
|
|
|
|
#define S17_GLOBAL_INT_PHYMASK (1 << 15)
|
|
|
|
#define S17_PHY_LINK_UP 0x400
|
|
#define S17_PHY_LINK_DOWN 0x800
|
|
#define S17_PHY_LINK_DUPLEX_CHANGE 0x2000
|
|
#define S17_PHY_LINK_SPEED_CHANGE 0x4000
|
|
|
|
/* For Port flow control registers */
|
|
#define S17_PORT_FLCTL_XON_DEFAULT (0x3a << 16)
|
|
#define S17_PORT_FLCTL_XOFF_DEFAULT (0x4a)
|
|
|
|
/* Module enable Register */
|
|
#define S17_MODULE_L3_EN (1 << 2)
|
|
#define S17_MODULE_ACL_EN (1 << 1)
|
|
#define S17_MODULE_MIB_EN (1 << 0)
|
|
|
|
/* MIB Function Register 1 */
|
|
#define S17_MIB_FUNC_ALL (3 << 24)
|
|
#define S17_MIB_CPU_KEEP (1 << 20)
|
|
#define S17_MIB_BUSY (1 << 17)
|
|
#define S17_MIB_AT_HALF_EN (1 << 16)
|
|
#define S17_MIB_TIMER_DEFAULT 0x100
|
|
|
|
#define S17_MAC_MAX 7
|
|
|
|
/* MAC power selector bit definitions */
|
|
#define S17_RGMII0_1_8V (1 << 19)
|
|
#define S17_RGMII1_1_8V (1 << 18)
|
|
|
|
/* SGMII_CTRL bit definitions */
|
|
#define S17c_SGMII_EN_LCKDT (1 << 0)
|
|
#define S17c_SGMII_EN_PLL (1 << 1)
|
|
#define S17c_SGMII_EN_RX (1 << 2)
|
|
#define S17c_SGMII_EN_TX (1 << 3)
|
|
#define S17c_SGMII_EN_SD (1 << 4)
|
|
#define S17c_SGMII_BW_HIGH (1 << 6)
|
|
#define S17c_SGMII_SEL_CLK125M (1 << 7)
|
|
#define S17c_SGMII_TXDR_CTRL_600mV (1 << 10)
|
|
#define S17c_SGMII_CDR_BW_8 (3 << 13)
|
|
#define S17c_SGMII_DIS_AUTO_LPI_25M (1 << 16)
|
|
#define S17c_SGMII_MODE_CTRL_SGMII_PHY (1 << 22)
|
|
#define S17c_SGMII_PAUSE_SG_TX_EN_25M (1 << 24)
|
|
#define S17c_SGMII_ASYM_PAUSE_25M (1 << 25)
|
|
#define S17c_SGMII_PAUSE_25M (1 << 26)
|
|
#define S17c_SGMII_HALF_DUPLEX_25M (1 << 30)
|
|
#define S17c_SGMII_FULL_DUPLEX_25M (1 << 31)
|
|
|
|
#ifndef BOOL
|
|
#define BOOL int
|
|
#endif
|
|
|
|
/*add feature define here*/
|
|
|
|
#ifdef CONFIG_AR7242_S17_PHY
|
|
#undef HEADER_REG_CONF
|
|
#undef HEADER_EN
|
|
#endif
|
|
|
|
#define LINK_UP 0x400
|
|
#define LINK(_data) (_data & LINK_UP)? "Up" : "Down"
|
|
#define DUPLEX(_data) (_data & 0x2000)?\
|
|
"Full duplex" : "Half duplex"
|
|
#define SPEED(_data) ((_data & 0xC000) >> 12)
|
|
#define SPEED_1000M (1 << 3)
|
|
#define SPEED_100M (1 << 2)
|
|
|
|
#define S17C_MAX_PORT 4
|
|
typedef struct {
|
|
u32 mac_pwr;
|
|
int port_count;
|
|
int chip_detect;
|
|
u32 port_phy_address[S17C_MAX_PORT];
|
|
bool update;
|
|
bool skip_vlan;
|
|
u32 pad0_mode;
|
|
u32 pad5_mode;
|
|
u32 pad6_mode;
|
|
u32 port0;
|
|
u32 sgmii_ctrl;
|
|
u32 port0_status;
|
|
u32 port6_status;
|
|
} ipq_s17c_swt_cfg_t;
|
|
|
|
#endif
|
|
|