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136 lines
3.2 KiB
Text
136 lines
3.2 KiB
Text
#ifndef PBLR_H
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#define PBLR_H
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#define _sizeof_nand_dma_buf(max_chunk_size) (sizeof(nand_dma_buf_t)+(max_chunk_size))
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// the function to export to u-boot
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#define pblr_printf (parameters._pblr_printf)
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#define parameters sram_parameters
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#define parameter_soc_rwp ((soc_t*)(&(parameters.soc)))
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#define para_flash_info (parameters.soc.flash_info)
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#define flash_info_num_chunk_per_block \
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((para_flash_info.num_page_per_block)/(para_flash_info.page_per_chunk))
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#define soc_configuration (*(const soc_configuration_t*)(SYSTEM_STARTUP_CADDR+SOC_CONF_OFFSET))
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// the table is stored just right after the first cache line the lplr
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inline static void
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_set_flags(u32_t *arr, u32_t i) {
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unsigned idx=i/(8*sizeof(u32_t));
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i &= (8*sizeof(u32_t))-1;
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arr[idx] |= 1UL << i;
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}
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inline static int
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_get_flags(u32_t *arr, u32_t i) {
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unsigned idx=i/(8*sizeof(u32_t));
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i &= (8*sizeof(u32_t))-1;
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return (arr[idx] & (1UL << i)) != 0;
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}
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#if (OTTO_NAND_FLASH == 1)
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#define MAX_WRITE_TRY 6 // when writing a chunk, the maximal number to try
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inline static int
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bbt_is_bad_block(u32_t chunk_id) {
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// assert(parameters.bbt_valid)
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u32_t *bbt=parameters.bbt;
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u32_t b=chunk_id/flash_info_num_chunk_per_block;
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return _get_flags(bbt, b);
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}
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inline static u8_t*
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pbldr_spare_bbi(spare_u *spare) {
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return &(spare->u8_oob[para_flash_info.bbi_swap_offset]);
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}
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#endif
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inline static void
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pbldr_bset(void *buf,u8_t value, u32_t nbyte) {
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u8_t *b=(u8_t *)buf;
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u8_t *e=b+nbyte;
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while (b!=e) *(b++)=value;
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}
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inline static void
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pbldr_bzero(void *buf, u32_t nbyte) {
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//u8_t *b=(u8_t *)buf;
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//u8_t *e=b+nbyte;
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//while (b!=e) *(b++)=0;
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pbldr_bset(buf,0,nbyte);
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}
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inline static void
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pbldr_wzero(void *buf, u32_t nword) {
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u32_t *b=(u32_t *)buf;
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u32_t *e=b+nword;
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while (b!=e) *(b++)=0;
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}
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inline static void
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pbldr_wzero_range(u32_t *buf, u32_t *buf_end) {
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while (buf!=buf_end) *(buf++)=0;
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}
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inline static void
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pbldr_memcpy(void *dst, const void *src, u32_t nbyte) {
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u8_t *d=(u8_t*)dst;
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const u8_t *s=(const u8_t *)src;
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const u8_t *e=s+nbyte;
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while (s!=e) *(d++)=*(s++);
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}
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inline static void
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pbldr_wmemcpy(void *dst, const void *src, u32_t nword) {
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u32_t *d=(u32_t*)dst;
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const u32_t *s=(const u32_t *)src;
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const u32_t *e=s+nword;
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while (s!=e) *(d++)=*(s++);
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}
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inline static int
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pbldr_memcmp(const void *a, const void *b, u32_t nbyte) {
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const u8_t *x=a;
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const u8_t *y=b;
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const u8_t *z=x+nbyte;
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while (x!=z)
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if (*(x++)!=*(y++))
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return -1;
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return 0;
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}
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inline static int
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pbldr_wmemcmp(const void *a, const void *b, u32_t nword) {
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const u32_t *x=a;
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const u32_t *y=b;
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const u32_t *z=x+nword;
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while (x!=z)
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if (*(x++)!=*(y++))
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return -1;
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return 0;
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}
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// return 0: successful
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inline static int
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check_if_all_one(u32_t *flags_arr, u32_t n) {
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int c;
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for (c=n;c>=0;c--)
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if (_get_flags(flags_arr, c)==0) return -1;
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return 0;
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}
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inline static u8_t*
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plr_addr_by_chunck_id(u32_t cid, u32_t chunk_size) {
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return (u8_t*)SYSTEM_STARTUP_CADDR+LPLR_DMA_SIZE+cid*chunk_size;
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}
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inline static u8_t*
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blr_addr_by_chunck_id(u32_t cid, u32_t chunk_size) {
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return (u8_t*)DRAM_CADDR+cid*chunk_size;
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}
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#if 0
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inline static void
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pbldr_dma_cache_inv_range(void *addr, u32_t nbyte) {
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parameters._dcache_flush_inv_range(addr,addr+nbyte-1);
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}
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#endif
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#endif //PBLR_H
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