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https://github.com/plappermaul/realtek-doc.git
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529 lines
21 KiB
C
529 lines
21 KiB
C
/*
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* Copyright (C) 2009-2016 Realtek Semiconductor Corp.
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* All Rights Reserved.
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*
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* This program is the proprietary software of Realtek Semiconductor
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* Corporation and/or its licensors, and only be used, duplicated,
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* modified or distributed under the authorized license from Realtek.
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*
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* ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER
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* THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED.
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*
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* $Revision: 88229 $
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* $Date: 2018-05-23 19:33:47 +0800 (Wed, 23 May 2018) $
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*
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* Purpose : I2C master driver.
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*
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* Feature : The file have include the following module and sub-modules
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* 1) i2c read and write
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*
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*/
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#include <common/rt_autoconf.h>
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#include <osal/sem.h>
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#include <osal/lib.h>
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#include <common/debug/rt_log.h>
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#include <drv/i2c/i2c.h>
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#include <ioal/ioal_init.h>
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#include <ioal/mem32.h>
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#include <hal/chipdef/chip.h>
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#include <ioal/ioal_init.h>
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#include <hwp/hw_profile.h>
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#include <private/drv/swcore/swcore_rtl9300.h>
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#include <private/drv/i2c/i2c_rtl9300.h>
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#include <private/drv/i2c/i2c_software_drv.h>
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#include <drv/gpio/generalCtrl_gpio.h>
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extern i2c_devInfo_t gI2C_dev[RTK_MAX_NUM_OF_UNIT][I2C_DEV_ID_END];
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static uint8 i2c_init[RTK_MAX_NUM_OF_UNIT] = {INIT_NOT_COMPLETED};
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static int32 r9300_data_write(uint32 unit, i2c_devConf_t *i2c_dev, uint8 *pBuff)
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{
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uint32 data_width, reg_idx,reg_offset, buff_offset;
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uint32 reg_data;
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int32 ret = RT_ERR_OK;
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data_width = gI2C_dev[unit][i2c_dev->device_id].conf.data_width;
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buff_offset = 0;
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reg_idx = 0;
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switch(gI2C_dev[unit][i2c_dev->device_id].conf.i2c_interface_id){
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case I2C_INTF_CONTROLLER_ID0:
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while(data_width)
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{
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reg_offset = 0;
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reg_data = 0;
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while((data_width) && (reg_offset < 4))
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{
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reg_data |= ((*(pBuff + buff_offset)) << (reg_offset*8));
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reg_offset++;
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buff_offset++;
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data_width --;
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}
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switch(reg_idx){
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case 0:
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ret = ioal_mem32_write(unit, RTL9300_I2C_MST1_DATA_WORD0_ADDR, reg_data);
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break;
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case 1:
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ret = ioal_mem32_write(unit, RTL9300_I2C_MST1_DATA_WORD1_ADDR, reg_data);
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break;
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case 2:
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ret = ioal_mem32_write(unit, RTL9300_I2C_MST1_DATA_WORD2_ADDR, reg_data);
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break;
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case 3:
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ret = ioal_mem32_write(unit, RTL9300_I2C_MST1_DATA_WORD3_ADDR, reg_data);
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break;
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default:
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return RT_ERR_FAILED;
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}
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reg_idx++;
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}
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break;
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case I2C_INTF_CONTROLLER_ID1:
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while(data_width)
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{
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reg_offset = 0;
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reg_data = 0;
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while((data_width) && (reg_offset < 4))
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{
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reg_data |= ((*(pBuff + buff_offset)) << (reg_offset*8));
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reg_offset++;
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buff_offset++;
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data_width --;
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}
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switch(reg_idx){
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case 0:
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ret = ioal_mem32_write(unit, RTL9300_I2C_MST2_DATA_WORD0_ADDR, reg_data);
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break;
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case 1:
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ret = ioal_mem32_write(unit, RTL9300_I2C_MST2_DATA_WORD1_ADDR, reg_data);
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break;
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case 2:
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ret = ioal_mem32_write(unit, RTL9300_I2C_MST2_DATA_WORD2_ADDR, reg_data);
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break;
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case 3:
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ret = ioal_mem32_write(unit, RTL9300_I2C_MST2_DATA_WORD3_ADDR, reg_data);
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break;
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default:
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return RT_ERR_FAILED;
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}
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reg_idx++;
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}
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break;
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default:
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return RT_ERR_FAILED;
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}
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return ret;
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}
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static int32 r9300_data_read(uint32 unit, i2c_devConf_t *i2c_dev, uint8 *pBuff)
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{
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uint32 data_width, reg_idx,reg_offset, buff_offset;
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uint32 reg_data;
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int32 ret = RT_ERR_OK;
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data_width = gI2C_dev[unit][i2c_dev->device_id].conf.data_width;
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buff_offset = 0;
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reg_idx = 0;
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switch(gI2C_dev[unit][i2c_dev->device_id].conf.i2c_interface_id){
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case I2C_INTF_CONTROLLER_ID0:
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while(data_width)
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{
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switch(reg_idx){
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case 0:
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ret = ioal_mem32_read(unit, RTL9300_I2C_MST1_DATA_WORD0_ADDR, ®_data);
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break;
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case 1:
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ret = ioal_mem32_read(unit, RTL9300_I2C_MST1_DATA_WORD1_ADDR, ®_data);
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break;
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case 2:
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ret = ioal_mem32_read(unit, RTL9300_I2C_MST1_DATA_WORD2_ADDR, ®_data);
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break;
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case 3:
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ret = ioal_mem32_read(unit, RTL9300_I2C_MST1_DATA_WORD3_ADDR, ®_data);
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break;
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default:
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return RT_ERR_FAILED;
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}
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reg_offset = 0;
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while((data_width) && (reg_offset < 4))
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{
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reg_data = (reg_data >> (reg_offset*8));
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*(pBuff + buff_offset) = (reg_data & RTL9300_I2C_MST1_DATA_WORD0_DATA0_MASK);
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reg_offset++;
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buff_offset++;
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data_width --;
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}
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reg_idx++;
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}
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break;
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case I2C_INTF_CONTROLLER_ID1:
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while(data_width)
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{
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switch(reg_idx){
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case 0:
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ret = ioal_mem32_read(unit, RTL9300_I2C_MST2_DATA_WORD0_ADDR, ®_data);
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break;
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case 1:
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ret = ioal_mem32_read(unit, RTL9300_I2C_MST2_DATA_WORD1_ADDR, ®_data);
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break;
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case 2:
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ret = ioal_mem32_read(unit, RTL9300_I2C_MST2_DATA_WORD2_ADDR, ®_data);
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break;
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case 3:
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ret = ioal_mem32_read(unit, RTL9300_I2C_MST2_DATA_WORD3_ADDR, ®_data);
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break;
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default:
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return RT_ERR_FAILED;
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}
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reg_offset = 0;
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while((data_width) && (reg_offset < 4))
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{
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reg_data = (reg_data >> (reg_offset*8));
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*(pBuff + buff_offset) = (reg_data & RTL9300_I2C_MST2_DATA_WORD0_DATA0_MASK);
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reg_offset++;
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buff_offset++;
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data_width --;
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}
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reg_idx++;
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}
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break;
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default:
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return RT_ERR_FAILED;
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}
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return ret;
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}
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int32 r9300_i2c_execution(uint32 unit, uint32 intf_id)
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{
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uint32 reg_data;
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int32 ret = RT_ERR_OK;
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switch(intf_id){
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case I2C_INTF_CONTROLLER_ID0:
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/* Set Trig */
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ret = ioal_mem32_read(unit, RTL9300_I2C_MST1_CTRL1_ADDR, ®_data);
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reg_data |= RTL9300_I2C_MST1_CTRL1_I2C_TRIG_MASK;
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ret = ioal_mem32_write(unit, RTL9300_I2C_MST1_CTRL1_ADDR, reg_data);
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/* Check Complete or Not */
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while(1)
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{
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ioal_mem32_read(unit, RTL9300_I2C_MST1_CTRL1_ADDR, ®_data);
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if((reg_data & RTL9300_I2C_MST1_CTRL1_I2C_TRIG_MASK) == 0)
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break;
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}
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/* Check Failed or Not*/
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ret = ioal_mem32_read(unit, RTL9300_I2C_MST1_CTRL1_ADDR, ®_data);
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if((reg_data & RTL9300_I2C_MST1_CTRL1_I2C_FAIL_MASK) != 0)
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{
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return RT_ERR_FAILED;
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}
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break;
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case I2C_INTF_CONTROLLER_ID1:
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/* Set Trig */
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ret = ioal_mem32_read(unit, RTL9300_I2C_MST2_CTRL1_ADDR, ®_data);
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reg_data |= RTL9300_I2C_MST2_CTRL1_I2C_TRIG_MASK;
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ret = ioal_mem32_write(unit, RTL9300_I2C_MST2_CTRL1_ADDR, reg_data);
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/* Check Complete or Not */
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while(1)
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{
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ioal_mem32_read(unit, RTL9300_I2C_MST2_CTRL1_ADDR, ®_data);
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if((reg_data & RTL9300_I2C_MST2_CTRL1_I2C_TRIG_MASK) == 0)
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break;
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}
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/* Check Failed or Not*/
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ret = ioal_mem32_read(unit, RTL9300_I2C_MST2_CTRL1_ADDR, ®_data);
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if((reg_data & RTL9300_I2C_MST2_CTRL1_I2C_FAIL_MASK) != 0)
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return RT_ERR_FAILED;
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break;
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default:
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return RT_ERR_FAILED;
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}
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return ret;
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}
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int32 r9300_i2c_init(uint32 unit)
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{
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RT_INIT_REENTRY_CHK(i2c_init[unit]);
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i2c_init[unit] = INIT_COMPLETED;
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return RT_ERR_OK;
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}
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int32 r9300_i2c_dev_init(uint32 unit, i2c_devConf_t *i2c_dev)
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{
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uint32 reg_data;
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uint32 mapping_freg;
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int32 ret;
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uint32 i2c_addrwidth, i2c_datawidth;
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if((gI2C_dev[unit][i2c_dev->device_id].conf.sda_pin_id >= I2C_9300_INTF_CONTROLLER_SDA_END)&&(gI2C_dev[unit][i2c_dev->device_id].conf.i2c_interface_id != I2C_INTF_SOFTWARE_DRV_ID))
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return RT_ERR_FAILED;
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switch(gI2C_dev[unit][i2c_dev->device_id].conf.i2c_interface_id){
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case I2C_INTF_CONTROLLER_ID0:
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/* Set SCL pin */
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ret = ioal_mem32_read(unit, RTL9300_I2C_MST1_CTRL1_ADDR, ®_data);
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reg_data |= RTL9300_I2C_MST1_CTRL1_GPIO8_SCL_SEL_MASK;
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/* Set SDA pin*/
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if((HWP_CHIP_REV(unit) < 3) && HWP_9300_FAMILY_ID(unit) && IF_CHIP_TYPE_1(unit))
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{
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reg_data &= ~RTL9300_INT_I2C_MST1_CTRL1_SDA_OUT_SEL_MASK;
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reg_data |= (gI2C_dev[unit][i2c_dev->device_id].conf.sda_pin_id << RTL9300_INT_I2C_MST1_CTRL1_SDA_OUT_SEL_OFFSET);
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}else{
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reg_data &= ~RTL9300_I2C_MST1_CTRL1_SDA_OUT_SEL_MASK;
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reg_data |= (gI2C_dev[unit][i2c_dev->device_id].conf.sda_pin_id << RTL9300_I2C_MST1_CTRL1_SDA_OUT_SEL_OFFSET);
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}
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ret = ioal_mem32_write(unit, RTL9300_I2C_MST1_CTRL1_ADDR, reg_data);
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/* Set Slave Device Address*/
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ret = ioal_mem32_read(unit, RTL9300_I2C_MST1_CTRL2_ADDR, ®_data);
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reg_data &= ~RTL9300_I2C_MST1_CTRL2_DEV_ADDR_MASK;
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reg_data |= (gI2C_dev[unit][i2c_dev->device_id].conf.dev_addr << RTL9300_I2C_MST1_CTRL2_DEV_ADDR_OFFSET);
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/* Set Data Width */
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reg_data &= ~RTL9300_I2C_MST1_CTRL2_DATA_WIDTH_MASK;
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reg_data |= ((gI2C_dev[unit][i2c_dev->device_id].conf.data_width - 1) << RTL9300_I2C_MST1_CTRL2_DATA_WIDTH_OFFSET);
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/* Set Memory Address Width */
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reg_data &= ~RTL9300_I2C_MST1_CTRL2_MEM_ADDR_WIDTH_MASK;
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reg_data |= ((gI2C_dev[unit][i2c_dev->device_id].conf.mem_addr_width) << RTL9300_I2C_MST1_CTRL2_MEM_ADDR_WIDTH_OFFSET);
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/* Set SCL Freq */
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switch(gI2C_dev[unit][i2c_dev->device_id].conf.clk_freq){
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case I2C_CLK_STD_MODE:
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mapping_freg = 0;
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break;
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case I2C_CLK_FAST_MODE:
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mapping_freg = 1;
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break;
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case I2C_CLK_RT_50K:
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mapping_freg = 3;
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break;
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case I2C_CLK_RT_2P5M:
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mapping_freg = 2;
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break;
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default:
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return RT_ERR_FAILED;
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}
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reg_data &= ~RTL9300_I2C_MST1_CTRL2_SCL_FREQ_MASK;
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reg_data |= ((mapping_freg) << RTL9300_I2C_MST1_CTRL2_SCL_FREQ_OFFSET);
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/* Set RD MODE */
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switch(gI2C_dev[unit][i2c_dev->device_id].conf.read_type){
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case I2C_INTF_READ_TYPE_RANDOM:
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reg_data &= ~RTL9300_INT_I2C_MST1_CTRL2_RD_MODE_MASK;
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break;
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case I2C_INTF_READ_TYPE_SEQUENTIAL:
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reg_data |= RTL9300_INT_I2C_MST1_CTRL2_RD_MODE_MASK;
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break;
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default:
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return RT_ERR_FAILED;
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}
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ret = ioal_mem32_write(unit, RTL9300_I2C_MST1_CTRL2_ADDR, reg_data);
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break;
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case I2C_INTF_CONTROLLER_ID1:
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/* Set SCL pin */
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ret = ioal_mem32_read(unit, RTL9300_I2C_MST2_CTRL1_ADDR, ®_data);
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reg_data |= RTL9300_I2C_MST2_CTRL1_GPIO17_SCL_SEL_MASK;
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/* Set SDA pin*/
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if((HWP_CHIP_REV(unit) < 3) && HWP_9300_FAMILY_ID(unit) && IF_CHIP_TYPE_1(unit))
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{
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reg_data &= ~RTL9300_INT_I2C_MST2_CTRL1_SDA_OUT_SEL_MASK;
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reg_data |= (gI2C_dev[unit][i2c_dev->device_id].conf.sda_pin_id << RTL9300_INT_I2C_MST2_CTRL1_SDA_OUT_SEL_OFFSET);
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}else{
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reg_data &= ~RTL9300_I2C_MST2_CTRL1_SDA_OUT_SEL_MASK;
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reg_data |= (gI2C_dev[unit][i2c_dev->device_id].conf.sda_pin_id << RTL9300_I2C_MST2_CTRL1_SDA_OUT_SEL_OFFSET);
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}
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ret = ioal_mem32_write(unit, RTL9300_I2C_MST2_CTRL1_ADDR, reg_data);
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/* Set Slave Device Address*/
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ret = ioal_mem32_read(unit, RTL9300_I2C_MST2_CTRL2_ADDR, ®_data);
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reg_data &= ~RTL9300_I2C_MST2_CTRL2_DEV_ADDR_MASK;
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reg_data |= (gI2C_dev[unit][i2c_dev->device_id].conf.dev_addr << RTL9300_I2C_MST2_CTRL2_DEV_ADDR_OFFSET);
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/* Set Data Width */
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reg_data &= ~RTL9300_I2C_MST2_CTRL2_DATA_WIDTH_MASK;
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reg_data |= ((gI2C_dev[unit][i2c_dev->device_id].conf.data_width - 1) << RTL9300_I2C_MST2_CTRL2_DATA_WIDTH_OFFSET);
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/* Set Memory Address Width */
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reg_data &= ~RTL9300_I2C_MST2_CTRL2_MEM_ADDR_WIDTH_MASK;
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reg_data |= ((gI2C_dev[unit][i2c_dev->device_id].conf.mem_addr_width) << RTL9300_I2C_MST2_CTRL2_MEM_ADDR_WIDTH_OFFSET);
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/* Set SCL Freq */
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switch(gI2C_dev[unit][i2c_dev->device_id].conf.clk_freq){
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case I2C_CLK_STD_MODE:
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mapping_freg = 0;
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break;
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case I2C_CLK_FAST_MODE:
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mapping_freg = 1;
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break;
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case I2C_CLK_RT_50K:
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mapping_freg = 3;
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break;
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case I2C_CLK_RT_2P5M:
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mapping_freg = 2;
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break;
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default:
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return RT_ERR_FAILED;
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}
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reg_data &= ~RTL9300_I2C_MST2_CTRL2_SCL_FREQ_MASK;
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reg_data |= ((mapping_freg) << RTL9300_I2C_MST2_CTRL2_SCL_FREQ_OFFSET);
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/* Set RD MODE */
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switch(gI2C_dev[unit][i2c_dev->device_id].conf.read_type){
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case I2C_INTF_READ_TYPE_RANDOM:
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reg_data &= ~RTL9300_INT_I2C_MST1_CTRL2_RD_MODE_MASK;
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break;
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case I2C_INTF_READ_TYPE_SEQUENTIAL:
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reg_data |= RTL9300_INT_I2C_MST1_CTRL2_RD_MODE_MASK;
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break;
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default:
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return RT_ERR_FAILED;
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}
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ret = ioal_mem32_write(unit, RTL9300_I2C_MST2_CTRL2_ADDR, reg_data);
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break;
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case I2C_INTF_SOFTWARE_DRV_ID:
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if((ret = drv_software_i2c_init(i2c_dev->scl_dev, i2c_dev->scl_pin_id, i2c_dev->sda_dev, i2c_dev->sda_pin_id, i2c_dev->device_id)) != RT_ERR_OK)
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{
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return RT_ERR_FAILED;
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}
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if(((i2c_dev->mem_addr_width) >= I2C_ADDR_WIDTH_BYTE_END) || ((i2c_dev->data_width) >= I2C_DATA_WIDTH_BYTE_END))
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{
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return RT_ERR_FAILED;
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}
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i2c_addrwidth = i2c_dev->mem_addr_width;
|
|
i2c_datawidth = i2c_dev->data_width;
|
|
|
|
drv_software_i2c_type_set(i2c_addrwidth, i2c_datawidth, i2c_dev->dev_addr, i2c_dev->scl_delay, i2c_dev->device_id);
|
|
return RT_ERR_OK;
|
|
break;
|
|
default:
|
|
return RT_ERR_FAILED;
|
|
}
|
|
|
|
/* Set Related SDA pin to I2C function*/
|
|
ret = ioal_mem32_read(unit, RTL9300_I2C_MST_GLB_CTRL_ADDR, ®_data);
|
|
reg_data |= (1 << gI2C_dev[unit][i2c_dev->device_id].conf.sda_pin_id);
|
|
ret = ioal_mem32_write(unit, RTL9300_I2C_MST_GLB_CTRL_ADDR, reg_data);
|
|
|
|
return RT_ERR_OK;
|
|
}
|
|
|
|
|
|
int32 r9300_i2c_read(uint32 unit, i2c_devConf_t *i2c_dev, uint32 reg_idex, uint8 *pBuff)
|
|
{
|
|
uint32 reg_data;
|
|
int32 ret;
|
|
i2c_devConf_t read_dev;
|
|
|
|
osal_memcpy(&read_dev, &gI2C_dev[unit][i2c_dev->device_id].conf, sizeof(i2c_devConf_t));
|
|
r9300_i2c_dev_init(unit, &read_dev);
|
|
|
|
switch(gI2C_dev[unit][i2c_dev->device_id].conf.i2c_interface_id){
|
|
case I2C_INTF_CONTROLLER_ID0:
|
|
/* Set Memory Address */
|
|
ret = ioal_mem32_read(unit, RTL9300_I2C_MST1_CTRL1_ADDR, ®_data);
|
|
/* Set Read OP*/
|
|
if((HWP_CHIP_REV(unit) < 3) && HWP_9300_FAMILY_ID(unit) && IF_CHIP_TYPE_1(unit))
|
|
{
|
|
reg_data &= ~RTL9300_INT_I2C_MST1_CTRL1_MEM_ADDR_MASK;
|
|
reg_data |= (reg_idex << RTL9300_INT_I2C_MST1_CTRL1_MEM_ADDR_OFFSET);
|
|
reg_data |= RTL9300_I2C_MST1_CTRL1_RWOP_MASK;
|
|
}else{
|
|
reg_data &= ~RTL9300_I2C_MST1_CTRL1_MEM_ADDR_MASK;
|
|
reg_data |= (reg_idex << RTL9300_I2C_MST1_CTRL1_MEM_ADDR_OFFSET);
|
|
reg_data &= ~RTL9300_I2C_MST1_CTRL1_RWOP_MASK;
|
|
}
|
|
ret = ioal_mem32_write(unit, RTL9300_I2C_MST1_CTRL1_ADDR, reg_data);
|
|
break;
|
|
case I2C_INTF_CONTROLLER_ID1:
|
|
/* Set Memory Address */
|
|
ret = ioal_mem32_read(unit, RTL9300_I2C_MST2_CTRL1_ADDR, ®_data);
|
|
/* Set Read OP*/
|
|
if((HWP_CHIP_REV(unit) < 3) && HWP_9300_FAMILY_ID(unit) && IF_CHIP_TYPE_1(unit))
|
|
{
|
|
reg_data &= ~RTL9300_INT_I2C_MST2_CTRL1_MEM_ADDR_MASK;
|
|
reg_data |= (reg_idex << RTL9300_INT_I2C_MST2_CTRL1_MEM_ADDR_OFFSET);
|
|
reg_data |= RTL9300_I2C_MST2_CTRL1_RWOP_MASK;
|
|
}else{
|
|
reg_data &= ~RTL9300_I2C_MST2_CTRL1_MEM_ADDR_MASK;
|
|
reg_data |= (reg_idex << RTL9300_I2C_MST2_CTRL1_MEM_ADDR_OFFSET);
|
|
reg_data &= ~RTL9300_I2C_MST2_CTRL1_RWOP_MASK;
|
|
}
|
|
ret = ioal_mem32_write(unit, RTL9300_I2C_MST2_CTRL1_ADDR, reg_data);
|
|
break;
|
|
case I2C_INTF_SOFTWARE_DRV_ID:
|
|
if((ret = drv_software_i2c_read(reg_idex, pBuff, i2c_dev->device_id)) != RT_ERR_OK)
|
|
{
|
|
return RT_ERR_FAILED;
|
|
}
|
|
return RT_ERR_OK;
|
|
break;
|
|
default:
|
|
return RT_ERR_FAILED;
|
|
}
|
|
|
|
ret = r9300_i2c_execution(unit, gI2C_dev[unit][i2c_dev->device_id].conf.i2c_interface_id);
|
|
if(ret == RT_ERR_FAILED)
|
|
return ret;
|
|
|
|
ret = r9300_data_read(unit, i2c_dev, pBuff);;
|
|
return ret;
|
|
}
|
|
|
|
int32 r9300_i2c_write(uint32 unit, i2c_devConf_t *i2c_dev, uint32 reg_idex, uint8 *pBuff)
|
|
{
|
|
uint32 reg_data;
|
|
int32 ret;
|
|
i2c_devConf_t write_dev;
|
|
|
|
osal_memcpy(&write_dev, &gI2C_dev[unit][i2c_dev->device_id].conf, sizeof(i2c_devConf_t));
|
|
r9300_i2c_dev_init(unit, &write_dev);
|
|
|
|
switch(gI2C_dev[unit][i2c_dev->device_id].conf.i2c_interface_id){
|
|
case I2C_INTF_CONTROLLER_ID0:
|
|
/* Set Memory Address */
|
|
ret = ioal_mem32_read(unit, RTL9300_I2C_MST1_CTRL1_ADDR, ®_data);
|
|
reg_data &= ~RTL9300_I2C_MST1_CTRL1_MEM_ADDR_MASK;
|
|
reg_data |= (reg_idex << RTL9300_I2C_MST1_CTRL1_MEM_ADDR_OFFSET);
|
|
/* Set Write OP*/
|
|
if((HWP_CHIP_REV(unit) < 3) && HWP_9300_FAMILY_ID(unit) && IF_CHIP_TYPE_1(unit))
|
|
reg_data &= ~RTL9300_I2C_MST1_CTRL1_RWOP_MASK;
|
|
else
|
|
reg_data |= RTL9300_I2C_MST1_CTRL1_RWOP_MASK;
|
|
ret = ioal_mem32_write(unit, RTL9300_I2C_MST1_CTRL1_ADDR, reg_data);
|
|
break;
|
|
case I2C_INTF_CONTROLLER_ID1:
|
|
/* Set Memory Address */
|
|
ret = ioal_mem32_read(unit, RTL9300_I2C_MST2_CTRL1_ADDR, ®_data);
|
|
reg_data &= ~RTL9300_I2C_MST2_CTRL1_MEM_ADDR_MASK;
|
|
reg_data |= (reg_idex << RTL9300_I2C_MST2_CTRL1_MEM_ADDR_OFFSET);
|
|
/* Set Write OP*/
|
|
if((HWP_CHIP_REV(unit) < 3) && HWP_9300_FAMILY_ID(unit) && IF_CHIP_TYPE_1(unit))
|
|
reg_data &= ~RTL9300_I2C_MST2_CTRL1_RWOP_MASK;
|
|
else
|
|
reg_data |= RTL9300_I2C_MST2_CTRL1_RWOP_MASK;
|
|
ret = ioal_mem32_write(unit, RTL9300_I2C_MST2_CTRL1_ADDR, reg_data);
|
|
break;
|
|
case I2C_INTF_SOFTWARE_DRV_ID:
|
|
if((ret = drv_software_i2c_write(reg_idex, pBuff, i2c_dev->device_id)) != RT_ERR_OK)
|
|
{
|
|
return RT_ERR_FAILED;
|
|
}
|
|
return RT_ERR_OK;
|
|
break;
|
|
default:
|
|
return RT_ERR_FAILED;
|
|
}
|
|
|
|
ret = r9300_data_write(unit, i2c_dev, pBuff);
|
|
if(ret == RT_ERR_FAILED)
|
|
return ret;
|
|
|
|
ret = r9300_i2c_execution(unit, gI2C_dev[unit][i2c_dev->device_id].conf.i2c_interface_id);
|
|
|
|
return ret;
|
|
}
|
|
|