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# Summary
RTL8214FC/RTL8218B (maybe generic RTL821x) Register Layout RTL8214FC/RTL8218B (maybe generic RTL821x) Register Layout
This is a sum up of what we got from the comments in the GPL sources. Additionally some SerDes registers where identified that work similar like the RTL838x/RTL839x built in SerDes. This is a sum up of what we got from the comments in the GPL sources. Additionally some SerDes registers where identified that work similar like the RTL838x/RTL839x built in SerDes.
# Basic registers
These basic registers are organized in pages of 32. Each page knows registers 0x00-0x1F These basic registers are organized in pages of 32. Each page knows registers 0x00-0x1F
Page | Register | Bits | Feature | Documentation Page | Register | Bits | Feature | Documentation
@ -36,10 +39,14 @@ Page | Register | Bits | Feature | Documentation
**Page** | **Register** | **Bits** | **unknown** | **Page** | **Register** | **Bits** | **unknown** |
0xb82 | 0x10 | 04:04 | ENABLE_PATCH | patch step 1: set to 1 to gain SerDEs access, go over to 0xb80:0x10 0xb82 | 0x10 | 04:04 | ENABLE_PATCH | patch step 1: set to 1 to gain SerDEs access, go over to 0xb80:0x10
# Special registers
These additional/internal registers are organized in pages of 8. Each page knows registers 0x10-0x17. Their "absoulte" address can be calucalted by the formula page * 8 + (register - 16). It seems as if they are for the whole chip package and only accessed via the first port. These additional/internal registers are organized in pages of 8. Each page knows registers 0x10-0x17. Their "absoulte" address can be calucalted by the formula page * 8 + (register - 16). It seems as if they are for the whole chip package and only accessed via the first port.
Page | Register | Bits | Feature | Documentation Page | Register | Bits | Feature | Documentation
--- | --- | --- | --- | --- --- | --- | --- | --- | ---
**Page** | **Register** | **Bits** | **Unknown Fiber** | **Absolute 0x1303**
0x260 | 0x13 | 12:08 | PHY_ADDRESS | Start PHY address. Do not modified it!
**Page** | **Register** | **Bits** | **Unknown** | **Absolute 0x1308** **Page** | **Register** | **Bits** | **Unknown** | **Absolute 0x1308**
0x261 | 0x10 | 14:13 | UNKOWN_RESET | write 0x3 and afterwards 0x0 0x261 | 0x10 | 14:13 | UNKOWN_RESET | write 0x3 and afterwards 0x0
**Page** | **Register** | **Bits** | **Unknown** | **Absolute 0x130b** **Page** | **Register** | **Bits** | **Unknown** | **Absolute 0x130b**
@ -177,6 +184,10 @@ Page | Register | Bits | Feature | Documentation
0x42e | 0x11 | 15:00 | 0x42e | 0x11 | 15:00 |
**Page** | **Register** | **Bits** | **Unknown SerDes - page unknown** | **Absolute 0x2261** **Page** | **Register** | **Bits** | **Unknown SerDes - page unknown** | **Absolute 0x2261**
0x44c | 0x11 | 15:00 | | This is some unknown PLL register - write 0x4000 to disable ring PLL 0x44c | 0x11 | 15:00 | | This is some unknown PLL register - write 0x4000 to disable ring PLL
**Page** | **Register** | **Bits** | **Unknown SerDes - page unknown** | **Absolute 0x2269**
0x44d | 0x11 | 15:00 | |
**Page** | **Register** | **Bits** | **Unknown SerDes - page unknown** | **Absolute 0x2271**
0x44e | 0x11 | 15:00 | | Some unknown register for fiber jitter on RTL8214FC
**Page** | **Register** | **Bits** | **Unknown filter register** | **Absolute 0x2310** **Page** | **Register** | **Bits** | **Unknown filter register** | **Absolute 0x2310**
0x462 | 0x10 | 13:12 | OFFSET_CALIBRATION 0x462 | 0x10 | 13:12 | OFFSET_CALIBRATION
**Page** | **Register** | **Bits** | **Unknown filter register 1** | **Absolute 0x2322** **Page** | **Register** | **Bits** | **Unknown filter register 1** | **Absolute 0x2322**