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@ -40,6 +40,10 @@ These additional/internal registers are organized in pages of 8. Each page knows
Page | Register | Bits | Feature | Documentation
--- | --- | --- | --- | ---
**Page** | **Register** | **Bits** | **Unknown** | **Absolute 0x1308**
0x261 | 0x10 | 14:13 | UNKOWN_RESET | write 0x3 and afterwards 0x0
**Page** | **Register** | **Bits** | **Unknown** | **Absolute 0x130b**
0x261 | 0x13 | 13:10 | DIS_FIBER_TX | each bit for on of ports 3-0 to disable (1) or enable (0) fiber tx
**Page** | **Register** | **Bits** | **PTP feature** | **Absolute 0x1600**
0x2C0 | 0x10 | 15:00 | PTP_TIME_NSEC_L
0x2C0 | 0x11 | 15:00 | PTP_TIME_NSEC_H
@ -175,12 +179,15 @@ Page | Register | Bits | Feature | Documentation
0x44c | 0x11 | 15:00 | | This is some unknown PLL register - write 0x4000 to disable ring PLL
**Page** | **Register** | **Bits** | **Unknown filter register** | **Absolute 0x2310**
0x462 | 0x10 | 13:12 | OFFSET_CALIBRATION
**Page** | **Register** | **Bits** | **Unknown filter register** | **Absolute 0x2322**
**Page** | **Register** | **Bits** | **Unknown filter register 1** | **Absolute 0x2322**
0x464 | 0x12 | 15:11 | FILTER_0
0x464 | 0x12 | 10:07 | FORCE
**Page** | **Register** | **Bits** | **Unknown filter register 2** | **Absolute 0x2323**
0x464 | 0x13 | 14:10 | FILTER_3
0x464 | 0x13 | 09:05 | FILTER_2
0x464 | 0x13 | 04:00 | FILTER_1
**Page** | **Register** | **Bits** | **Unknown** | **Absolute 0x2327**
0x464 | 0x17 | 15:15 | UNKNOWN_RESET | write 1 and 0 to do some reset
**Page** | **Register** | **Bits** | **Unknown CMU register** | **Absolute 0x233c**
0x467 | 0x14 | 15:0 | | For CMU reset write 0x143d, 0x3c15, 0x3c17, 0x0000
**Page** | **Register** | **Bits** | **PHYCR1** | **Absolute 0x2520**