From d295ac929bbe6521a9998718f3479c00b4a76264 Mon Sep 17 00:00:00 2001
From: plappermaul <plappermaul@users.noreply.github.com>
Date: Thu, 26 Jun 2025 19:57:54 +0200
Subject: [PATCH] Update RTL8218B.md

---
 RTL8218B.md | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/RTL8218B.md b/RTL8218B.md
index 3187f0f7..c51433ae 100644
--- a/RTL8218B.md
+++ b/RTL8218B.md
@@ -8,6 +8,12 @@ Page | Register | Bits | Feature | Documentation
 --- | --- | --- | --- | ---
 **Page** | **Register** | **Bits** | **unknown** | 
 0xa42 | 0x14 | 07:07 | 500M_EEE_ABILITY
+**Page** | **Register** | **Bits** | **unknown** | 
+0xa44 | 0x11 | 09:09 | RETRY_DOWN_SPEED_500
+0xa44 | 0x11 | 05:05 | UTP_DOWN_SPEED | 0 = 100MBit
+0xa44 | 0x11 | 03:03 | UTP_DOWN_SPEED_ENABLE
+0xa44 | 0x11 | 02:02 | 2PAIR_AUTO_DOWNSPEED
+
 
 These additional/internal registers are organized in pages of 8. Each page knows registers 0x10-0x17. Their "absoulte" address can be calucalted by the formula page * 8 + (register - 16). It seems as if they are for the whole chip package and only accessed via the first port.