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Update RTL8218B.md

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@ -25,7 +25,7 @@ Page | Register | Bits | MAC SerDes 0 - page 0 | Description
0x404 | 0x13 | 12:12 | SEL_DEG 0x404 | 0x13 | 12:12 | SEL_DEG
0x404 | 0x13 | 11:08 | REG_CALIB_OK_CNT 0x404 | 0x13 | 11:08 | REG_CALIB_OK_CNT
0x404 | 0x13 | 07:07 | EXT_PWR_CTL 0x404 | 0x13 | 07:07 | EXT_PWR_CTL
0x404 | 0x13 | 06:06 | SOFT_RST 0x404 | 0x13 | 06:06 | SOFT_RST | Set to 1 then to 0 to run digital soft reset
0x404 | 0x13 | 05:05 | CLR_SOFT_RSTB 0x404 | 0x13 | 05:05 | CLR_SOFT_RSTB
0x404 | 0x13 | 04:00 | CMA_RQ 0x404 | 0x13 | 04:00 | CMA_RQ
**Page** | **Register** | **Bits** | **MAC SerDes 0 - page 4** | **Description** **Page** | **Register** | **Bits** | **MAC SerDes 0 - page 4** | **Description**
@ -93,3 +93,5 @@ Page | Register | Bits | MAC SerDes 0 - page 0 | Description
0x424 | 0x17 | 08:08 | CFG_MARK_TXSCR_ERR | 0x424 | 0x17 | 08:08 | CFG_MARK_TXSCR_ERR |
0x424 | 0x17 | 07:04 | BYP_START | 0x424 | 0x17 | 07:04 | BYP_START |
0x424 | 0x17 | 03:00 | BYP_END | 0x424 | 0x17 | 03:00 | BYP_END |
**Page** | **Register** | **Bits** | **Unknown CMU register** | **Description**
0x467 | 0x14 | 15:0 | UNKNOWN | For CMU reset write 0x143d, 0x3c15, 0x3c17, 0x0000