diff --git a/sources/rtk-gp3000/src/hal/phy/Kconfig b/sources/rtk-gp3000/src/hal/phy/Kconfig
new file mode 100644
index 00000000..2be2ebc8
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/Kconfig
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
+#
+
+config RTK_MSSDK_PHY
+	tristate "Realtek MSSDK PHYs"
+	help
+	  Currently supports the RTL8261N,RTL8264B PHYs.
+
diff --git a/sources/rtk-gp3000/src/hal/phy/Makefile b/sources/rtk-gp3000/src/hal/phy/Makefile
new file mode 100644
index 00000000..ff4c203a
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/Makefile
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
+#
+
+ccflags-y    := -DRTK_PHYDRV_IN_LINUX
+#ccflags-y    += -DDEBUG
+
+obj-$(CONFIG_RTK_MSSDK_PHY)	+= rtk-ms-phy.o
+
+rtk-ms-phy-objs     := rtk_phy.o
+rtk-ms-phy-objs     += rtk_phy_rtl8224.o
+rtk-ms-phy-objs     += rtk_osal.o
+
+# files from SDK
+rtk-ms-phy-objs     += phy_patch.o
+rtk-ms-phy-objs     += phy_rtl826xb_patch.o
+rtk-ms-phy-objs     += phy_rtl8224_patch.o
+
+# rtk phylib
+rtk-ms-phy-objs     += rtk_phylib.o
+rtk-ms-phy-objs     += rtk_phylib_rtl826xb.o
+rtk-ms-phy-objs     += rtk_phylib_rtl8224.o
+
+ifdef CONFIG_MACSEC
+rtk-ms-phy-objs     += rtk_macsec.o
+rtk-ms-phy-objs     += rtk_phylib_macsec.o
+endif
diff --git a/sources/rtk-gp3000/src/hal/phy/README b/sources/rtk-gp3000/src/hal/phy/README
new file mode 100644
index 00000000..1b0d5ec2
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/README
@@ -0,0 +1,25 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
+ */
+
+the driver is based on linux 5.10.146
+
+1. Copy the folder "drivers/net/phy/rtk" to your linux in the same path
+
+2. Modify Kconfig: linux/drivers/net/phy/Kconfig for add menuconfig
+
+    if PHYLIB
+    ......
+    source "drivers/net/phy/rtk/Kconfig"
+    endif # PHYLIB
+
+3. Modify Makefile: linux/drivers/net/phy/Makefile for build code
+
+    obj-$(CONFIG_RTK_MSSDK_PHY)		+= rtk/
+
+4. enable kernel config:
+    CONFIG_RTK_MSSDK_PHY=y
+
+
diff --git a/sources/rtk-gp3000/src/hal/phy/construct/conf_rtl8224.c b/sources/rtk-gp3000/src/hal/phy/construct/conf_rtl8224.c
new file mode 100644
index 00000000..cebfe662
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/construct/conf_rtl8224.c
@@ -0,0 +1,3160 @@
+//Date: Wed Jun 22 11:29:51 2022
+
+#define RTL8224_AB_FW_VER           0x0090
+#define RTL8224_FW_VER              0x0080
+#define RTL8224_MAIN_VER            0xFF
+#define RTL8224_SW_VER              0xFF
+#define RTL8224_TOP_VER             0xFF
+#define RTL8224_AFEFW_VER           0xFF
+#define RTL8224_PATCH_FLOW_VER      "BV0002"
+
+rtk_phy_hwpatch_t rtl8224_patch_fwpr_conf[] = {
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x8023},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1802},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb82e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0001},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb820,  7,  7, 0x0001},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa016},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa012},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa014},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8010},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8023},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8027},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x802b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8042},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8052},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8062},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8070},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x416e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x09cc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0a9b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd501},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa103},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8203},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd500},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0188},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0aa1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd501},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8103},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa203},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd500},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0188},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xac03},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa138},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1ded},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xac03},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa138},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1cb8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd504},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaa18},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd500},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x14e4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd719},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x7fac},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x14e4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd704},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5fbc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd504},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa001},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa1e0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd500},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd031},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd1c5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x14e4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd704},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5fbc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x111f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf80},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd712},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4077},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd71e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4159},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd4c0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd71e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x6099},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x7f04},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1bc0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x9f80},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1e2a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1e2c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf80},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd712},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4077},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd71e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4159},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd4c1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd71e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x6099},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x7f04},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1bc0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x9f80},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1cf6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1cf9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd708},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x3b0f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8067},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x150c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd503},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8970},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0c07},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0901},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa008},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8002},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd500},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1504},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa026},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa024},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1500},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa022},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1cec},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa020},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1e20},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa006},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1111},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa004},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1cb7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa002},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1dec},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x017f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa008},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x7f00},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa012},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0ff8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa014},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xc114},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd04a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd069},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd71f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x40ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa152},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0a20},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa154},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x10f6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa156},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x122c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa158},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x09af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa15a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x09b0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa150},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x001f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa016},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0020},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa012},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa014},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8010},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x801f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8022},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8025},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8030},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8030},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8030},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8030},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa301},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0b55},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd700},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5f9f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd131},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd047},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0b55},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd700},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5edf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd700},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5f74},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x032a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8280},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0504},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x9580},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x074c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0b24},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd14a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd048},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd700},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4014},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd417},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0b24},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0670},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa10e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa10c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa10a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa108},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa106},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x066e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa104},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x074a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa102},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0503},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa100},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0325},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa110},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x000f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa012},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0ff8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa014},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd186},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd04e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa164},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x049d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa166},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x049e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa162},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0003},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb87c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8592},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb87e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf85},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaaaf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x85b3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf85},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xb9af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x85bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf85},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xdeaf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x85de},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf85},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xdeaf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x85de},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0246},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xb802},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x3f92},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf21},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0102},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x85de},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf20},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd202},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8945},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf21},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x25f8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfbef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x79fb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe080},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x12ad},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x2504},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee83},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8c00},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd100},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf62},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xda02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5feb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x97ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfcaf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4fe8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf8e0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0502},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8602},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xae16},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa001},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0502},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x869d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xae0e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa002},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0502},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8789},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xae06},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa003},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0302},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8832},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfc04},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf8f9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfafb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef79},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfbbf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x628f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe08f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd248},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x031a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x9002},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x600a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1f55},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe38f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd91c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x450d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x46e3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fd8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1a43},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe48f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd6e5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fd7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef64},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1f44},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1f55},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe38f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xdbe1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fd9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1c45},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0d46},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1b64},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe38f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd8ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x75e3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fda},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1a75},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0288},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xb7ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x47e4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fdd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe58f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xde1f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x661f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x55e0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fd6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe18f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd7e3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fdc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1a63},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe38f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd91c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x650d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x661a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x64bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x65ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe08f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd248},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x031a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x9002},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x600a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xac2a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x05d7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x017f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xae03},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd700},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xff02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x88c7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef47},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe48f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xdfe5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fe0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xff01},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xae03},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0222},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x14ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef97},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfffe},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfdfc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x04f8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf9fa},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfbef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x79fb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0287},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1abf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x628f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe08f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd248},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x031a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x9002},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x600a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1f55},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe38f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd51b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x45ab},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x24e0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe18f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfee2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fd3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe38f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd41b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x45ab},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x14bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1f44},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1f55},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe18f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd8e3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fda},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1a45},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xdc19},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xddae},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x2ebf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fe5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe38f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd24b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x021a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x93e8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x19e8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe18f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe2e2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe38f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfc1a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x54e0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fdf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe18f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe01b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x45aa},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x06ee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x02ae},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0302},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8927},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x97ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfefd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfc04},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf8f9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef59},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf9fa},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfb02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x6767},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfb00},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfc00},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfd00},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfe00},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe08f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xdfe1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fe0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe28f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xdde3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fde},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef74},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef65},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0d55},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0288},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfde7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fd1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef46},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1b47},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x9e29},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef46},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0288},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd4ad},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x2704},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x7cff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xff14},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe28f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfde3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffe},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1b54},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x9e02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xab0e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe48f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfde5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffe},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef46},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe48f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfbe5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x16ae},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd1bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x63e2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0266},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd4ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfefd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef95},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfdfc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x04f8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf9fa},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfbef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x79fb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0267},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x67e2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe38f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfce0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fe2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1a50},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe68f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf9e7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffa},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0d55},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0288},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfde7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fd1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe08f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf9e1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffa},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0288},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd4ad},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x2704},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x7cff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xff14},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1f55},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe38f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe11c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x540d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x54e0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe18f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfe1b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x54ab},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0fe0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ff9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe18f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfa14},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe48f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf9e5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffa},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xae22},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xede3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fd2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4b02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1a93},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe88f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf919},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe88f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfae0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ff9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe18f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfae3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fe2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1a43},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe48f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf9e5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffa},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef64},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe08f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xdfe1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fe0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1b46},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaba0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xede3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fd2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4b02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1a93},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd819},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd9a4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0302},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8927},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf63},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe202},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x66d4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xff03},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x97ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfefd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfc04},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf8f9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfafb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef79},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfbbf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fed},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe38f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd24b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x021a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x93d8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x19d9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe38f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd81b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x43ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x740c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x761f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x44e1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fd9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef64},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd300},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0266},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe6ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x47bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ff5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe38f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd21a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x93dd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xede3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fd2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4b02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1a93},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd819},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd9e3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fd8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1b43},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe38f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xda1b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x439f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1bbf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x628f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe08f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd248},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x031a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x9002},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x600a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf5e2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fd2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1a92},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xdb1b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x31aa},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x01dd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xff00},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe08f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd210},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe48f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd2a0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0407},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd200},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0222},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x14ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef97},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfffe},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfdfc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x04f8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfaac},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4f08},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef46},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1b67},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaa02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef74},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfefc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x04f8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfaef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x461b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x67ab},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x02ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x74fe},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfc04},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf9ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x95f9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef54},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0d55},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe28f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd11b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x239e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0602},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x88fd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe78f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd15c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x001f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf64},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xb402},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5feb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf64},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xc002},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x600a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfdef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x95fd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x04f8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf9fb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef79},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfbe2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fd2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xac3b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0a5b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x070c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x321a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x322b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x40ae},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0a5b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x030c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x330c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x211a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x322b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x6002},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4756},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x97ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfdfc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x04f8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef49},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf8bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fed},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe08f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd248},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x021a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x90e8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x19e8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xff03},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfcef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x94fc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x04ee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fed},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00ee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00ee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00ee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ff0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00ee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ff1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00ee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ff2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00ee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ff3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00ee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ff4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00ee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ff9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00ee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffa},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00ee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00ee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00ee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00ee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffe},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00ee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fd2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00ee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00ee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fd1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0004},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb85e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x20fe},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb860},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x20cf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb862},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x2122},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb864},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4fdc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb886},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb888},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb88a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb88c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb838},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x000f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb820,  7,  7, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x847d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf84},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x95af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x849a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf84},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa0af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x84ae},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf84},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xdbaf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x84fa},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf84},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfaaf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x84fa},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x2901},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf16},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5802},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x84fa},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf16},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x2fee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffe},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffbf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x161c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf16},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00e2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8700},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xad30},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x21e2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8701},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe387},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x021b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x549f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x17ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x54e1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8018},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0d14},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf85},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8402},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x55a4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0d11},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf85},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8702},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x55a4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef45},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe281},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xc2af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4056},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe187},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00ad},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x2813},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe180},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x180d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x16bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8584},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0255},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa40d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x11bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8587},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0255},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa402},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x3b96},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf3a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfc02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8501},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0285},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5904},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf8f9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfafb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef79},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfbd7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd500},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00a2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0005},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf57},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x61ae},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x13a2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0105},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf57},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x64ae},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0ba2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0205},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf57},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x67ae},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x03bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x576a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0255},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xc3ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x6402},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5b12},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x13e1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1b13},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x9fd5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe083},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x7380},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1b02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x9f0a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef47},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe48f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfce5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xae06},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x2a01},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd300},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaebd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x97ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfefd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfc04},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf8f9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfafb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe28f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfce3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef65},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe08f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfee1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef74},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x025a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf7ad},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x500c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe68f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfee7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe283},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4ee6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x834f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfffe},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfdfc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x04cc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xc010},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00c0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x2000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb818},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x164d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb81a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x162c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb81c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x15fd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb81e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4053},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb850},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x3af9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb852},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb878},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb884},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb832},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x001f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb896,  0,  0, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb892, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc206},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  8, 0x00b1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb896,  0,  0, 0x0001},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb82e,  0,  0, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x8023},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0000},
+};
+
+rtk_phy_hwpatch_t rtl8224_patch_fwlm_conf[] = {
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81a3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0032},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81a4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00c0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81a5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0032},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81a8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x001d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0025},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81b2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0009},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81b6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x003f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81b7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0048},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81b8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x000c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81b9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0004},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81ba},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81bb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0020},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81bc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0004},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81bd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0020},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81be},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x001a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00e0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81c0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0001},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81c1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x003a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81c2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x001c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81c3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0060},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81c4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81c5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0011},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81c6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81c7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00cf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81c8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81c9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00b0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81ca},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81cb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x000f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81cc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0011},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81cd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00c0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81ce},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81cf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x000e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81d0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81d1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00be},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81d2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81d3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0018},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81d4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0008},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81d5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0070},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81d6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81d7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0037},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81d8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81d9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0048},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81da},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81db},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00f4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81dc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00eb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81dd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00a0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81de},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81df},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x002b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81e0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81e1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x009c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81e2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81e3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00b2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81e4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00eb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81e5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81e6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0002},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81e7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0092},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81e8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00fe},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81e9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00e4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81ea},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81eb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x003c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81ec},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0006},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81ed},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00f2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81ee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x003a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81f0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81f1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x008a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81f2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81f3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00d0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81f4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x000a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81f5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0009},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81f6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81f7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00dc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81f8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81f9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0030},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81fa},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x8700},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0001},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x8701},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0004},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x8018},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0070},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81a6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00c0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81a9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81b0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0005},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81b3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x001d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81fb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x006c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x8702},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0050},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x8ffb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0001},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80dc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x000a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x8378},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0022},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa47e,  7,  6, 0x0001},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8217},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x001e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8384},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0004},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8fd6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8fd7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8fd8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x000c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8fd9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0080},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8fda},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x000a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8fdb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0019},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8fdc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0019},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8fdd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8fde},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8fdf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8fe0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8fe1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0020},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8fe2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x000c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8fd3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8fd4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0015},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8fd5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0015},
+};
+
+rtk_phy_hwpatch_t rtl8224_patch_afe_conf[] = {
+    {RTK_HWPATCH_OP_PHY, 0x02 ,0x00, 0xbf84,  2,  0, 0x0004},
+    {RTK_HWPATCH_OP_PHY, 0x02 ,0x00, 0xbf8c, 10,  6, 0x0000},
+};
+
+rtk_phy_hwpatch_t rtl8224_patch_sds_conf[] = {
+    {RTK_HWPATCH_OP_MMD, 0x01 ,0x1e, 0x7b20,  4,  0, 0x001f},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x06, 0x0012, 15,  0, 0x00a4},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x07, 0x0010,  7,  0, 0x0003},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x06, 0x0003, 15, 15, 0x0001},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x06, 0x001d,  9,  9, 0x0001},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x06, 0x001f, 13, 13, 0x0001},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x21, 0x0010, 15,  0, 0x4480},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x21, 0x0013, 15,  0, 0x0400},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x21, 0x0018, 15,  0, 0x6d02},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x21, 0x001b, 15,  0, 0x424e},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x21, 0x001d, 15,  0, 0x0002},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x36, 0x001c, 15,  0, 0x1390},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x2e, 0x0004, 15,  0, 0x0080},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x2e, 0x0006, 15,  0, 0x0408},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x2e, 0x0007, 15,  0, 0x020d},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x2e, 0x0009, 15,  0, 0x0601},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x2e, 0x000b, 15,  0, 0x222c},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x2e, 0x000c, 15,  0, 0xa217},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x2e, 0x000d, 15,  0, 0xfe40},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x2e, 0x0015, 15,  0, 0xf5f1},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x2e, 0x0016, 15,  0, 0x0443},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x2e, 0x001d, 15,  0, 0xabb0},
+    {RTK_HWPATCH_OP_MMD, 0x01 ,0x1e, 0x7b20, 14, 10, 0x0002},
+    {RTK_HWPATCH_OP_MMD, 0x01 ,0x1e, 0x7b20,  4,  0, 0x000d},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x20, 0x0000,  5,  4, 0x0003},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x20, 0x0000,  5,  4, 0x0001},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x20, 0x0000,  5,  4, 0x0003},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x20, 0x0000,  5,  4, 0x0000},
+};
+
+rtk_phy_hwpatch_t rtl8224_patch_top_conf[] = {
+    {RTK_HWPATCH_OP_MMD, 0x01 ,0x1e, 0x044c, 15,  0, 0x8224},
+};
+
+
+rtk_phy_hwpatch_t rtl8224_b_patch_fwpr_conf[] = {
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x8023},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1801},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb82e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0001},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb820,  7,  7, 0x0001},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa016},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa012},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa014},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8010},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8016},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8029},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x802d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8031},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8048},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8058},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8068},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8808},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd711},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x404f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa808},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1dff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x416e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x09cc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0a9b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd501},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa103},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8203},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd500},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0188},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0aa1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd501},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8103},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa203},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd500},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0188},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xac03},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa138},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1ded},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xac03},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa138},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1cb8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd504},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaa18},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd500},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x14e4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd719},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x7fac},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x14e4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd704},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5fbc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd504},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa001},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa1e0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd500},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd031},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd1c5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x14e4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd704},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5fbc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x111f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf80},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd712},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4077},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd71e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4159},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd4c0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd71e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x6099},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x7f04},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1bc0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x9f80},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1e27},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1e29},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf80},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd712},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4077},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd71e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4159},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd4c1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd71e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x6099},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x7f04},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1bc0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x9f80},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1cf6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1cf9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd708},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x3b0f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x806d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x150c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd503},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8970},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0c07},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0901},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa008},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8002},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd500},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1504},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa026},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1500},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa024},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1cec},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa022},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1e1d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa020},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1111},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa006},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1cb7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa004},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1dec},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa002},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x017f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1dfe},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa008},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xff00},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa012},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0ff8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa014},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xc114},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd04a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd069},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd71f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x40ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa152},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0a20},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa154},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x10f6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa156},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x122c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa158},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x09af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa15a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x09b0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa150},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x001f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa016},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0020},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa012},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa014},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8010},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8027},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8036},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8039},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8044},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8044},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8044},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8044},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa710},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa00a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8190},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8204},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8280},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa404},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd130},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd047},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0b46},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd700},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5fb4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa110},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa204},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa280},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd130},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd047},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0b46},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd700},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5fb4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0505},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa301},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0b46},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd700},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5f9f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd131},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd047},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0b46},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd700},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5edf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd700},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5f74},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x032a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x9580},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x073d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0b15},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd14a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd048},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd700},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4014},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd417},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0b15},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0661},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa10e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa10c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa10a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa108},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa106},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x065f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa104},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x073b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa102},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0325},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa100},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x04ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xa110},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x000f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb87c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x858b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb87e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf85},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa3af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x85b8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf85},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xc3af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x865b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf86},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x64af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x866d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf86},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x73af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8692},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa001},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0602},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8692},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf4f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x68a0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0206},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0287},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x55af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4f68},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf4f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x45ee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x01ee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x838c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x01af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5299},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfe00},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1b03},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd100},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1b10},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xac2d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0fa2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0006},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd700},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0eaf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x860c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd700},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x11af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x860c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa001},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0fa2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0106},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd700},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x12af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x860c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd700},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x15af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x860c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa002},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0fa2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0206},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd700},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x17af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x860c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd700},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1baf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x860c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfe01},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf44},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5102},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x87b0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe080},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x28ac},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x2009},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf62},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5902},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5f29},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xac28},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1fbf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x61e7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x025f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x29ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x21bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x61ea},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x025f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x29ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x31ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x021b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x03a0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xff13},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa200},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0bd1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x70af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x444e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0288},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5faf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x444e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd15f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf44},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4ea0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfe0d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa200},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x05d1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x59af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x444e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd14c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf44},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4eaf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4451},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0245},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfc02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x3f89},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf20},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf802},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8930},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0222},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0baf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x20cc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x028c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x41af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x211c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf8fb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef79},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfbe0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8012},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xad25},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x04ee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x838c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00d1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x61f9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x025f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0aff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef97},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfffc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf4f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x28f8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf9ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x59e1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x3901},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x9e64},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe083},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x97e1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8200},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1b01},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x9f07},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee83},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8c05},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf87},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x50d1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0fbf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x620e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x025f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0abf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x61f9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x025f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x29e5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x838f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf62},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0b02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x65f9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf62},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1102},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x65f9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf62},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1402},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x65f0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd103},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf61},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf902},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5f0a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe182},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x01bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x6217},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x025f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0abf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x621a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0265},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf9bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x621a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0265},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf0bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x621d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0265},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf9bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x621d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0265},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf0ee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x838c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x02af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8750},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd10f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf62},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0e02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5f0a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf61},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf902},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5f29},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe583},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fbf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x620b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0265},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf9bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x6211},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0265},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf9bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x6214},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0265},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf0d1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x03bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x61f9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x025f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0ad1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x40bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x6217},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x025f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0abf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x621a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0265},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf9bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x621a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0265},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf0bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x621d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0265},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf9bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x621d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0265},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf0ee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x838c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x02ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x95fd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfc04},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf8f9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef59},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf62},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x2002},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5f29},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa100},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x49bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x620b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0265},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf0e1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x838f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf61},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf902},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5f0a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf62},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0e02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x65f0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf62},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1102},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x65f0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf62},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1402},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x65f0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf62},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1702},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x65f0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe18f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffa1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x010b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee83},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8c07},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xff00},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf87},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xabe1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8394},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa101},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x07ee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x838c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x05af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x87ab},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee83},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8c03},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef95},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfdfc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x04f8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfaef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x69fb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf61},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfc02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5f29},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0d45},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5c07},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xff1c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x47ac},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x2704},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0c41},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xae03},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd4ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffbf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x615a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x025f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0abf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x614e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0265},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf9bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x614e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0265},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf0bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x61ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x025f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x290d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x455c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x07ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1c47},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xac27},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x040c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x41ae},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x03d4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf61},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5a02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5f0a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf61},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5102},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x65f9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf61},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5102},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x65f0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf62},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0202},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5f29},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0d45},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5c07},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xff1c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x47ac},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x2704},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0c41},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xae03},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd4ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffbf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x615a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x025f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0abf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x6154},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0265},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf9bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x6154},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0265},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf0bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x6205},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x025f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x290d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x455c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x07ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1c47},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xac27},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x040c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x41ae},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x03d4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf61},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5a02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5f0a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf61},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5702},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x65f9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf61},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5702},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x65f0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x96fe},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfc04},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf9fa},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfba3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0008},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd646},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x9ed2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x889e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa301},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x13a2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0008},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd638},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x19d2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x889e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd63b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe6d2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x01af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x889e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa302},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x13a2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0008},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd62c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fd2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x889e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd62f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x94d2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x01af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x889e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd625},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xcbd2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0102},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x88b4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0266},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfa0d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x75ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x47a0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0002},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xae03},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd400},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfefd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x04f8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf9fa},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef69},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xface},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfa1f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x33be},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xac30},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x06bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x83c0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf88},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xcdbf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x83c2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef13},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0c16},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1f00},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1a94},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd819},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd9ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x74bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x83e2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef13},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0c16},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1f00},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1a94},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd819},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd9ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x64ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x03d3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0c02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x6602},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0c74},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef30},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xac30},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x06d6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x91b1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf89},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x01d6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x886f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0266},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfa0d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x725f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x3fff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x2713},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf60},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5f29},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xad28},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x07a3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x02aa},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0c81},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xae03},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa304},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa3cf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef47},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe482},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xc8e5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x82c9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfec6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfeef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x96fe},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfdfc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x04f8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf9ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x59f9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfafb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd200},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef32},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0c34},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe78f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfdbf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x61ae},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4803},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1a90},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x025f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x29ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x64e3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fd7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x028c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x89ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x460d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x46e3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fd6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1a43},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe48f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd4e5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fd5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1f66},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1f77},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe38f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd91a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x63e3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fd7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x028c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x890d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x661b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x46ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x64e3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fd6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1a73},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe38f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd81a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x7302},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8b30},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef47},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe48f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xdbe5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fdc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd301},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x028c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x7a1f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x66e0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fd4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe18f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd5e3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fda},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1a63},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe38f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd702},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8c89},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0d66},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1a64},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf65},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0eef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0248},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x031a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x9002},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5f29},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xac2a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x05d7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x017f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xae03},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd700},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xff02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8b40},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef47},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe48f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xdde5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fde},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd302},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x028c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x7a02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8b4d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd303},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x028c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x7ae0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fdb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe18f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xdcef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x64e0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fdd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe18f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xdeef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x7402},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8bd2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd304},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x028c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x7abf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fe3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef32},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4b02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1a93},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe88f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf919},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe88f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfad0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00e1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fe0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1a64},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe08f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xdde1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fde},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1b46},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaa18},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe08f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf9e1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffa},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe38f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe01a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x43e4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ff3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe58f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf4d3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0502},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8c7a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xae03},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf8a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa3e0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ff3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe18f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf40c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x41bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8cd4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1a94},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd819},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd9ad},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x2704},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x7cff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xff14},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe38f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xdfef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x6402},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8c89},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0d64},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe08f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfbe1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1b64},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xab0f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe08f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf3e1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ff4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x14e4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ff3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe58f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf4ae},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x21bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8feb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef32},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4b02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1a93},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe88f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf319},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe88f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf4e0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ff3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe18f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf4e3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fe0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1a43},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe48f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf3e5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ff4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef64},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe08f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xdde1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fde},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1b46},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xab99},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xebef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x324b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x021a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x93d8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x19d9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa400},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0015},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd306},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x028c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x7abf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8feb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef32},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4b02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1a93},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe88f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf919},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe88f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfad3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0702},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8c7a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xebef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x324b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x021a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x93d8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x19d9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe38f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd61b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x43ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x740c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x761f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x44e1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fd7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef64},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd300},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0266},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x02ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x47bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ff5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1a92},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xddd3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0802},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8c7a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xebef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x324b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x021a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x93d8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x19d9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe38f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd61b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x43e3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fd8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1b43},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x9f1c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd309},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x028c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x7abf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x61ae},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4803},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1a90},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x025f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x29bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ff5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1a92},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xdb1b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x31aa},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x01dd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x12a2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0402},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xae03},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf89},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x39ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfefd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef95},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfdfc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x04f8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfaef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x46ac},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4f06},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1b67},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaa02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef74},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfefc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x04f8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfaef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x461b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x67ab},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x02ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x74fe},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfc04},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf8f9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfafb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef79},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfb02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x6683},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd340},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf8c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd4a3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x6002},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xae0e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1a32},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0246},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x9a02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8bab},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1b32},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x2b04},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaeed},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef32},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef69},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf65},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0eef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0248},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x031a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x9002},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5f29},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xac2a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1bef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x96ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x234a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x02d3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x60a3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8002},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xae0e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1a32},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0246},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x9a02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8bab},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1b32},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x2b08},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaeed},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf63},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0102},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x65f0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x97ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfefd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfc04},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf8f9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfad2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x691f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x44d0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x12bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x63d3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x025f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0a12},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf63},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xdf02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5f29},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef96},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xdc19},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xdd19},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa220},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe2fe},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfdfc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x04f8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf9ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x59f9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf8c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd4ee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ff9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00ee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffa},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00ee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00ee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x004e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0002},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1a96},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x174f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0002},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x2f8c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd4ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x691b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x679e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x2fe0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe18f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfcda},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x19db},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x19ad},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x3704},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x7dff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xff15},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1b45},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x9e02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xabe3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe68f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfbe7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef59},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x3d8c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd43d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0002},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0d51},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe68f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf9e7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffa},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaecb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe28f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf9e3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffa},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef65},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe28f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfbe3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef75},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfdef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x95fd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfc04},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xeb00},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xec00},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xed00},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee00},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef00},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf100},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf200},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf300},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf400},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf900},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfa00},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfb00},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xee8f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfc00},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x04f9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe28f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfd5a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf05b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0f1e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x23e6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfd04},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf81f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x44ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x131c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x64fc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0400},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb85e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4f35},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb860},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5295},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb862},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4404},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb864},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x20f5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb886},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x20c9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb888},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x2119},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb88a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4f1c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb88c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb838},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x007f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb820,  7,  7, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x847d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf84},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x95af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x849a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf84},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xa0af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x84ae},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf84},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xdbaf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x84fa},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf84},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfaaf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x84fa},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x2901},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf16},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5802},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x84fa},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf16},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x2fee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffe},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffbf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x161c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf16},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00e2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8700},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xad30},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x21e2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8701},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe387},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x021b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x549f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x17ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x54e1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8018},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0d14},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf85},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8402},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5598},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0d11},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf85},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8702},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5598},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef45},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe281},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xc2af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4056},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe187},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00ad},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x2813},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe180},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x180d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x16bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8584},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0255},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x980d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x11bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8587},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0255},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x9802},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x3b96},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaf3a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfc02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8501},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0285},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5904},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf8f9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfafb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef79},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfbd7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd500},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00a2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0005},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf57},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x55ae},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x13a2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0105},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf57},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x58ae},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0ba2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0205},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbf57},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5bae},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x03bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x575e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0255},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xb7ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x6402},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x5b00},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x13e1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1b13},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x9fd5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe083},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x7380},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1b02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x9f0a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef47},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe48f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfce5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xae06},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x2a01},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd300},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xaebd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xffef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x97ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfefd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfc04},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf8f9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfafb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe28f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfce3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8ffd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef65},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe08f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfee1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xef74},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x025a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe5ad},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x500c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe68f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfee7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x8fff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xe283},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4ee6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x834f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfffe},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfdfc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x04cc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xc010},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x00c0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x2000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb818},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x164d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb81a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x162c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb81c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x15fd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb81e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x4053},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb850},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x3af9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb852},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb878},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb884},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb832},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x001f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb896,  0,  0, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb892, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc202},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0xfa02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc204},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x4d02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc206},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0xb103},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc208},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x3003},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc20a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0xb504},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc20c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x3a04},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc20e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0xe705},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc210},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0xac06},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc212},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x9407},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc214},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x9808},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc216},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0xd70a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc218},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x5c0c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc21a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x5e0e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc21c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x0110},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc21e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x5ef6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc220},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0xf6f5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc222},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0xf3f3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc224},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0xefeb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc226},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0xe7e4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc228},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0xe2df},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc22a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0xdddb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc22c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0xdad9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc270},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x1819},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc272},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x1c1e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc274},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x2021},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc276},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x2223},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc278},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x2324},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc27a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x2525},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc27c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x2626},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc27e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x264a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc280},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x4a4a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc282},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x4d4d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc284},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x5055},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc286},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x5252},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc288},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x5252},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc28a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x5251},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc28c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x5252},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc201},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890,  7,  0, 0x0001},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc22e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  8, 0x00d7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc26f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890,  7,  0, 0x0018},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc28e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  8, 0x0052},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb896,  0,  0, 0x0001},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8217},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x001e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb82e,  0,  0, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x8023},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0000},
+};
+
+rtk_phy_hwpatch_t rtl8224_b_patch_fwlm_conf[] = {
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x8017},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0007},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8066},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0010},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8067},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0040},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8068},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x000a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8069},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0040},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x806e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0002},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x806f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x00a0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8084},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0010},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8085},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0040},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8086},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x000a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8087},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0040},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x808c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0002},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x808d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x00a0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8029},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x000e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80b5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0095},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80b6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00cb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80b7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00f6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80b8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0004},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80b9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00d2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80ba},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0006},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80bb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00f7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80bc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00bc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80bd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x004b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80be},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0019},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x002f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80c9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00a0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80ca},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00cb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80cb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00f6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80cc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0004},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80cd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x009e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80ce},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0006},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80cf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00f5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80d0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00c4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80d1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x004c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80d2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0019},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80d3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x002f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80c0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x000c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80d4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x000c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa87e, 12,  8, 0x0006},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80a1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0048},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80a2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x009c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80a3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00b6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80a4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0003},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80a5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00da},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80a6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x000a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80a7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00ea},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80a8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00a6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80a9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00e3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80aa},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x001f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80ab},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x003b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80ac},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x001e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81a3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0032},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81a4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00c0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81a5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0032},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81a8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x001d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x002d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81b2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0009},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81b6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0048},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81b7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0048},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81b8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0008},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81b9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0004},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81ba},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81bb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0020},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81bc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0004},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81bd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0020},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81be},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x001a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00e0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81c0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0001},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81c1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x003a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81c2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x001c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81c3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0060},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81c4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81c5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0011},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81c6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81c7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00cf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81c8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81c9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00b0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81ca},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81cb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x000f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81cc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x000d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81cd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00ad},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81ce},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81cf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x000e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81d0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81d1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00be},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81d2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81d3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0018},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81d4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0008},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81d5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0070},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81d6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81d7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0037},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81d8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81d9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0048},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81da},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81db},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00f4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81dc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00eb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81dd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00a0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81de},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81df},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x002b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81e0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81e1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x009c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81e2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81e3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00b2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81e4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00eb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81e5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00af},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81e6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0002},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81e7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0092},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81e8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00fe},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81e9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00e4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81ea},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81eb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x003c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81ec},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0006},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81ed},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00f2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81ee},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81ef},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x003a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81f0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81f1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x008a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81f2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81f3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00d0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81f4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x000a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81f5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0009},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81f6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81f7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00dc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81f8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00ff},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81f9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0030},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81fa},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x8700},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0001},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x8701},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0004},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x8018},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0070},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81a6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x00c0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81a9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81b0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0005},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81b3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x001c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x81fb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x006c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x8702},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0050},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa86a,  0,  0, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x8ffb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0001},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80dc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x000a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x8378},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  8, 0x0022},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8384},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0004},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8fd4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8fd5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8fd6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x000c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8fd7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0080},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8fd8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x000a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8fd9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0019},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8fda},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0019},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8fdb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8fdc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8fdd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8fde},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8fdf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x0020},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8fe0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  8, 0x000c},
+};
+
+
+rtk_phy_hwpatch_t rtl8224_b_patch_afe_conf[] = {
+    {RTK_HWPATCH_OP_PHY, 0x02 ,0x00, 0xbf84,  2,  0, 0x0004},
+    {RTK_HWPATCH_OP_PHY, 0x02 ,0x00, 0xbf8c, 10,  6, 0x0000},
+};
+
+rtk_phy_hwpatch_t rtl8224_b_patch_sds_conf[] = {
+    {RTK_HWPATCH_OP_MMD, 0x01 ,0x1e, 0x7b20,  4,  0, 0x001f},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x06, 0x0012, 15,  0, 0x00a4},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x07, 0x0010,  7,  0, 0x0003},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x06, 0x0003, 15, 15, 0x0001},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x06, 0x001d,  9,  9, 0x0001},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x06, 0x001f, 13, 13, 0x0001},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x21, 0x0010, 15,  0, 0x4480},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x21, 0x0013, 15,  0, 0x0400},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x21, 0x0018, 15,  0, 0x6d02},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x21, 0x001b, 15,  0, 0x424e},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x21, 0x001d, 15,  0, 0x0002},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x36, 0x001c, 15,  0, 0x1390},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x2e, 0x0004, 15,  0, 0x0080},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x2e, 0x0006, 15,  0, 0x0408},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x2e, 0x0007, 15,  0, 0x020d},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x2e, 0x0009, 15,  0, 0x0601},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x2e, 0x000b, 15,  0, 0x222c},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x2e, 0x000c, 15,  0, 0xa217},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x2e, 0x000d, 15,  0, 0xfe40},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x2e, 0x0015, 15,  0, 0xf5f1},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x2e, 0x0016, 15,  0, 0x0443},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x2e, 0x001d, 15,  0, 0xabb0},
+    {RTK_HWPATCH_OP_MMD, 0x01 ,0x1e, 0x7b20, 14, 10, 0x0002},
+    {RTK_HWPATCH_OP_MMD, 0x01 ,0x1e, 0x7b20,  4,  0, 0x000d},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x20, 0x0000,  5,  4, 0x0003},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x20, 0x0000,  5,  4, 0x0001},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x20, 0x0000,  5,  4, 0x0003},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x20, 0x0000,  5,  4, 0x0000},
+};
+
+rtk_phy_hwpatch_t rtl8224_b_patch_top_conf[] = {
+    {RTK_HWPATCH_OP_MMD, 0x01 ,0x1e, 0x044c, 15,  0, 0x8224},
+};
+
+
+rtk_phy_hwpatch_t rtl8224_a_patch_fwpr_conf[] = {
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x8023},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x1800},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0xb82e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0001},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb820, 15,  0, 0x0090},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb820, 15,  0, 0x0010},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb896, 15,  0, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb892, 15,  0, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc202},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0xc101},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc204},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0xff02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc206},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x6a02},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc208},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0xd903},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc20a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x5c03},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc20c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0xf604},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc20e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x8805},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc210},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x4006},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc212},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x3d07},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc214},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x2408},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc216},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x2b09},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc218},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x840b},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc21a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x410c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc21c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x440e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc21e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x00f6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc220},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0xf6f5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc222},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0xf3f3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc224},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0xefeb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc226},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0xe7e4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc228},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0xe2df},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc22a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0xdddb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc22c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0xdad9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc270},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x1819},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc272},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x1c1e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc274},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x2021},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc276},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x2223},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc278},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x2324},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc27a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x2525},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc27c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x2626},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc27e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x264a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc280},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x4a4a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc282},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x4d4d},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc284},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x5055},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc286},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x5252},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc288},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x5252},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc28a},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x5251},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc28c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  0, 0x5252},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc201},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890,  7,  0, 0x0001},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc22e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  8, 0x00d7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc26f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890,  7,  0, 0x0018},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb88e, 15,  0, 0xc28e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb890, 15,  8, 0x0052},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb896, 15,  0, 0x0001},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb82e, 15,  0, 0x0000},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x8023},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0000},
+};
+
+rtk_phy_hwpatch_t rtl8224_a_patch_fwlm_conf[] = {
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80b5},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x98c3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80b6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xc3f6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80b7},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf604},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80b8},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x04d2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80b9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xd206},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80ba},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x06fa},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80bb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfabc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80bc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbc66},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80bd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x6619},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80be},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x192f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80bf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x2f0c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80c0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0c23},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80c9},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xc0bb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80ca},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xbbf6},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80cb},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xf604},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80cc},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x049e},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80cd},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x9e06},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80ce},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x06fa},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80cf},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xfac4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80d0},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0xc463},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80d1},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x6319},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80d2},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x192f},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80d3},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x2f0c},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa436, 15,  0, 0x80d4},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xa438, 15,  0, 0x0c23},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87c, 15,  0, 0x8012},
+    {RTK_HWPATCH_OP_PHY, 0xff ,0x00, 0xb87e, 15,  0, 0xee47},
+};
+
+rtk_phy_hwpatch_t rtl8224_a_patch_afe_conf[] = {
+    {RTK_HWPATCH_OP_PHY, 0x02 ,0x00, 0xbf84,  2,  0, 0x0007},
+    {RTK_HWPATCH_OP_PHY, 0x02 ,0x00, 0xbf8c, 10,  6, 0x0000},
+};
+
+rtk_phy_hwpatch_t rtl8224_a_patch_sds_conf[] = {
+    {RTK_HWPATCH_OP_MMD, 0x01 ,0x1e, 0x7b20,  4,  0, 0x001f},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x06, 0x0012, 15,  0, 0x5078},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x2e, 0x0004, 15,  0, 0x0080},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x2e, 0x0016, 15,  0, 0x4743},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x36, 0x001c, 15,  0, 0x1390},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x2e, 0x000b, 15,  0, 0x232c},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x21, 0x0018, 15,  0, 0x6c02},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x21, 0x0018, 15,  0, 0x6d02},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x2e, 0x001d, 15,  0, 0xabb0},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x2e, 0x0009, 10, 10, 0x0001},
+    {RTK_HWPATCH_OP_MMD, 0x01 ,0x1e, 0x7b20, 14, 10, 0x0002},
+    {RTK_HWPATCH_OP_MMD, 0x01 ,0x1e, 0x7b20,  4,  0, 0x000d},
+    {RTK_HWPATCH_OP_MMD, 0x01 ,0x1e, 0x0ac8,  9,  9, 0x0001},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x20, 0x0000,  5,  4, 0x0003},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x20, 0x0000,  5,  4, 0x0001},
+    {RTK_HWPATCH_OP_SDS, 0x01 ,0x20, 0x0000,  5,  4, 0x0003},
+};
+
+rtk_phy_hwpatch_t rtl8224_a_patch_top_conf[] = {
+};
+
diff --git a/sources/rtk-gp3000/src/hal/phy/construct/conf_rtl8261n_c.c b/sources/rtk-gp3000/src/hal/phy/construct/conf_rtl8261n_c.c
new file mode 100644
index 00000000..4ac0b260
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/construct/conf_rtl8261n_c.c
@@ -0,0 +1,2803 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (c) 2024 Realtek Semiconductor Corp. All rights reserved.
+ */
+//Date: Mon Jul 29 17:30:38 2024
+
+rtk_hwpatch_t rtl8261n_c_top_conf[17] = {
+    {RTK_PATCH_OP_TOP     , 0xf  , 2     , 20    , 15, 0 , 0x5   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 2     , 21    , 15, 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 2     , 22    , 15, 0 , 0x280 , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 2     , 23    , 15, 0 , 0x0014, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 3     , 16    , 15, 0 , 0x0300, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 3     , 17    , 15, 0 , 0x01ff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 3     , 18    , 15, 0 , 0x000c, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 3     , 19    , 15, 0 , 0x01ff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 3     , 20    , 15, 0 , 0x0200, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 3     , 21    , 15, 0 , 0x0015, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 3     , 22    , 15, 0 , 0x0200, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 3     , 23    , 15, 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 4     , 16    , 15, 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 13    , 23    , 8 , 5 , 0x6   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 90    , 18    , 15, 0 , 0x15a , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 90    , 19    , 15, 0 , 0x15a , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 90    , 20    , 15, 8 , 0x01  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8261n_c_sds_conf[103] = {
+    {RTK_PATCH_OP_TOP     , 0xf  , 24    , 18    , 15, 0 , 0x881F, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 24    , 19    , 15, 0 , 0x003F, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 24    , 20    , 15, 0 , 0x003F, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 24    , 21    , 15, 0 , 0x003F, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 24    , 22    , 15, 0 , 0x001F, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x06  , 0x0D  , 15, 0 , 0x0F00, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x06  , 0x0E  , 15, 0 , 0x3F5A, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x07  , 0x10  , 15, 12, 0x8   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x07  , 0x10  , 7 , 0 , 0x3   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x06  , 0x1D  , 15, 0 , 0x0600, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x21  , 0x00  , 15, 0 , 0x4902, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x21  , 0x08  , 15, 0 , 0x0FC0, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x21  , 0x09  , 15, 0 , 0x33F0, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x21  , 0x0C  , 15, 0 , 0x08BF, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x21  , 0x12  , 15, 0 , 0x8000, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x36  , 0x07  , 15, 0 , 0x04C0, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x36  , 0x08  , 15, 0 , 0x2000, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2E  , 0x0B  , 15, 0 , 0x2390, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2E  , 0x0C  , 15, 0 , 0xAA17, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2E  , 0x0D  , 15, 0 , 0xFE40, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2E  , 0x0E  , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2E  , 0x11  , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2E  , 0x15  , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2E  , 0x16  , 15, 0 , 0x0041, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2F  , 0x00  , 15, 0 , 0x1F00, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2F  , 0x01  , 15, 0 , 0x2800, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2F  , 0x02  , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2F  , 0x11  , 15, 0 , 0x3000, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2F  , 0x13  , 15, 0 , 0xF400, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2F  , 0x1E  , 15, 0 , 0x0500, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x34  , 0x0B  , 15, 0 , 0x2390, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x34  , 0x0C  , 15, 0 , 0xA517, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x34  , 0x0D  , 15, 0 , 0xFE41, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x34  , 0x0E  , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x34  , 0x11  , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x34  , 0x15  , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x34  , 0x16  , 15, 0 , 0x0041, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x35  , 0x00  , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x35  , 0x01  , 15, 0 , 0x0800, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x35  , 0x02  , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x35  , 0x11  , 15, 0 , 0x3001, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x35  , 0x13  , 15, 0 , 0xF400, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x35  , 0x1E  , 15, 0 , 0x0100, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2C  , 0x0B  , 15, 0 , 0x2390, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2C  , 0x0C  , 15, 0 , 0xA517, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2C  , 0x0D  , 15, 0 , 0xFE41, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2C  , 0x0E  , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2C  , 0x11  , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2C  , 0x15  , 15, 0 , 0x7A61, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2C  , 0x16  , 15, 0 , 0x0041, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2D  , 0x00  , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2D  , 0x01  , 15, 0 , 0x0800, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2D  , 0x02  , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2D  , 0x11  , 15, 0 , 0x3001, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2D  , 0x13  , 15, 0 , 0xF400, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2D  , 0x1E  , 15, 0 , 0x0100, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x28  , 0x0B  , 15, 0 , 0x2390, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x28  , 0x0C  , 15, 0 , 0xA514, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x28  , 0x0D  , 15, 0 , 0xFE43, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x28  , 0x0E  , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x28  , 0x11  , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x28  , 0x15  , 15, 0 , 0x7A61, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x28  , 0x16  , 15, 0 , 0x0041, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x29  , 0x00  , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x29  , 0x01  , 15, 0 , 0x0800, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x29  , 0x02  , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x29  , 0x11  , 15, 0 , 0x3001, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x29  , 0x13  , 15, 0 , 0xF400, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x29  , 0x1E  , 15, 0 , 0x0100, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x26  , 0x0B  , 15, 0 , 0x2390, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x26  , 0x0C  , 15, 0 , 0xA514, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x26  , 0x0D  , 15, 0 , 0xFE43, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x26  , 0x0E  , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x26  , 0x11  , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x26  , 0x15  , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x26  , 0x16  , 15, 0 , 0x0041, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x27  , 0x00  , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x27  , 0x01  , 15, 0 , 0x0800, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x27  , 0x02  , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x27  , 0x11  , 15, 0 , 0x3001, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x27  , 0x13  , 15, 0 , 0xF400, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x27  , 0x1E  , 15, 0 , 0x0100, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x24  , 0x0B  , 15, 0 , 0x2390, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x24  , 0x0C  , 15, 0 , 0xA514, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x24  , 0x0D  , 15, 0 , 0xFE43, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x24  , 0x0E  , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x24  , 0x11  , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x24  , 0x15  , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x24  , 0x16  , 15, 0 , 0x0041, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x25  , 0x00  , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x25  , 0x01  , 15, 0 , 0x0800, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x25  , 0x02  , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x25  , 0x11  , 15, 0 , 0x3001, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x25  , 0x13  , 15, 0 , 0xF400, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x25  , 0x1E  , 15, 0 , 0x0100, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 24    , 18    , 15, 0 , 0x880D, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 24    , 19    , 15, 0 , 0x0024, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 24    , 20    , 15, 0 , 0x0036, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 24    , 21    , 15, 0 , 0x0035, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 24    , 22    , 15, 0 , 0x001A, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x1F  , 0x00  , 15, 0 , 0x001B, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x1F  , 0x00  , 15, 0 , 0x0000, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 90    , 20    , 7 , 0 , 0x01  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8261n_c_afe_conf[2] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbf1a, 3 , 2 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 90    , 21    , 15, 8 , 0x01  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8261n_c_uc_conf[92] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb820, 7 , 7 , 0x0   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbd8a, 5 , 3 , 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbd8c, 6 , 4 , 0x5   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8060, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 12, 10, 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8061, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 13, 0x5   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa466, 1 , 1 , 0x1   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8491, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x3D  , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x85b7, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf85, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85b7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcfaf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85b9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x85e6, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85bb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85bd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13af, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85bf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x862f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85c1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85c3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2faf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85c5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x862f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85c7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85c9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2faf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85cb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x862f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85cd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe085, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85cf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1ee1, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85d1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x851f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85d3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe28f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85d5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00e3, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85d7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8f01, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85d9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1b54, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85db},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xad37, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85dd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x03af, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85df},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4291, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85e1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf42, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85e3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf4e2, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85e5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8f03, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85e7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xad30, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85e9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x21e2, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85eb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8f04, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85ed},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe38f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85ef},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x051b, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85f1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x549f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85f3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x17ef, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85f5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x54e1, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85f7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8f03, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85f9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d11, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85fb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85fd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2f02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85ff},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6a4c, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8601},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d11, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8603},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8605},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3202, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8607},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6a4c, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8609},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef45, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x860b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe282, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x860d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x80af, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x860f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x40ee, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8611},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe18f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8613},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x03ad, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8615},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2810, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8617},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d13, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8619},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x861b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2f02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x861d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6a4c, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x861f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d11, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8621},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8623},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3202, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8625},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6a4c, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8627},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x023c, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8629},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2eaf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x862b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3b94, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x862d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xccc0, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x862f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8631},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xc020, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8633},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb818, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x428b, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb81a, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x40eb, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb81c, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3b91, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb81e, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb850, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb852, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb878, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb884, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb832, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0007, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8261n_c_uc2_conf[402] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb820, 7 , 7 , 0x1   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb87c, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8af6, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb87e, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf8b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8af6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0eaf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8af8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8b41, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8afa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf8b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8afc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4faf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8afe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8b5b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b00},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf8b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b02},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xb4af, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b04},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8bc0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b06},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf8b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b08},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xdaaf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b0a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8c2d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b0c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf8ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b0e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x49f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b10},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf70, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b12},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b14},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b16},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xad28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b18},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b1a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8a55, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b1c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xad28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b1e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0502, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b20},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5ee2, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b22},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xae0e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b24},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x025d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b26},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b28},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8d1e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b2a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xae06, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b2c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x025d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b2e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7002, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b30},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8d66, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b32},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe087, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b34},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1ef6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b36},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x27e4, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b38},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x871e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b3a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfcef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b3c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x94fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b3e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x04a1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b40},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0103, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b42},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x028d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b44},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x42e0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b46},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8a09, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b48},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef23, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b4a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf5e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b4c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5bac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b4e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5003, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b50},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf62, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b52},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8a02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b54},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8d66, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b56},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf62, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b58},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xb0bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b5a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x68e0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b5c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b5e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x72ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b60},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x31bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b62},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x68dd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b64},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b66},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x721e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b68},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x31ac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b6a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3819, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b6c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf68, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b6e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe902, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b70},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b72},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef31, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b74},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf68, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b76},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe602, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b78},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b7a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1e31, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b7c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xac38, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b7e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cee, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b80},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8933, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b82},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x02ae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b84},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0aee, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b86},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8933, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b88},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00ae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b8a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x04ee, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b8c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8933, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b8e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x01bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b90},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8ff9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b92},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe189, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b94},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x331a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b96},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x91db, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b98},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf69, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b9a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4c02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b9c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b9e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1f00, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1f22, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1b45, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xad27, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x05e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x870d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8baa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xae03, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bac},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe187, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bae},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0eaf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2d1a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0248, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf702, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8d8a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0222, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bba},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4faf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bbc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4176, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bbe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf8d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd402, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x70eb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf8d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe302, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x70eb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bca},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf8d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bcc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe902, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bce},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x70eb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd300, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0241, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7caf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x46b2, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf69, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bda},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bdc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bde},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe58f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf8d0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00d1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x697f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bea},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x53bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bec},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6f0a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bee},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xebbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6f0a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf4d6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bfa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bfc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bfe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x70f4, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c00},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c02},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c04},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x70eb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c06},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa600, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c08},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7f07, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c0a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd001, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c0c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe489, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c0e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfeae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c10},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c12},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6f52, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c14},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c16},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x72ad, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c18},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2803, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c1a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x16ae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c1c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xddd0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c1e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c20},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8ff8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c22},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf69, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c24},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c26},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6753, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c28},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf53, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c2a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa2ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c2c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x56ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c2e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x67cf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c30},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2f00, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c32},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x02ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c34},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x97d8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c36},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c38},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef74, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c3a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0271, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c3c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf5bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c3e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8948, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c40},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef47, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c42},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xdc19, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c44},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xddef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c46},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7502, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c48},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x71f5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c4a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef67, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c4c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe189, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c4e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33ad, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c50},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x280a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c52},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xad4f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c54},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x05d6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c56},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c58},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xae02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c5a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c61, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c5c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbdd8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c5e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c60},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef74, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c62},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0271, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c64},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf5bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c66},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x894a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c68},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef47, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c6a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xdc19, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c6c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xddcf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c6e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2f00, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c70},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x06ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c72},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x97d8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c74},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c76},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef74, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c78},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe189, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c7a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c7c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0050, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c7e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c80},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x46d8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c82},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c84},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef64, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c86},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d63, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c88},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d77, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c8a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1b67, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c8c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c8e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x48d8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c90},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c92},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef74, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c94},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1b67, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c96},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c98},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4ad8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c9a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c9c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef74, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c9e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xad5f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x05d7, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xae02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c71, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1a76, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8caa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xee87, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cac},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd500, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cae},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe186, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xc0e5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x892a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe186, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbde5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x892b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cba},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xad5f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cbc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x03af, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cbe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x32a5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef67, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3e00, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf6ac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4f03, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cca},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf5af, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ccc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x32a8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cce},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe189, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0145, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x46d8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cda},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef64, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cdc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d62, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cde},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d75, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1b67, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x48d8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1b64, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cea},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef76, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cec},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cee},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4ad8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d41, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1a74, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d72, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xee87, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cfa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd519, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cfc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe186, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cfe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xc1e5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d00},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x892a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d02},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe186, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d04},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbee5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d06},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x892b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d08},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xac5f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d0a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xb2ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d0c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x673e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d0e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00e2, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d10},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xac4f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d12},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xb8d7, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d14},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d16},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf32, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d18},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa8af, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d1a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3263, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d1c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf8ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d1e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x49f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d20},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d22},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3a02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d24},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d26},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xac28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d28},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x12bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d2a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6d63, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d2c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d2e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x72e5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d30},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8ffc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d32},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d34},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d36},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d38},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe58f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d3a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfdfc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d3c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef94, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d3e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d40},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf8ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d42},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x49f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d44},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d46},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3a02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d48},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d4a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xac28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d4c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x12e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d4e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8ffe, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d50},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d52},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6302, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d54},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6753, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d56},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe18f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d58},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d5a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6d6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d5c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d5e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x53fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d60},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef94, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d62},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d64},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf8ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d66},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x49f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d68},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d6a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3a02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d6c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d6e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xac28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d70},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x12e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d72},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8ffc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d74},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d76},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6302, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d78},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6753, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d7a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe18f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d7c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfdbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d7e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6d6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d80},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d82},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x53fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d84},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef94, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d86},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d88},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf8fa, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d8a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef69, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d8c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d8e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3a02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d90},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d92},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xad28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d94},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0ebf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d96},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8dd7, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d98},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d9a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf4bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d9c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8dd4, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d9e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8da0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf4ae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8da2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2ad1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8da4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0fbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8da6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8dda, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8da8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8daa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x53bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dac},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8ddd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dae},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8db0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xebd1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8db2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8db4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8de0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8db6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8db8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x53bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dba},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8de3, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dbc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dbe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf4d1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dc0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dc2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8de6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dc4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dc6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x53bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dc8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8de9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dca},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dcc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf4ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dce},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x96fe, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dd0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dd2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x77bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dd4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6c66, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dd6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbd6c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dd8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x30bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dda},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5444, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ddc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbd54, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dde},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x85bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8de0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5e55, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8de2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbd54, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8de4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa7bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8de6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5cbb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8de8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbd5c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dea},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb85e, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x62ba, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb860, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5e56, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb862, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6287, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb864, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2d07, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb886, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4170, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb888, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x46ad, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb88a, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5370, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb88c, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x316e, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb838, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00ff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb820, 7 , 7 , 0x0   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8261n_c_nctl0_conf[80] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb820, 7 , 7 , 0x1   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x801a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8023, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8035, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8035, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8035, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8035, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8035, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd719, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3bb7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8014, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd704, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x406e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x12db, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1301, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2a69, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8020, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9f01, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d45, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf01, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d43, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xc6bf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1da6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd708, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2630, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1b58, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7f63, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2c72, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x802d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8024, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1da6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd708, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2630, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1b58, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2318, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1b55, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x802d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA026, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA024, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA022, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA020, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA006, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA004, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1b4c, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA002, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d42, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA000, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x12d7, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA008, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0300, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb820, 7 , 7 , 0x0   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8261n_c_nctl1_conf[72] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb820, 7 , 7 , 0x1   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0010, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x801f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x38c1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8019, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd73e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6122, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0241, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x801d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd501, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce01, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa50f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd500, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x02e7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x38c1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8029, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd73e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6142, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0288, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8a0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x802d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd501, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce01, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa50f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd500, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00d3, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA08E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA08C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA08A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA088, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA086, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA084, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA082, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00ce, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA080, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x02e3, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA090, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0003, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb820, 7 , 7 , 0x0   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8261n_c_nctl2_conf[878] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb820, 7 , 7 , 0x1   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0020, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8029, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8217, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x82d0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x82f9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8322, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8336, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8336, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcb0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cc7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4127, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b05, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d18, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0f73, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8034, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8031, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1bf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd06d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1dd, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd06d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd06e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x37},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x38},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x39},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd05a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x40},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x41},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x42},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x43},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x44},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x45},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x46},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x47},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x48},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x49},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x142d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x50},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x51},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0ccf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x52},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x53},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x54},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c24, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x55},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x56},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x57},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x58},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x147c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x59},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1435, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1485, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x60},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa8c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x61},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x62},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x63},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x64},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x65},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cfc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x66},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0224, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x67},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0ca0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x68},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x69},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd162, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x70},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x71},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x72},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x73},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8840, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x74},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x75},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd045, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x76},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x77},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x78},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x79},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6127, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f3b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x88c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x80},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x81},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8350, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x82},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x84a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x83},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffb6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x84},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xb920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x85},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcd33, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x86},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x87},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x88},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x89},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6065, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f94, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x90},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffee, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x91},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xb820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x92},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x93},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x94},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x95},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7fa5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x96},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x97},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x98},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x99},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x147c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1435, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1485, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa2fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8880, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0440, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcd34, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xaa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xab},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xac3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xac},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xad},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xae},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xaf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa604, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x80bb, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xba},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd19f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x63f4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4368, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8d38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xca},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x80d7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xce},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x80d4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1f4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1c6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xda},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6074, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xde},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4056, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x61fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfff9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xea},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4070, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xeb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xec},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x81a4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xed},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xee},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xef},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xae80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x81a4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd05a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xff},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x100},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x101},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x102},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x103},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x104},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x105},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x106},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x107},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x108},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x142d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x109},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0ccf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c24, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x110},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x111},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x112},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x147c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x113},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x114},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x115},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1435, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x116},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x117},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x118},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1485, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x119},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa8c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cfc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x120},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0224, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x121},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0ca0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x122},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x123},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8604, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x124},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcd35, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x125},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd162, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x126},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x127},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x128},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x129},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8840, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd045, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x130},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x131},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x132},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x133},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6127, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x134},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x135},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f3b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x136},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x88c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x137},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x138},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x139},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8350, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x84a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffb8, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbb80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x140},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x141},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xb920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x142},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcd36, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x143},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x144},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x145},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x146},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x147},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x148},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9b80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x149},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6065, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f94, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffe8, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xb820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x150},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x151},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x152},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x153},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7fa5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x154},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x155},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x156},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x157},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x158},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x147c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x159},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1435, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1485, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa2fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x160},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x161},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8880, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x162},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x163},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0440, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x164},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcd37, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x165},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x166},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x167},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x168},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x169},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xac3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x170},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x171},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa604, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x172},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x173},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x174},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x817e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x175},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x176},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x817b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x177},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x178},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x179},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x180},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x181},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x182},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x183},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x184},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x185},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x186},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x187},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x188},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x189},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8d38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x190},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x819a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x191},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x192},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8197, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x193},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x194},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x195},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x196},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x197},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x198},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x199},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd189, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b05, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1aa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ab},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ac},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ad},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ae},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1af},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ba},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x142d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa180, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcd38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1be},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x81d4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x81cc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf013, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ca},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ce},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1da},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd13b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1db},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd055, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1dc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1dd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1de},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1df},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f7b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa302, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ea},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1eb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ec},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ed},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ee},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c12, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ef},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8206, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x81fe, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf013, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ff},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x200},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x201},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x202},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x203},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd040, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x204},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x205},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x206},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x207},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x208},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x209},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd16b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x210},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x211},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x212},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x213},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f2a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x214},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x215},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x087a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x216},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x217},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x646d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x218},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x219},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8231, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8227, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x220},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x221},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x222},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf01a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x223},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x224},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x225},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf017, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x226},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x227},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x228},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x229},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x230},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x231},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x232},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x233},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x234},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x235},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x236},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x237},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x238},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x239},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x240},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x241},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x242},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x243},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f29, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x244},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x245},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x246},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x247},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x248},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x249},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x250},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x251},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x252},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x253},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x254},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x255},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x256},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x257},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x142d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x258},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x259},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8bc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c09, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x260},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa420, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x261},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcd3b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x262},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x263},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x65ad, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x264},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x43c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x265},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x266},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x267},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x827b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x268},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x269},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8273, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf024, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd15d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x270},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x271},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf021, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x272},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x273},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x274},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1c6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x275},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x276},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf01c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x277},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd15d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x278},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x279},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf019, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf014, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x280},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x281},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf011, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x282},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x283},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x284},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x828e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x285},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x286},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x828b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x287},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1e5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x288},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x289},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf009, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd191, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x290},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd16b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x291},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x292},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x293},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x294},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x295},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x296},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x297},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x298},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x299},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f2c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x40e7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b05, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcd3c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x644d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2aa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x43c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ab},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ac},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ad},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x82c1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ae},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2af},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x82b9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf019, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf016, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ba},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf011, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd13e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2be},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf009, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ca},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ce},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0956, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2969, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x82f5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x82eb, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x82e1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2da},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd15c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2db},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2dc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf01a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2dd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2de},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2df},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf017, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd13e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ea},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2eb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ec},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ed},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ee},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ef},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x09a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2969, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x831e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8314, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x830a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ff},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x300},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x301},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x302},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x303},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd15d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x304},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x305},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf01a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x306},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x307},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x308},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf017, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x309},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd16b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x310},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x311},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x312},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x313},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x314},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x315},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x316},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x317},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x318},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x319},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x320},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0a39, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x321},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x322},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2969, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x323},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8332, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x324},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x325},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x832f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x326},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x327},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x832c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x328},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd18a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x329},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf009, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1c6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x330},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x331},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x332},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x333},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x334},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0506, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x335},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA10E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA10C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA10A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x04f4, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA108, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0a12, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA106, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0979, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA104, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x089f, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA102, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0692, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA100, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0f60, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA110, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x003f, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0020, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1ff8, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b0e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ff8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b0e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ff9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b0e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fff},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA164, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0baa, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA166, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c19, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA168, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1293, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA16A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA16C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA16E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA170, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA172, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA162, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0007, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb820, 7 , 7 , 0x0   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8261n_c_algxg_conf[184] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8165, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x22  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8167, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x33  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x827E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x68  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8013, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x39  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8ffb, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x14  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8ff9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x1e  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x82D9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x20  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x82DA, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x816E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xab  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8159, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x58  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x815A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x99  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8139, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x25  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8125, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x67  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8126, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x89  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x827D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x4c  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8205, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x4d  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8FFA, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x78  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8159, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x58  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x815A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x99  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x815B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x77  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x815C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xfb  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8125, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x67  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8126, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x89  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8127, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x77  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8128, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xf7  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x80DF, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x51  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x80E0, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x94  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x80F1, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x99  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x80F2, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x97  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x80F4, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xF9  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x80F7, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x99  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x80F8, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x9A  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x80FA, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x39  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x817B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x40  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x817C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xCC  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8149, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x28  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x814A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xE3  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x816D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xAA  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x80F3, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x75  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x80F9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x73  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x869D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xD   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8695, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x39  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x868D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x5   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x869E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x61  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8696, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x66  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x868E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xF3  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x869F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x15  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8697, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x3E  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x868F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xE   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86A0, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x89  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8698, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x95  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8690, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xC1  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86A1, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x35  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8699, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x64  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8691, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x32  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86A2, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xDC  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x869A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x59  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8692, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xC8  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86A3, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x1E  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x869B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x2F  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8693, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x13  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86A4, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x5A  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x869C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xC   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8694, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x7D  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86B5, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x9   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86AD, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x21  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86A5, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x4   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86B6, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x9   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86AE, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x6D  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86A6, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x88  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86B7, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x12  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86AF, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x2D  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86A7, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xC   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86B8, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x59  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86B0, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x72  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86A8, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x41  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86B9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x34  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86B1, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x57  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86A9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x30  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86BA, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xA2  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86B2, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xBD  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86AA, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x48  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86BB, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x22  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86B3, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x2F  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86AB, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x22  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86BC, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x10  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86B4, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x82  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86AC, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xF5  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x820A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x61  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x820B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x97  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x820C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x7C  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x820D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xB2  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8261n_c_alg_giga_conf[5] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa836, 15, 15, 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa85c, 7 , 7 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa85c, 6 , 3 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8367, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x5d  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8261n_c_normal_conf[21] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x817d, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x07  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb516, 6 , 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8ffe, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x04  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8fff, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x05  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8132, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x77  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8134, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x88  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x80ca, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x77  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x80cc, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x88  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8062, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x77  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8064, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x88  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x801E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0015, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8261n_c_dataram_conf[148] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb820, 7 , 7 , 0x0   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb896, 0 , 0 , 0x0   , RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb892, 15, 8 , 0x0   , RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC10B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xD5  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC10C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xD5  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC10D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xD5  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC10E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xD5  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC10F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xD5  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC110, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xD5  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC149, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x08  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC14A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x08  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC14B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x08  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC14C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x08  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC14D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x08  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC14E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x08  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC166, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xEE  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC167, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xEE  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC168, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x07  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC169, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x09  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC16A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x0B  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC16B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x0D  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC16C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x13  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC16D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x0E  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC16E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x11  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC16F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x14  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC170, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x17  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC171, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x15  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC172, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x10  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC173, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x0B  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC128, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xF7  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC129, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xF7  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC12A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xF8  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC12B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xF7  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC12C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xF6  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC12D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xF5  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC12E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xF2  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC12F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xF7  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC130, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xF5  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC131, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xF2  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC132, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xF0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC133, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xF1  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC134, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xF4  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC135, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xF7  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC118, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xEC  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC119, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xEB  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC11A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xEB  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC11B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xE8  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC11C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xE8  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC11D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xEA  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC11E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xE9  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC11F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xE7  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC120, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xE6  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC121, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xE7  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC122, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xE6  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC123, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xEA  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC124, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xEB  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC125, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xED  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC126, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xE3  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC127, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xE0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC156, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x19  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC157, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x1B  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC158, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x1B  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC159, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x1F  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC15A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x1E  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC15B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x1C  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC15C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x1D  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC15D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x20  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC15E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x22  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC15F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x21  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC160, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x25  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC161, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x20  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC162, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x21  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC163, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x27  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC164, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x57  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC165, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x74  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb896, 0 , 0 , 0x1   , RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8261n_c_rtct_conf[186] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa468, 1 , 0 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa422, 0 , 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc010, 9 , 9 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc010, 10, 10, 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc010, 14, 13, 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc000, 0 , 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_DELAY_MS, 0    , 0     , 0     , 0 , 0 , 1000  , RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8260, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x35  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8270, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0A  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8271, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x1F  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8280, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x1D  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8281, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8278, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x01  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8279, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8274, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x50  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8275, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x60  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8276, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x2B  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8277, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0A  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x04  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x80  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x02  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x80  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x03  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xC0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8263, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x37  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8264, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x20  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8261, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x37  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8262, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x20  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8265, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8273, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xE4  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8266, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x45  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8267, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xE0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8282, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8283, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0A  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8284, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8285, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x35  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8286, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8287, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xF7  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8288, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8289, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x01  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x44  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x30  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFC  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x52  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x02  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x04  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8290, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8291, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x64  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8292, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0B  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8293, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x20  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8294, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8295, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x12  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8296, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8297, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x59  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8298, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8299, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xEA  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xE3  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xD0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x35  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xBE  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A0, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A1, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x39  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A2, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xEC  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A3, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A4, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A5, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x35  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A6, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A7, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xBE  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A8, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x60  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AA, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0C  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AB, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x10  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AC, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AD, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x98  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AE, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AF, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x05  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B0, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B1, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x01  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B2, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x08  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B3, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B4, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B5, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x3D  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B6, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B7, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x46  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B8, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xF2  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x826D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x25  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x826E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x03  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F00, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x03  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F01, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x10  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F03, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0F  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F04, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x06  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F05, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x80  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa422, 1 , 1 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa422, 7 , 4 , 0xf   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 90    , 21    , 7 , 0 , 0x6   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8261n_c_rtct_5e_conf[186] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa468, 1 , 0 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa422, 0 , 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc010, 9 , 9 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc010, 10, 10, 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc010, 14, 13, 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc000, 0 , 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_DELAY_MS, 0    , 0     , 0     , 0 , 0 , 1000  , RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8260, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x35  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8270, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0A  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8271, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x1F  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8280, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x1D  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8281, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8278, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x01  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8279, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8274, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x50  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8275, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x60  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8276, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x2B  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8277, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0A  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x04  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x80  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x02  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x80  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x03  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xC0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8263, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x37  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8264, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x20  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8261, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x37  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8262, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x20  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8265, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8273, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xE4  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8266, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x45  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8267, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xE0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8282, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8283, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0A  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8284, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8285, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x35  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8286, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8287, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xF7  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8288, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8289, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x01  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x42  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xD0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFC  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x52  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x02  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x04  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8290, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8291, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x68  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8292, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0B  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8293, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x20  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8294, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8295, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x12  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8296, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8297, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x59  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8298, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8299, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xEA  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xEA  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xF0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xA5  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xBE  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A0, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A1, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x49  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A2, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xEC  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A3, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A4, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A5, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x35  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A6, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A7, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xBE  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A8, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x60  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AA, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0C  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AB, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x10  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AC, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AD, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x98  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AE, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AF, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x05  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B0, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B1, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x01  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B2, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x05  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B3, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x2F  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B4, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B5, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xDF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B6, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B7, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x25  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B8, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xF4  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x826D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x28  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x826E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x03  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F00, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x03  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F01, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x10  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F03, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0F  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F04, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x06  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F05, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x80  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa422, 1 , 1 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa422, 7 , 4 , 0xf   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 90    , 21    , 7 , 0 , 0x6   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8261n_c_rtct_6asftp_conf[186] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa468, 1 , 0 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa422, 0 , 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc010, 9 , 9 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc010, 10, 10, 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc010, 14, 13, 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc000, 0 , 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_DELAY_MS, 0    , 0     , 0     , 0 , 0 , 1000  , RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8260, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x35  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8270, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0A  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8271, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x1F  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8280, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x1D  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8281, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8278, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x01  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8279, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8274, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x50  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8275, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x60  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8276, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x2B  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8277, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0A  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x04  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x80  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x02  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x80  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x03  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xC0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8263, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x37  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8264, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x20  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8261, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x37  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8262, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x20  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8265, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8273, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xE4  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8266, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x45  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8267, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xE0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8282, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8283, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0A  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8284, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8285, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x35  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8286, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8287, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xF7  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8288, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8289, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x01  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x39  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xE0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFD  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xBF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x01  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x94  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8290, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8291, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x50  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8292, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x09  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8293, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x90  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8294, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8295, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x32  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8296, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8297, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x64  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8298, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8299, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xEA  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xEA  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xB0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xC0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xCE  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A0, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A1, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x4F  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A2, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xEC  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A3, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x22  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A4, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A5, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x35  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A6, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A7, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xBE  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A8, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x60  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AA, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0C  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AB, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x10  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AC, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AD, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x98  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AE, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AF, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x05  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B0, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B1, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x01  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B2, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x05  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B3, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x2F  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B4, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B5, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xDF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B6, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B7, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x10  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B8, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xF4  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x826D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x38  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x826E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x03  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F00, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x03  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F01, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x10  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F03, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0F  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F04, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x06  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F05, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x80  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa422, 1 , 1 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa422, 7 , 4 , 0xf   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 90    , 21    , 7 , 0 , 0x6   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8261n_c_rtct_6auutp_conf[186] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa468, 1 , 0 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa422, 0 , 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc010, 9 , 9 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc010, 10, 10, 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc010, 14, 13, 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc000, 0 , 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_DELAY_MS, 0    , 0     , 0     , 0 , 0 , 1000  , RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8260, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x35  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8270, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0A  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8271, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x1F  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8280, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x1D  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8281, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8278, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x01  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8279, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8274, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x50  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8275, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x60  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8276, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x2B  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8277, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0A  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x04  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x80  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x02  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x80  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x03  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xC0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8263, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x37  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8264, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x20  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8261, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x37  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8262, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x20  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8265, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8273, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xE4  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8266, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x45  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8267, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xE0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8282, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8283, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xDF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8284, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8285, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x95  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8286, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8287, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x40  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8288, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8289, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xCA  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x42  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x50  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFC  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x52  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x02  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x04  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8290, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8291, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x68  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8292, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0B  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8293, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x20  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8294, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8295, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x12  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8296, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8297, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x59  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8298, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8299, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xEA  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xE6  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xB0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x35  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xBE  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A0, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A1, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x59  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A2, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xEC  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A3, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A4, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A5, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x35  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A6, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A7, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xBE  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A8, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x60  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AA, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0C  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AB, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x10  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AC, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AD, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x98  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AE, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AF, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x05  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B0, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B1, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x01  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B2, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x03  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B3, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xDC  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B4, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B5, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x68  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B6, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B7, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x46  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B8, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xF2  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x826D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x38  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x826E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x03  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F00, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x03  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F01, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x10  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F03, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0F  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F04, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x06  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F05, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x80  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa422, 1 , 1 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa422, 7 , 4 , 0xf   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 90    , 21    , 7 , 0 , 0x6   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+};
+
diff --git a/sources/rtk-gp3000/src/hal/phy/construct/conf_rtl8261n_c_lp.c b/sources/rtk-gp3000/src/hal/phy/construct/conf_rtl8261n_c_lp.c
new file mode 100644
index 00000000..cd9ad93b
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/construct/conf_rtl8261n_c_lp.c
@@ -0,0 +1,2902 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (c) 2024 Realtek Semiconductor Corp. All rights reserved.
+ */
+//Date: Mon Jul 29 17:31:42 2024
+
+rtk_hwpatch_t rtl8261n_c_top_conf[17] = {
+    {RTK_PATCH_OP_TOP     , 0xf  , 2     , 20    , 15, 0 , 0x5   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 2     , 21    , 15, 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 2     , 22    , 15, 0 , 0x280 , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 2     , 23    , 15, 0 , 0x0014, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 3     , 16    , 15, 0 , 0x0300, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 3     , 17    , 15, 0 , 0x01ff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 3     , 18    , 15, 0 , 0x000c, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 3     , 19    , 15, 0 , 0x01ff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 3     , 20    , 15, 0 , 0x0200, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 3     , 21    , 15, 0 , 0x0015, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 3     , 22    , 15, 0 , 0x0200, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 3     , 23    , 15, 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 4     , 16    , 15, 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 13    , 23    , 8 , 5 , 0x6   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 90    , 18    , 15, 0 , 0x15a , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 90    , 19    , 15, 0 , 0x15a , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 90    , 20    , 15, 8 , 0x01  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8261n_c_sds_conf[103] = {
+    {RTK_PATCH_OP_TOP     , 0xf  , 24    , 18    , 15, 0 , 0x881F, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 24    , 19    , 15, 0 , 0x003F, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 24    , 20    , 15, 0 , 0x003F, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 24    , 21    , 15, 0 , 0x003F, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 24    , 22    , 15, 0 , 0x001F, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x06  , 0x0D  , 15, 0 , 0x0F00, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x06  , 0x0E  , 15, 0 , 0x3F5A, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x07  , 0x10  , 15, 12, 0x8   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x07  , 0x10  , 7 , 0 , 0x3   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x06  , 0x1D  , 15, 0 , 0x0600, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x21  , 0x00  , 15, 0 , 0x4902, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x21  , 0x08  , 15, 0 , 0x0FC0, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x21  , 0x09  , 15, 0 , 0x33F0, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x21  , 0x0C  , 15, 0 , 0x08BF, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x21  , 0x12  , 15, 0 , 0x8000, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x36  , 0x07  , 15, 0 , 0x04C0, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x36  , 0x08  , 15, 0 , 0x2000, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2E  , 0x0B  , 15, 0 , 0x2390, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2E  , 0x0C  , 15, 0 , 0xAA17, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2E  , 0x0D  , 15, 0 , 0xFE40, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2E  , 0x0E  , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2E  , 0x11  , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2E  , 0x15  , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2E  , 0x16  , 15, 0 , 0x0041, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2F  , 0x00  , 15, 0 , 0x1F00, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2F  , 0x01  , 15, 0 , 0x2800, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2F  , 0x02  , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2F  , 0x11  , 15, 0 , 0x3000, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2F  , 0x13  , 15, 0 , 0xF400, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2F  , 0x1E  , 15, 0 , 0x0500, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x34  , 0x0B  , 15, 0 , 0x2390, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x34  , 0x0C  , 15, 0 , 0xA517, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x34  , 0x0D  , 15, 0 , 0xFE41, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x34  , 0x0E  , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x34  , 0x11  , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x34  , 0x15  , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x34  , 0x16  , 15, 0 , 0x0041, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x35  , 0x00  , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x35  , 0x01  , 15, 0 , 0x0800, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x35  , 0x02  , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x35  , 0x11  , 15, 0 , 0x3001, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x35  , 0x13  , 15, 0 , 0xF400, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x35  , 0x1E  , 15, 0 , 0x0100, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2C  , 0x0B  , 15, 0 , 0x2390, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2C  , 0x0C  , 15, 0 , 0xA517, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2C  , 0x0D  , 15, 0 , 0xFE41, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2C  , 0x0E  , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2C  , 0x11  , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2C  , 0x15  , 15, 0 , 0x7A61, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2C  , 0x16  , 15, 0 , 0x0041, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2D  , 0x00  , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2D  , 0x01  , 15, 0 , 0x0800, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2D  , 0x02  , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2D  , 0x11  , 15, 0 , 0x3001, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2D  , 0x13  , 15, 0 , 0xF400, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2D  , 0x1E  , 15, 0 , 0x0100, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x28  , 0x0B  , 15, 0 , 0x2390, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x28  , 0x0C  , 15, 0 , 0xA514, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x28  , 0x0D  , 15, 0 , 0xFE43, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x28  , 0x0E  , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x28  , 0x11  , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x28  , 0x15  , 15, 0 , 0x7A61, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x28  , 0x16  , 15, 0 , 0x0041, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x29  , 0x00  , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x29  , 0x01  , 15, 0 , 0x0800, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x29  , 0x02  , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x29  , 0x11  , 15, 0 , 0x3001, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x29  , 0x13  , 15, 0 , 0xF400, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x29  , 0x1E  , 15, 0 , 0x0100, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x26  , 0x0B  , 15, 0 , 0x2390, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x26  , 0x0C  , 15, 0 , 0xA514, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x26  , 0x0D  , 15, 0 , 0xFE43, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x26  , 0x0E  , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x26  , 0x11  , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x26  , 0x15  , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x26  , 0x16  , 15, 0 , 0x0041, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x27  , 0x00  , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x27  , 0x01  , 15, 0 , 0x0800, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x27  , 0x02  , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x27  , 0x11  , 15, 0 , 0x3001, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x27  , 0x13  , 15, 0 , 0xF400, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x27  , 0x1E  , 15, 0 , 0x0100, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x24  , 0x0B  , 15, 0 , 0x2390, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x24  , 0x0C  , 15, 0 , 0xA514, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x24  , 0x0D  , 15, 0 , 0xFE43, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x24  , 0x0E  , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x24  , 0x11  , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x24  , 0x15  , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x24  , 0x16  , 15, 0 , 0x0041, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x25  , 0x00  , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x25  , 0x01  , 15, 0 , 0x0800, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x25  , 0x02  , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x25  , 0x11  , 15, 0 , 0x3001, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x25  , 0x13  , 15, 0 , 0xF400, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x25  , 0x1E  , 15, 0 , 0x0100, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 24    , 18    , 15, 0 , 0x880D, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 24    , 19    , 15, 0 , 0x0024, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 24    , 20    , 15, 0 , 0x0036, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 24    , 21    , 15, 0 , 0x0035, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 24    , 22    , 15, 0 , 0x001A, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x1F  , 0x00  , 15, 0 , 0x001B, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x1F  , 0x00  , 15, 0 , 0x0000, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 90    , 20    , 7 , 0 , 0x01  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8261n_c_afe_conf[31] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbf1a, 3 , 2 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbfb0, 15, 13, 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbf9c, 15, 13, 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbfb0, 12, 10, 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbf9c, 12, 10, 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbfb0, 9 , 7 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbfb0, 6 , 4 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbfa0, 15, 13, 0x5   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbf14, 15, 13, 0x5   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbf14, 4 , 2 , 0x5   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbfb0, 1 , 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbf9c, 9 , 8 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbf9c, 7 , 6 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbf14, 12, 10, 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbf14, 9 , 7 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbf12, 5 , 3 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbf10, 2 , 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbf14, 1 , 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbf14, 6 , 5 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbf8e, 3 , 3 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbfa8, 2 , 2 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbfa8, 3 , 3 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbf1c, 4 , 4 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8061, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 10, 8 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbc3c, 15, 0 , 0x100 , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbf18, 15, 13, 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbf18, 12, 11, 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbd5c, 6 , 4 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbd80, 15, 0 , 0x280 , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 90    , 21    , 15, 8 , 0x03  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8261n_c_uc_conf[92] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb820, 7 , 7 , 0x0   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbd8a, 5 , 3 , 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbd8c, 6 , 4 , 0x5   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8060, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 12, 10, 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8061, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 13, 0x5   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa466, 1 , 1 , 0x1   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8491, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x3D  , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x85b7, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf85, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85b7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcfaf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85b9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x85e6, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85bb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85bd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13af, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85bf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x862f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85c1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85c3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2faf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85c5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x862f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85c7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85c9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2faf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85cb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x862f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85cd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe085, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85cf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1ee1, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85d1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x851f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85d3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe28f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85d5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00e3, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85d7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8f01, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85d9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1b54, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85db},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xad37, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85dd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x03af, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85df},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4291, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85e1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf42, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85e3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf4e2, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85e5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8f03, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85e7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xad30, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85e9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x21e2, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85eb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8f04, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85ed},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe38f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85ef},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x051b, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85f1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x549f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85f3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x17ef, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85f5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x54e1, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85f7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8f03, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85f9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d11, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85fb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85fd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2f02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85ff},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6a4c, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8601},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d11, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8603},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8605},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3202, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8607},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6a4c, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8609},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef45, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x860b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe282, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x860d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x80af, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x860f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x40ee, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8611},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe18f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8613},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x03ad, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8615},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2810, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8617},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d13, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8619},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x861b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2f02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x861d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6a4c, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x861f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d11, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8621},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8623},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3202, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8625},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6a4c, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8627},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x023c, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8629},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2eaf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x862b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3b94, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x862d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xccc0, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x862f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8631},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xc020, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8633},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb818, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x428b, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb81a, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x40eb, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb81c, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3b91, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb81e, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb850, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb852, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb878, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb884, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb832, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0007, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8261n_c_uc2_conf[402] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb820, 7 , 7 , 0x1   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb87c, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8af6, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb87e, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf8b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8af6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0eaf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8af8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8b41, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8afa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf8b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8afc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4faf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8afe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8b5b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b00},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf8b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b02},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xb4af, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b04},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8bc0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b06},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf8b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b08},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xdaaf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b0a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8c2d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b0c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf8ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b0e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x49f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b10},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf70, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b12},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b14},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b16},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xad28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b18},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b1a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8a55, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b1c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xad28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b1e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0502, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b20},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5ee2, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b22},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xae0e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b24},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x025d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b26},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b28},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8d1e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b2a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xae06, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b2c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x025d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b2e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7002, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b30},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8d66, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b32},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe087, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b34},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1ef6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b36},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x27e4, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b38},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x871e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b3a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfcef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b3c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x94fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b3e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x04a1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b40},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0103, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b42},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x028d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b44},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x42e0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b46},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8a09, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b48},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef23, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b4a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf5e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b4c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5bac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b4e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5003, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b50},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf62, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b52},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8a02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b54},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8d66, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b56},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf62, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b58},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xb0bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b5a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x68e0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b5c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b5e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x72ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b60},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x31bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b62},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x68dd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b64},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b66},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x721e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b68},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x31ac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b6a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3819, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b6c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf68, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b6e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe902, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b70},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b72},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef31, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b74},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf68, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b76},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe602, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b78},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b7a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1e31, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b7c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xac38, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b7e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cee, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b80},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8933, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b82},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x02ae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b84},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0aee, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b86},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8933, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b88},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00ae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b8a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x04ee, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b8c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8933, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b8e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x01bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b90},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8ff9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b92},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe189, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b94},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x331a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b96},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x91db, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b98},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf69, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b9a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4c02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b9c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b9e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1f00, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1f22, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1b45, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xad27, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x05e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x870d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8baa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xae03, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bac},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe187, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bae},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0eaf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2d1a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0248, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf702, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8d8a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0222, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bba},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4faf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bbc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4176, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bbe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf8d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd402, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x70eb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf8d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe302, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x70eb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bca},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf8d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bcc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe902, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bce},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x70eb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd300, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0241, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7caf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x46b2, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf69, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bda},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bdc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bde},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe58f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf8d0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00d1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x697f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bea},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x53bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bec},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6f0a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bee},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xebbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6f0a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf4d6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bfa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bfc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bfe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x70f4, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c00},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c02},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c04},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x70eb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c06},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa600, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c08},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7f07, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c0a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd001, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c0c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe489, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c0e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfeae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c10},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c12},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6f52, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c14},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c16},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x72ad, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c18},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2803, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c1a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x16ae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c1c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xddd0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c1e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c20},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8ff8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c22},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf69, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c24},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c26},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6753, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c28},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf53, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c2a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa2ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c2c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x56ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c2e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x67cf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c30},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2f00, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c32},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x02ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c34},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x97d8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c36},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c38},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef74, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c3a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0271, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c3c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf5bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c3e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8948, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c40},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef47, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c42},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xdc19, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c44},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xddef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c46},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7502, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c48},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x71f5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c4a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef67, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c4c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe189, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c4e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33ad, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c50},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x280a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c52},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xad4f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c54},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x05d6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c56},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c58},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xae02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c5a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c61, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c5c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbdd8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c5e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c60},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef74, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c62},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0271, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c64},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf5bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c66},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x894a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c68},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef47, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c6a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xdc19, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c6c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xddcf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c6e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2f00, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c70},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x06ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c72},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x97d8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c74},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c76},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef74, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c78},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe189, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c7a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c7c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0050, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c7e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c80},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x46d8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c82},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c84},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef64, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c86},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d63, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c88},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d77, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c8a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1b67, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c8c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c8e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x48d8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c90},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c92},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef74, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c94},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1b67, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c96},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c98},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4ad8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c9a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c9c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef74, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c9e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xad5f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x05d7, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xae02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c71, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1a76, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8caa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xee87, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cac},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd500, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cae},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe186, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xc0e5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x892a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe186, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbde5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x892b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cba},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xad5f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cbc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x03af, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cbe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x32a5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef67, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3e00, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf6ac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4f03, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cca},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf5af, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ccc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x32a8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cce},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe189, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0145, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x46d8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cda},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef64, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cdc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d62, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cde},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d75, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1b67, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x48d8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1b64, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cea},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef76, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cec},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cee},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4ad8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x19d9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d41, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1a74, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d72, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xee87, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cfa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd519, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cfc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe186, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cfe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xc1e5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d00},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x892a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d02},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe186, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d04},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbee5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d06},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x892b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d08},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xac5f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d0a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xb2ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d0c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x673e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d0e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00e2, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d10},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xac4f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d12},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xb8d7, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d14},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d16},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf32, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d18},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa8af, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d1a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3263, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d1c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf8ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d1e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x49f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d20},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d22},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3a02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d24},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d26},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xac28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d28},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x12bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d2a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6d63, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d2c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d2e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x72e5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d30},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8ffc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d32},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d34},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6f02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d36},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d38},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe58f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d3a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfdfc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d3c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef94, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d3e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d40},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf8ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d42},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x49f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d44},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d46},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3a02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d48},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d4a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xac28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d4c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x12e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d4e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8ffe, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d50},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d52},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6302, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d54},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6753, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d56},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe18f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d58},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d5a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6d6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d5c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d5e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x53fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d60},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef94, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d62},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d64},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf8ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d66},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x49f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d68},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d6a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3a02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d6c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d6e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xac28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d70},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x12e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d72},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8ffc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d74},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d76},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6302, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d78},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6753, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d7a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe18f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d7c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfdbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d7e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6d6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d80},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d82},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x53fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d84},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef94, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d86},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d88},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf8fa, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d8a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef69, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d8c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d8e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3a02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d90},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6772, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d92},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xad28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d94},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0ebf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d96},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8dd7, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d98},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d9a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf4bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d9c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8dd4, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d9e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8da0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf4ae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8da2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2ad1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8da4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0fbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8da6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8dda, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8da8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8daa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x53bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dac},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8ddd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dae},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8db0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xebd1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8db2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8db4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8de0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8db6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8db8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x53bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dba},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8de3, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dbc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dbe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf4d1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dc0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dc2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8de6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dc4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0267, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dc6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x53bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dc8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8de9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dca},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dcc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf4ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dce},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x96fe, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dd0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dd2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x77bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dd4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6c66, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dd6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbd6c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dd8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x30bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dda},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5444, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ddc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbd54, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dde},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x85bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8de0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5e55, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8de2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbd54, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8de4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa7bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8de6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5cbb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8de8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbd5c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8dea},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb85e, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x62ba, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb860, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5e56, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb862, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6287, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb864, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2d07, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb886, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4170, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb888, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x46ad, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb88a, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5370, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb88c, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x316e, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb838, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00ff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb820, 7 , 7 , 0x0   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8261n_c_nctl0_conf[80] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb820, 7 , 7 , 0x1   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x801a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8023, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8035, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8035, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8035, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8035, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8035, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd719, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3bb7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8014, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd704, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x406e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x12db, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1301, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2a69, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8020, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9f01, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d45, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf01, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d43, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xc6bf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1da6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd708, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2630, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1b58, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7f63, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2c72, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x802d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8024, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1da6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd708, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2630, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1b58, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2318, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1b55, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x802d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA026, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA024, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA022, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA020, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA006, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA004, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1b4c, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA002, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d42, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA000, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x12d7, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA008, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0300, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb820, 7 , 7 , 0x0   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8261n_c_nctl1_conf[72] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb820, 7 , 7 , 0x1   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0010, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x801f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x802f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x38c1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8019, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd73e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6122, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0241, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x801d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd501, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce01, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa50f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd500, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x02e7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x38c1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8029, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd73e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6142, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0288, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8a0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x802d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd501, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce01, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa50f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd500, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00d3, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA08E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA08C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA08A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA088, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA086, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA084, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA082, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00ce, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA080, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x02e3, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA090, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0003, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb820, 7 , 7 , 0x0   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8261n_c_nctl2_conf[878] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb820, 7 , 7 , 0x1   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0020, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8029, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8217, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x82d0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x82f9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8322, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8336, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8336, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcb0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cc7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4127, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b05, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d18, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0f73, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8034, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8031, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1bf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd06d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1dd, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd06d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd06e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x37},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x38},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x39},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd05a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x40},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x41},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x42},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x43},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x44},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x45},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x46},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x47},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x48},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x49},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x142d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x50},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x51},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0ccf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x52},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x53},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x54},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c24, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x55},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x56},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x57},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x58},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x147c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x59},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1435, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1485, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x60},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa8c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x61},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x62},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x63},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x64},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x65},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cfc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x66},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0224, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x67},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0ca0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x68},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x69},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd162, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x70},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x71},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x72},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x73},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8840, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x74},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x75},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd045, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x76},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x77},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x78},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x79},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6127, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f3b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x88c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x80},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x81},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8350, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x82},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x84a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x83},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffb6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x84},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xb920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x85},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcd33, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x86},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x87},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x88},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x89},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6065, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f94, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x90},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffee, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x91},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xb820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x92},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x93},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x94},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x95},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7fa5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x96},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x97},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x98},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x99},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x147c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1435, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1485, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa2fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8880, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0440, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcd34, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xaa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xab},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xac3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xac},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xad},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xae},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xaf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa604, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x80bb, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xba},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd19f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x63f4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4368, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8d38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xca},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x80d7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xce},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x80d4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1f4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1c6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xda},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6074, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xde},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4056, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x61fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfff9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xea},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4070, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xeb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xec},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x81a4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xed},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xee},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xef},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xae80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x81a4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd05a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xff},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x100},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x101},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x102},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x103},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x104},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x105},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x106},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x107},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x108},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x142d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x109},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0ccf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c24, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x110},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x111},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x112},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x147c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x113},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x114},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x115},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1435, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x116},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x117},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x118},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1485, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x119},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa8c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cfc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x120},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0224, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x121},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0ca0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x122},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x123},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8604, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x124},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcd35, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x125},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd162, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x126},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x127},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x128},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x129},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8840, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd045, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x130},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x131},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x132},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x133},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6127, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x134},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x135},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f3b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x136},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x88c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x137},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x138},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x139},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8350, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x84a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffb8, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbb80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x140},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x141},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xb920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x142},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcd36, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x143},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x144},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x145},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x146},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x147},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x148},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9b80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x149},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6065, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f94, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffe8, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xb820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x150},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x151},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x152},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x153},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7fa5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x154},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x155},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x156},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x157},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x158},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x147c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x159},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1435, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1485, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa2fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x160},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x161},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8880, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x162},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x163},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0440, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x164},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcd37, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x165},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x166},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x167},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x168},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x169},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xac3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x170},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x171},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa604, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x172},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x173},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x174},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x817e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x175},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x176},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x817b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x177},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x178},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x179},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x180},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x181},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x182},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x183},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x184},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x185},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x186},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x187},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x188},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x189},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8d38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x190},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x819a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x191},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x192},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8197, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x193},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x194},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x195},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x196},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x197},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x198},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x199},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd189, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b05, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1aa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ab},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ac},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ad},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ae},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1af},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ba},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x142d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa180, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcd38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1be},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x81d4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x81cc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf013, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ca},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ce},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1da},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd13b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1db},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd055, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1dc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1dd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1de},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1df},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f7b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa302, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ea},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1eb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ec},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ed},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ee},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c12, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ef},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8206, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x81fe, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf013, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ff},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x200},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x201},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x202},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x203},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd040, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x204},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x205},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x206},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x207},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x208},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x209},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd16b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x210},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x211},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x212},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x213},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f2a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x214},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x215},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x087a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x216},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x217},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x646d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x218},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x219},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8231, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8227, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x220},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x221},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x222},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf01a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x223},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x224},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x225},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf017, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x226},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x227},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x228},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x229},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x230},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x231},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x232},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x233},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x234},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x235},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x236},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x237},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x238},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x239},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x240},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x241},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x242},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x243},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f29, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x244},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x245},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x246},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x247},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x248},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x249},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x250},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x251},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x252},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x253},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x254},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x255},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x256},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x257},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x142d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x258},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x259},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8bc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c09, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x260},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa420, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x261},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcd3b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x262},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x263},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x65ad, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x264},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x43c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x265},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x266},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x267},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x827b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x268},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x269},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8273, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf024, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd15d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x270},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x271},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf021, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x272},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x273},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x274},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1c6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x275},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x276},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf01c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x277},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd15d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x278},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x279},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf019, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf014, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x280},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x281},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf011, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x282},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x283},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x284},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x828e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x285},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x286},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x828b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x287},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1e5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x288},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x289},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf009, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd191, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x290},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd16b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x291},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x292},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x293},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1418, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x294},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x295},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1463, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x296},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x297},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x298},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x299},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f2c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x40e7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b05, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcd3c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x644d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2aa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x43c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ab},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ac},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ad},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x82c1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ae},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2af},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x82b9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf019, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf016, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ba},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf011, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd13e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2be},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf009, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ca},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ce},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0956, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2969, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x82f5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x82eb, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x82e1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2da},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd15c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2db},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2dc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf01a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2dd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2de},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2df},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf017, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd13e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ea},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2eb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ec},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ed},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ee},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ef},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x09a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2969, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x831e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8314, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x830a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ff},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x300},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x301},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x302},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x303},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd15d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x304},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x305},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf01a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x306},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x307},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x308},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf017, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x309},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd16b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x310},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x311},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x312},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x313},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x314},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x315},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x316},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x317},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x318},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x319},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x320},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0a39, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x321},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x322},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2969, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x323},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8332, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x324},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x325},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x832f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x326},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x327},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x832c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x328},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd18a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x329},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf009, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1c6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x330},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x331},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x332},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x333},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x334},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0506, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x335},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA10E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA10C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA10A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x04f4, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA108, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0a12, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA106, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0979, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA104, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x089f, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA102, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0692, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA100, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0f60, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA110, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x003f, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0020, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1ff8, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b0e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ff8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b0e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ff9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b0e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fff},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA164, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0baa, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA166, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c19, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA168, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1293, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA16A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA16C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA16E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA170, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA172, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA162, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0007, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb820, 7 , 7 , 0x0   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8261n_c_algxg_conf[184] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8165, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x22  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8167, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x33  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x827E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x68  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8013, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x39  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8ffb, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x14  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8ff9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x1e  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x82D9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x20  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x82DA, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x816E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xab  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8159, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x58  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x815A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x99  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8139, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x25  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8125, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x67  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8126, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x89  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x827D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x4c  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8205, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x4d  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8FFA, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x78  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8159, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x58  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x815A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x99  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x815B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x77  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x815C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xfb  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8125, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x67  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8126, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x89  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8127, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x77  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8128, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xf7  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x80DF, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x51  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x80E0, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x94  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x80F1, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x99  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x80F2, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x97  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x80F4, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xF9  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x80F7, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x99  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x80F8, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x9A  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x80FA, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x39  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x817B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x40  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x817C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xCC  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8149, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x28  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x814A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xE3  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x816D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xAA  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x80F3, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x75  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x80F9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x73  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x869D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xD   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8695, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x39  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x868D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x5   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x869E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x61  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8696, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x66  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x868E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xF3  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x869F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x15  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8697, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x3E  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x868F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xE   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86A0, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x89  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8698, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x95  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8690, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xC1  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86A1, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x35  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8699, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x64  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8691, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x32  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86A2, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xDC  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x869A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x59  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8692, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xC8  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86A3, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x1E  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x869B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x2F  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8693, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x13  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86A4, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x5A  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x869C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xC   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8694, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x7D  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86B5, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x9   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86AD, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x21  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86A5, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x4   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86B6, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x9   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86AE, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x6D  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86A6, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x88  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86B7, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x12  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86AF, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x2D  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86A7, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xC   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86B8, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x59  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86B0, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x72  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86A8, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x41  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86B9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x34  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86B1, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x57  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86A9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x30  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86BA, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xA2  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86B2, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xBD  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86AA, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x48  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86BB, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x22  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86B3, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x2F  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86AB, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x22  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86BC, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x10  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86B4, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x82  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x86AC, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xF5  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x820A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x61  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x820B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x97  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x820C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x7C  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x820D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xB2  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8261n_c_alg_giga_conf[5] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa836, 15, 15, 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa85c, 7 , 7 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa85c, 6 , 3 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8367, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x5d  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8261n_c_normal_conf[91] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x817d, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x07  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb516, 6 , 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8ffe, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x04  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8fff, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x05  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8132, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x77  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8134, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x88  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x80ca, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x77  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x80cc, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x88  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8062, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x77  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8064, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x88  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x801E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0015, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xac1c, 8 , 7 , 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xac1e, 13, 12, 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xad96, 7 , 6 , 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xad96, 5 , 4 , 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xad96, 3 , 2 , 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xad96, 1 , 0 , 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xad98, 3 , 2 , 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xad98, 1 , 0 , 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xae38, 3 , 2 , 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xae38, 1 , 0 , 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb00a, 14, 14, 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb006, 13, 12, 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb00a, 10, 10, 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb00a, 9 , 9 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb00a, 8 , 8 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb008, 13, 12, 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb008, 9 , 8 , 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb008, 5 , 4 , 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb00a, 6 , 6 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb00a, 4 , 4 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb00a, 2 , 2 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb10a, 14, 14, 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb106, 13, 12, 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb10a, 10, 10, 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb10a, 9 , 9 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb10a, 8 , 8 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb108, 13, 12, 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb108, 9 , 8 , 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb108, 5 , 4 , 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb10a, 6 , 6 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb10a, 4 , 4 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb10a, 2 , 2 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb20a, 14, 14, 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb206, 13, 12, 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb20a, 10, 10, 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb20a, 9 , 9 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb20a, 8 , 8 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb208, 13, 12, 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb208, 9 , 8 , 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb208, 5 , 4 , 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb20a, 6 , 6 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb20a, 4 , 4 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb20a, 2 , 2 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb30a, 14, 14, 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb306, 13, 12, 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb30a, 10, 10, 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb30a, 9 , 9 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb30a, 8 , 8 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb308, 13, 12, 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb308, 9 , 8 , 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb308, 5 , 4 , 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb30a, 6 , 6 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb30a, 4 , 4 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb30a, 2 , 2 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x82DF, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8267, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x81EF, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x829A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8222, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x81AA, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x829B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x7   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8223, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x7   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8261n_c_dataram_conf[148] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb820, 7 , 7 , 0x0   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb896, 0 , 0 , 0x0   , RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb892, 15, 8 , 0x0   , RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC10B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xD5  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC10C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xD5  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC10D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xD5  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC10E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xD5  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC10F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xD5  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC110, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xD5  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC149, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x08  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC14A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x08  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC14B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x08  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC14C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x08  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC14D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x08  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC14E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x08  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC166, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xEE  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC167, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xEE  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC168, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x07  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC169, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x09  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC16A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x0B  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC16B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x0D  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC16C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x13  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC16D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x0E  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC16E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x11  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC16F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x14  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC170, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x17  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC171, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x15  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC172, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x10  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC173, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x0B  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC128, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xF7  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC129, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xF7  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC12A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xF8  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC12B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xF7  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC12C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xF6  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC12D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xF5  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC12E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xF2  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC12F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xF7  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC130, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xF5  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC131, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xF2  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC132, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xF0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC133, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xF1  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC134, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xF4  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC135, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xF7  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC118, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xEC  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC119, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xEB  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC11A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xEB  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC11B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xE8  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC11C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xE8  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC11D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xEA  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC11E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xE9  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC11F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xE7  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC120, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xE6  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC121, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xE7  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC122, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xE6  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC123, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xEA  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC124, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xEB  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC125, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xED  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC126, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xE3  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC127, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xE0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC156, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x19  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC157, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x1B  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC158, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x1B  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC159, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x1F  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC15A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x1E  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC15B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x1C  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC15C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x1D  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC15D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x20  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC15E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x22  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC15F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x21  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC160, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x25  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC161, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x20  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC162, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x21  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC163, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x27  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC164, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x57  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC165, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x74  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb896, 0 , 0 , 0x1   , RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8261n_c_rtct_conf[186] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa468, 1 , 0 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa422, 0 , 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc010, 9 , 9 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc010, 10, 10, 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc010, 14, 13, 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc000, 0 , 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_DELAY_MS, 0    , 0     , 0     , 0 , 0 , 1000  , RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8260, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x35  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8270, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0A  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8271, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x1F  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8280, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x1D  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8281, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8278, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x01  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8279, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8274, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x50  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8275, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x60  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8276, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x2B  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8277, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0A  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x04  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x80  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x02  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x80  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x03  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xC0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8263, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x37  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8264, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x20  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8261, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x37  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8262, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x20  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8265, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8273, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xE4  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8266, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x45  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8267, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xE0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8282, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8283, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0A  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8284, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8285, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x35  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8286, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8287, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xF7  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8288, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8289, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x01  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x44  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x30  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFC  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x52  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x02  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x04  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8290, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8291, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x64  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8292, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0B  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8293, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x20  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8294, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8295, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x12  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8296, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8297, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x59  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8298, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8299, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xEA  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xE3  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xD0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x35  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xBE  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A0, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A1, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x39  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A2, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xEC  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A3, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A4, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A5, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x35  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A6, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A7, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xBE  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A8, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x60  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AA, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0C  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AB, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x10  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AC, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AD, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x98  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AE, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AF, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x05  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B0, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B1, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x01  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B2, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x08  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B3, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B4, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B5, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x3D  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B6, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B7, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x46  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B8, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xF2  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x826D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x25  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x826E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x03  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F00, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x03  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F01, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x10  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F03, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0F  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F04, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x06  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F05, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x80  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa422, 1 , 1 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa422, 7 , 4 , 0xf   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 90    , 21    , 7 , 0 , 0x6   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8261n_c_rtct_5e_conf[186] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa468, 1 , 0 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa422, 0 , 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc010, 9 , 9 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc010, 10, 10, 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc010, 14, 13, 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc000, 0 , 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_DELAY_MS, 0    , 0     , 0     , 0 , 0 , 1000  , RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8260, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x35  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8270, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0A  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8271, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x1F  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8280, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x1D  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8281, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8278, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x01  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8279, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8274, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x50  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8275, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x60  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8276, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x2B  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8277, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0A  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x04  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x80  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x02  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x80  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x03  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xC0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8263, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x37  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8264, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x20  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8261, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x37  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8262, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x20  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8265, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8273, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xE4  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8266, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x45  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8267, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xE0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8282, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8283, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0A  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8284, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8285, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x35  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8286, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8287, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xF7  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8288, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8289, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x01  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x42  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xD0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFC  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x52  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x02  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x04  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8290, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8291, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x68  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8292, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0B  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8293, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x20  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8294, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8295, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x12  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8296, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8297, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x59  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8298, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8299, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xEA  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xEA  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xF0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xA5  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xBE  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A0, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A1, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x49  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A2, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xEC  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A3, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A4, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A5, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x35  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A6, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A7, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xBE  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A8, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x60  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AA, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0C  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AB, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x10  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AC, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AD, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x98  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AE, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AF, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x05  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B0, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B1, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x01  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B2, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x05  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B3, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x2F  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B4, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B5, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xDF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B6, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B7, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x25  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B8, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xF4  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x826D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x28  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x826E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x03  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F00, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x03  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F01, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x10  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F03, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0F  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F04, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x06  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F05, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x80  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa422, 1 , 1 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa422, 7 , 4 , 0xf   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 90    , 21    , 7 , 0 , 0x6   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8261n_c_rtct_6asftp_conf[186] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa468, 1 , 0 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa422, 0 , 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc010, 9 , 9 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc010, 10, 10, 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc010, 14, 13, 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc000, 0 , 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_DELAY_MS, 0    , 0     , 0     , 0 , 0 , 1000  , RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8260, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x35  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8270, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0A  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8271, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x1F  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8280, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x1D  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8281, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8278, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x01  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8279, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8274, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x50  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8275, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x60  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8276, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x2B  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8277, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0A  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x04  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x80  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x02  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x80  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x03  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xC0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8263, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x37  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8264, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x20  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8261, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x37  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8262, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x20  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8265, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8273, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xE4  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8266, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x45  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8267, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xE0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8282, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8283, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0A  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8284, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8285, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x35  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8286, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8287, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xF7  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8288, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8289, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x01  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x39  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xE0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFD  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xBF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x01  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x94  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8290, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8291, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x50  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8292, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x09  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8293, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x90  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8294, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8295, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x32  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8296, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8297, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x64  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8298, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8299, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xEA  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xEA  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xB0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xC0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xCE  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A0, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A1, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x4F  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A2, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xEC  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A3, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x22  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A4, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A5, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x35  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A6, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A7, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xBE  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A8, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x60  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AA, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0C  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AB, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x10  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AC, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AD, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x98  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AE, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AF, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x05  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B0, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B1, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x01  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B2, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x05  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B3, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x2F  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B4, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B5, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xDF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B6, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B7, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x10  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B8, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xF4  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x826D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x38  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x826E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x03  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F00, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x03  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F01, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x10  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F03, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0F  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F04, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x06  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F05, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x80  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa422, 1 , 1 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa422, 7 , 4 , 0xf   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 90    , 21    , 7 , 0 , 0x6   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8261n_c_rtct_6auutp_conf[186] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa468, 1 , 0 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa422, 0 , 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc010, 9 , 9 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc010, 10, 10, 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc010, 14, 13, 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xc000, 0 , 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_DELAY_MS, 0    , 0     , 0     , 0 , 0 , 1000  , RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8260, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x35  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8270, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0A  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8271, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x1F  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8280, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x1D  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8281, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8278, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x01  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8279, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8274, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x50  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8275, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x60  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8276, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x2B  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8277, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0A  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x04  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x80  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x02  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x80  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x03  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x827B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xC0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8263, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x37  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8264, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x20  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8261, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x37  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8262, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x20  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8265, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8273, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xE4  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8266, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x45  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8267, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xE0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8282, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8283, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xDF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8284, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8285, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x95  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8286, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8287, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x40  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8288, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8289, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xCA  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x42  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x50  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFC  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x52  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x02  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x828F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x04  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8290, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8291, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x68  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8292, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0B  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8293, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x20  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8294, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8295, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x12  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8296, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8297, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x59  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8298, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8299, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xEA  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xE6  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xB0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x35  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x829F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xBE  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A0, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A1, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x59  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A2, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xEC  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A3, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A4, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A5, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x35  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A6, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A7, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xBE  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A8, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82A9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x60  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AA, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0C  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AB, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x10  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AC, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AD, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x98  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AE, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82AF, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x05  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B0, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B1, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x01  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B2, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x03  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B3, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xDC  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B4, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B5, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x68  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B6, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B7, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x46  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B8, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xFF  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x82B9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xF2  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x826D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x38  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x826E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x03  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F00, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x03  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F01, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x10  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F03, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0F  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F04, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x06  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8F05, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x80  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa422, 1 , 1 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa422, 7 , 4 , 0xf   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 90    , 21    , 7 , 0 , 0x6   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+};
+
diff --git a/sources/rtk-gp3000/src/hal/phy/construct/conf_rtl8264b.c b/sources/rtk-gp3000/src/hal/phy/construct/conf_rtl8264b.c
new file mode 100644
index 00000000..8f61054e
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/construct/conf_rtl8264b.c
@@ -0,0 +1,2331 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
+ */
+//Date: Tue Jan 31 11:51:10 2023
+
+rtk_hwpatch_t rtl8264b_top_conf[] = {
+    {RTK_PATCH_OP_TOP     , 0xf  , 2     , 20    , 15, 0 , 0x5   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 2     , 21    , 15, 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 2     , 22    , 15, 0 , 0x280 , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 2     , 23    , 15, 0 , 0x0014, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 3     , 16    , 15, 0 , 0x0300, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 3     , 17    , 15, 0 , 0x01ff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 3     , 18    , 15, 0 , 0x000c, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 3     , 19    , 15, 0 , 0x01ff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 3     , 20    , 15, 0 , 0x0200, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 3     , 21    , 15, 0 , 0x0015, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 3     , 22    , 15, 0 , 0x0200, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 3     , 23    , 15, 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 4     , 16    , 15, 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 13    , 23    , 8 , 5 , 0x6   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 90    , 18    , 15, 0 , 0xd   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 90    , 19    , 15, 0 , 0xd   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 90    , 20    , 15, 8 , 0x02  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8264b_sds_conf[] = {
+    {RTK_PATCH_OP_TOP     , 0xf  , 24    , 18    , 15, 0 , 0x881F, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 24    , 19    , 15, 0 , 0x003F, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 24    , 20    , 15, 0 , 0x003F, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 24    , 21    , 15, 0 , 0x003F, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 24    , 22    , 15, 0 , 0x001F, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x06  , 0x0D  , 15, 0 , 0x0F00, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x06  , 0x0E  , 15, 0 , 0x3F5A, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x07  , 0x10  , 15, 12, 0x8   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x07  , 0x10  , 7 , 0 , 0x3   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x06  , 0x1D  , 15, 0 , 0x0600, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x21  , 0x00  , 15, 0 , 0x4902, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x21  , 0x08  , 15, 0 , 0x0FC0, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x21  , 0x09  , 15, 0 , 0x33F0, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x21  , 0x0C  , 15, 0 , 0x08BF, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x21  , 0x12  , 15, 0 , 0x8000, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x36  , 0x07  , 15, 0 , 0x04C0, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x36  , 0x08  , 15, 0 , 0x2000, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2E  , 0x0B  , 15, 0 , 0x2390, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2E  , 0x0C  , 15, 0 , 0xAA17, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2E  , 0x0D  , 15, 0 , 0xFE40, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2E  , 0x0E  , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2E  , 0x11  , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2E  , 0x15  , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2E  , 0x16  , 15, 0 , 0x0041, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2F  , 0x00  , 15, 0 , 0x1F00, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2F  , 0x01  , 15, 0 , 0x2800, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2F  , 0x02  , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2F  , 0x11  , 15, 0 , 0x3000, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2F  , 0x13  , 15, 0 , 0xF400, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2F  , 0x1E  , 15, 0 , 0x0500, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x34  , 0x0B  , 15, 0 , 0x2390, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x34  , 0x0C  , 15, 0 , 0xA517, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x34  , 0x0D  , 15, 0 , 0xFE41, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x34  , 0x0E  , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x34  , 0x11  , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x34  , 0x15  , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x34  , 0x16  , 15, 0 , 0x0041, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x35  , 0x00  , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x35  , 0x01  , 15, 0 , 0x0800, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x35  , 0x02  , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x35  , 0x11  , 15, 0 , 0x3001, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x35  , 0x13  , 15, 0 , 0xF400, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x35  , 0x1E  , 15, 0 , 0x0100, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2C  , 0x0B  , 15, 0 , 0x2390, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2C  , 0x0C  , 15, 0 , 0xA517, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2C  , 0x0D  , 15, 0 , 0xFE41, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2C  , 0x0E  , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2C  , 0x11  , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2C  , 0x15  , 15, 0 , 0x7A61, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2C  , 0x16  , 15, 0 , 0x0041, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2D  , 0x00  , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2D  , 0x01  , 15, 0 , 0x0800, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2D  , 0x02  , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2D  , 0x11  , 15, 0 , 0x3001, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2D  , 0x13  , 15, 0 , 0xF400, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x2D  , 0x1E  , 15, 0 , 0x0100, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x28  , 0x0B  , 15, 0 , 0x2390, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x28  , 0x0C  , 15, 0 , 0xA514, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x28  , 0x0D  , 15, 0 , 0xFE43, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x28  , 0x0E  , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x28  , 0x11  , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x28  , 0x15  , 15, 0 , 0x7A61, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x28  , 0x16  , 15, 0 , 0x0041, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x29  , 0x00  , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x29  , 0x01  , 15, 0 , 0x0800, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x29  , 0x02  , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x29  , 0x11  , 15, 0 , 0x3001, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x29  , 0x13  , 15, 0 , 0xF400, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x29  , 0x1E  , 15, 0 , 0x0100, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x26  , 0x0B  , 15, 0 , 0x2390, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x26  , 0x0C  , 15, 0 , 0xA514, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x26  , 0x0D  , 15, 0 , 0xFE43, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x26  , 0x0E  , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x26  , 0x11  , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x26  , 0x15  , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x26  , 0x16  , 15, 0 , 0x0041, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x27  , 0x00  , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x27  , 0x01  , 15, 0 , 0x0800, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x27  , 0x02  , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x27  , 0x11  , 15, 0 , 0x3001, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x27  , 0x13  , 15, 0 , 0xF400, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x27  , 0x1E  , 15, 0 , 0x0100, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x24  , 0x0B  , 15, 0 , 0x2390, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x24  , 0x0C  , 15, 0 , 0xA514, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x24  , 0x0D  , 15, 0 , 0xFE43, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x24  , 0x0E  , 15, 0 , 0x12F4, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x24  , 0x11  , 15, 0 , 0xF2AD, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x24  , 0x15  , 15, 0 , 0x7A41, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x24  , 0x16  , 15, 0 , 0x0041, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x25  , 0x00  , 15, 0 , 0x1F80, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x25  , 0x01  , 15, 0 , 0x0800, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x25  , 0x02  , 15, 0 , 0x0FC8, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x25  , 0x11  , 15, 0 , 0x3001, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x25  , 0x13  , 15, 0 , 0xF400, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x25  , 0x1E  , 15, 0 , 0x0100, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 24    , 18    , 15, 0 , 0x880D, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 24    , 19    , 15, 0 , 0x0024, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 24    , 20    , 15, 0 , 0x0036, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 24    , 21    , 15, 0 , 0x0035, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 24    , 22    , 15, 0 , 0x001A, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x1F  , 0x00  , 15, 0 , 0x001B, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PSDS0   , 0xf  , 0x1F  , 0x00  , 15, 0 , 0x0000, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 90    , 20    , 7 , 0 , 0x04  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8264b_afe_conf[] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbf92, 15, 11, 0x1C  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbfaa, 10, 8 , 0x5   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbfae, 8 , 6 , 0x5   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbfaa, 12, 11, 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbf1c, 4 , 4 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbf0e, 5 , 4 , 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbf1c, 15, 13, 0x5   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbf16, 12, 12, 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbc24, 3 , 2 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbc24, 1 , 0 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbf08, 2 , 0 , 0x6   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbf0c, 5 , 3 , 0x7   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbf0c, 8 , 6 , 0x7   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbf0c, 11, 9 , 0x7   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbf0c, 14, 12, 0x7   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbf1a, 3 , 2 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_TOP     , 0xf  , 90    , 21    , 15, 8 , 0x04  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8264b_uc_conf[] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb820, 7 , 7 , 0x0   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbd8a, 5 , 3 , 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbd8c, 6 , 4 , 0x5   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8060, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 12, 10, 0x3   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8061, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 13, 0x5   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa466, 1 , 1 , 0x1   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8491, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x1D  , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8018, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 12, 12, 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x85af, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf85, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85af},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xc7af, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85b1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x85df, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85b3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85b5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1baf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85b7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8674, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85b9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85bb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7daf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85bd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x875b, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85bf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf87, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85c1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x67af, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85c3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8774, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85c5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf85, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85c7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xdc02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85c9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6957, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85cb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe48f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85cd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2ce5, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85cf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8f2d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85d1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe084, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85d3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x11e1, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85d5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8412, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85d7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf5d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85d9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x73f6, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85db},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xb01a, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85dd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe08f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85df},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2ce1, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85e1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8f2d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85e3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85e5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6802, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85e7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6938, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85e9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85eb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6b02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85ed},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6938, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85ef},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85f1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6e02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85f3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6938, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85f5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85f7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7102, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85f9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6938, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85fb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85fd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7402, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x85ff},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x70e5, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8601},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8603},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7702, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8605},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x70e5, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8607},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8609},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7a02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x860b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x70e5, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x860d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x860f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7d02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8611},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x70e5, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8613},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd784, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8615},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa2af, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8617},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5eed, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8619},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0286, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x861b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x21af, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x861d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x07ad, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x861f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf8f9, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8621},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfaef, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8623},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x69e0, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8625},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8018, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8627},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xad24, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8629},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x39d4, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x862b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x002e, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x862d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6e, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x862f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0402, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8631},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6938, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8633},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd480, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8635},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x03bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8637},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x866e, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8639},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0269, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x863b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x38d4, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x863d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x000f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x863f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8641},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7102, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8643},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6938, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8645},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8647},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7102, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8649},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x70dc, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x864b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd480, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x864d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0bbf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x864f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x866e, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8651},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0269, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8653},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x38d4, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8655},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x000f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8657},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8659},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7102, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x865b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6938, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x865d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf86, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x865f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7102, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8661},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x70dc, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8663},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0208, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8665},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1eef, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8667},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x96fe, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8669},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfdfc, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x866b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x04f0, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x866d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbd94, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x866f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x30bd, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8671},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9602, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8673},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8621, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8675},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0254, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8677},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xdcaf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8679},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x03c1, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x867b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0286, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x867d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2102, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x867f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8686, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8681},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf04, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8683},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x41f8, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8685},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfbef, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8687},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x79e0, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8689},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8018, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x868b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xac20, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x868d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x03af, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x868f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8756, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8691},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6b, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8693},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3402, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8695},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x70dc, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8697},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6b, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8699},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3102, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x869b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x70e5, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x869d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x869f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4902, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86a1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x70dc, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86a3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86a5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4c02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86a7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x70e5, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86a9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86ab},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4f02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86ad},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x70e5, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86af},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6b, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86b1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3702, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86b3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x70dc, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86b5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6c, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86b7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86b9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x70dc, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86bb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6b, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86bd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3402, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86bf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x70e5, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86c1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1f00, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86c3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe183, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86c5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd4bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86c7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6bcd, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86c9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0269, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86cb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x38bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86cd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6bd0, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86cf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0269, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86d1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x38bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86d3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6bd3, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86d5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0269, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86d7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x38bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86d9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6bd6, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86db},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0269, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86dd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x38bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86df},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6bd9, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86e1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86e3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe5bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86e5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6bdc, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86e7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86e9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe5bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86eb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6bdf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86ed},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86ef},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe5bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86f1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6be2, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86f3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86f5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe5bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86f7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6f46, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86f9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86fb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xdce1, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86fd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x83d3, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x86ff},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8701},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3a02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8703},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6938, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8705},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d14, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8707},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8709},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4002, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x870b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6938, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x870d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d12, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x870f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8711},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3d02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8713},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6938, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8715},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8717},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4302, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8719},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x70dc, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x871b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0238, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x871d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xb5bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x871f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6bd9, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8721},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8723},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xdcbf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8725},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6bdc, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8727},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8729},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xdcbf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x872b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6bdf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x872d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x872f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xdcbf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8731},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6be2, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8733},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8735},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xdcbf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8737},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6b34, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8739},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x873b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xdcbf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x873d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6b37, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x873f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8741},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe5bf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8743},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6f4f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8745},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8747},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xdcbf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8749},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6b31, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x874b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x874d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xdcbf, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x874f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6f4c, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8751},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0270, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8753},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xdcef, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8755},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x97ff, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8757},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8759},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xac2f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x875b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x03af, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x875d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b2a, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x875f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x020e, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8761},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x95af, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8763},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b3f, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8765},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xee84, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8767},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3c00, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8769},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6c, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x876b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c02, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x876d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x70e5, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x876f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf01, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8771},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0300, RTK_PATCH_CMP_SWC , 0, 0xa438, 0xa436, 0x8773},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb818, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5d6d, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb81a, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5eea, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb81c, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x07aa, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb81e, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x03be, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb850, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x043e, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb852, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b26, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb878, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00fd, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb884, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb832, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x007f, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8264b_uc2_conf[] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb820, 7 , 7 , 0x1   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb87c, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8acf, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb87e, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf8a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8acf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe7af, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ad1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8b40, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ad3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf8b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ad5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4caf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ad7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8b6a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ad9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf8b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8adb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xb5af, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8add},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8bd1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8adf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf8c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ae1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x04af, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ae3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8c12, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ae5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf67, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ae7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6302, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ae9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x65f5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8aeb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef31, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8aed},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf67, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8aef},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6002, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8af1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x65f5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8af3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1e31, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8af5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xac38, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8af7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x19bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8af9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x676c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8afb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8afd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf5ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8aff},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x31bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b01},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6769, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b03},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b05},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf51e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b07},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x31ac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b09},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x380c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b0b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xee89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b0d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2c02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b0f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xae0a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b11},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xee89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b13},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2c00, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b15},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xae04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b17},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xee89, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b19},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2c01, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b1b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf8f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b1d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd5e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b1f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x892c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b21},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1a91, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b23},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xdbbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b25},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x67cf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b27},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b29},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf51f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b2b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x001f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b2d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x221b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b2f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x45ad, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b31},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2705, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b33},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe187, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b35},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x06ae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b37},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x03e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b39},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8707, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b3b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf2d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b3d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1a02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b3f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8c1e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b41},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x028c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b43},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7b02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b45},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x224f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b47},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf40, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b49},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xb8ac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b4b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2f0f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b4d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0210, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b4f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x62bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b51},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6d36, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b53},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b55},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf5e5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b57},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8fde, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b59},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf10, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b5b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4ae1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b5d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8fde, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b5f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b61},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3602, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b63},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x65d6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b65},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf10, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b67},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x59e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b69},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8fdd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b6b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa100, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b6d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0dbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b6f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6d36, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b71},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b73},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf5e5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b75},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8fdc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b77},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xee8f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b79},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xdd01, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b7b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b7d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3602, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b7f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6f77, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b81},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf86, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b83},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xc7e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b85},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x892c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b87},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4903, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b89},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1a91, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b8b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef69, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b8d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xdbbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b8f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x67cf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b91},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b93},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf51f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b95},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x001f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b97},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x22ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b99},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x741b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b9b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x45ad, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b9d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2711, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8b9f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf86, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd0d0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8fdc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ba9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3602, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bab},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x65d6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bad},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf35, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8baf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x46af, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3527, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x026f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6eee, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8fdd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bb9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bbb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8d31, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bbd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x026f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bbf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6ebf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8d40, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x026f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6ebf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8d46, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bc9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x026f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bcb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6eaf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bcd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x36a9, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bcf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf8ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x49f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xc202, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x65f5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bd9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xad28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bdb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bdd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8a4e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bdf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xad28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0502, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5d65, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xae0e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x025c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8be9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1202, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8beb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8cc5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bed},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xae06, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bef},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x025b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf302, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8d0d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe087, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x17f6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bf9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x27e4, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bfb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8717, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bfd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfcef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8bff},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x94fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c01},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x04a1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c03},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0103, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c05},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x028c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c07},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe9e0, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c09},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8a02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c0b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef23, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c0d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf5c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c0f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xdeac, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c11},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5003, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c13},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf61, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c15},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c17},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8d0d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c19},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaf61, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c1b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c1d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfafb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c1f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef79, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c21},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfbbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c23},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6766, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c25},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c27},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf5ad, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c29},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2810, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c2b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xad30, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c2d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x05d7, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c2f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0002, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c31},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xae16, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c33},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xad32, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c35},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x24d7, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c37},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0003, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c39},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xae0e, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c3b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xad31, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c3d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x05d7, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c3f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c41},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xae06, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c43},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xad33, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c45},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x14d7, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c47},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0001, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c49},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf8f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c4b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xdf4f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c4d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0008, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c4f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1a97, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c51},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd78c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c53},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x63d6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c55},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8c7b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c57},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c59},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3bff, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c5b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef97, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c5d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfffe, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c5f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c61},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x206b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c63},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0e20, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c65},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6b11, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c67},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x206b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c69},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1420, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c6b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6b17, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c6d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x206b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c6f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2020, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c71},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6b23, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c73},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x206b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c75},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2600, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c77},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6b29, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c79},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf8fa, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c7b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef69, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c7d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c7f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbd02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c81},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x65f5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c83},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xad28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c85},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0ebf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c87},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8d34, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c89},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x026f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c8b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x77bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c8d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8d31, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c8f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x026f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c91},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x77ae, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c93},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2ad1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c95},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0fbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c97},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8d37, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c99},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c9b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd6bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c9d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8d3a, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8c9f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x026f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6ed1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8d3d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ca9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd6bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cab},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8d40, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cad},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x026f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8caf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x77d1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8d43, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd6bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cb9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8d46, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cbb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x026f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cbd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x77ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cbf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x96fe, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf8ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x49f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cc9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbd02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ccb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x65f5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ccd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xac28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ccf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x12bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6be6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf5e5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8fd8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cd9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cdb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf202, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cdd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x65f5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cdf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe58f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd9fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef94, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf8ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ce9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x49f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ceb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8ced},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbd02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cef},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x65f5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xac28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x12e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8fda, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cf9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe602, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cfb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x65d6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cfd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe18f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8cff},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xdbbf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d01},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6bf2, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d03},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d05},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd6fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d07},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef94, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d09},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d0b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf8ef, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d0d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x49f8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d0f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6d, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d11},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbd02, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d13},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x65f5, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d15},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xac28, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d17},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x12e1, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d19},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8fd8, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d1b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf6b, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d1d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe602, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d1f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x65d6, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d21},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xe18f, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d23},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd9bf, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d25},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6bf2, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d27},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0265, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d29},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd6fc, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d2b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xef94, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d2d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfc04, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d2f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x77bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d31},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6c66, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d33},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbd6c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d35},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x30bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d37},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5444, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d39},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbd54, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d3b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x85bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d3d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5e55, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d3f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbd54, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d41},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa7bd, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d43},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5cbb, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d45},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbd5c, RTK_PATCH_CMP_SWC , 0, 0xb87e, 0xb87c, 0x8d47},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb85e, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2d07, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb860, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x40b5, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb862, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1047, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb864, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3504, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb886, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x36A6, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb888, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x613d, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb88a, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5cd9, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb88c, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x610a, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xb838, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00ff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb820, 7 , 7 , 0x0   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8264b_nctl0_conf[] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb820, 7 , 7 , 0x1   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8015, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8020, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x802a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8030, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8035, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8046, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x806b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd707, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x606f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x801a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd707, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x606f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x801a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce10, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcf01, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd705, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcf02, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd719, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3bb7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8024, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd704, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x406e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x12bd, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x12e3, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xab80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd500, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xc402, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x004a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8b80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd500, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x090f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x37},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0a03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x38},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x39},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1c1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x401c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce00, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd500, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x801a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x40},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd501, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x41},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce01, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x42},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x43},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x44},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0aa9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x45},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd500, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x46},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x47},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2a69, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x48},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8056, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x49},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3f48, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8058, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3f4b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x805a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x618c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3f40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x805c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x50},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3f43, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x51},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x805e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x52},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x616b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x53},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6187, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x54},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x55},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcc8f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x56},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x57},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcc8d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x58},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x59},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcc8b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcc89, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcc87, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcc91, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x60},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x61},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b9a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x62},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x63},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xca80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x64},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x65},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0ba0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x66},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xca00, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x67},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd504, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x68},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x69},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1658, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa208, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0a88, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d91, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA026, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d90, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA024, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1657, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA022, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0aa1, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA020, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0047, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA006, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0049, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA004, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x12b9, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA002, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0be5, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA000, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1811, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA008, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xff00, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0ff8, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xc483, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x0ff8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xc483, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xff9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xffa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xffb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xffc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xffd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xffe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfff},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA152, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1a83, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA154, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1d29, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA156, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA158, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA15A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA15C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA15E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA160, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA150, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0003, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb820, 7 , 7 , 0x0   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8264b_nctl1_conf[] = {
+};
+
+rtk_hwpatch_t rtl8264b_nctl2_conf[] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb820, 7 , 7 , 0x1   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0020, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8022, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x809f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x80fb, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x810f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8116, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x831d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8370, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd707, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x416f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd05a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa501, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd701, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5fbd, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8501, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0427, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x040b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa610, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcd16, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa501, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd701, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5fbd, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8501, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd707, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x406f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x803d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5fbe, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8380, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x37},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x38},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd403, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x39},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13c5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1433, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x40},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x41},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13ec, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x42},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x43},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x44},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x143c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x45},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x46},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa8c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x47},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa2fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x48},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x49},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0ca0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x14a5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcd17, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x4f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd057, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x50},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x51},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd066, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x52},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x53},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd076, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x54},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x55},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x56},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x57},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x607c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x58},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x613d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x59},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfffb, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5fbd, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x5f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa607, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x60},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf007, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x61},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa607, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x62},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x63},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x64},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x65},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5fbc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x66},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x67},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x68},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x69},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5fbb, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8840, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cf8, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x6f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d48, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x70},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x71},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x72},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd055, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x73},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x74},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x75},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x76},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5fbb, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x77},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x78},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x61e7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x79},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f3a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x88c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x82fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8350, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x7f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x84a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x80},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8607, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x81},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x82},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x83},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8df8, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x84},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8370, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x85},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x86},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xff9b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x87},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8510, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x88},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa508, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x89},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8508, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcd18, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x8f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xb920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x90},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x91},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x92},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x93},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x94},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x95},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9a20, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x96},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x97},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x98},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x99},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6065, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f94, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffe0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0233, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd705, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x9f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3fa7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x80a6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd75f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x699c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd704, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4066, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xa9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xaa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd705, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xab},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x61b4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xac},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd704, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xad},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x609f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xae},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6150, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xaf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2d71, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x80b9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cf0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x05a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13b1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xb9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xba},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8220, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c30, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0410, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xbf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x81a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8302, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8684, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8203, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xaa10, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xc9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8b07, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xca},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xce},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xcf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce0b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce0b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xd9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce09, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xda},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce09, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xde},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa204, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xdf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13e4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xab08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcda0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd705, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x40de, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd162, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd045, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbf10, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xe9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xea},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13b1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xeb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9f10, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xec},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xed},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13b1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xee},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xef},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x607a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13b1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9f10, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8210, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa210, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xf9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x2969, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x810b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xfe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0xff},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x100},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8105, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x101},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd18a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x102},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x103},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf009, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x104},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x105},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x106},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x107},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1c6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x108},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x109},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x04eb, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x10f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x110},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8df8, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x111},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8370, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x112},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x113},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x114},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x009e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x115},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x116},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x117},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8121, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x118},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x119},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x811e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1bf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd06d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1dd, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd06d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x11f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x120},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x121},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd06e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x122},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x123},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x124},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x125},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x126},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x127},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd05a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x128},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x129},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x12f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x130},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x131},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x132},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x133},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x134},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x135},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x136},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x137},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x138},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x139},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13e4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0ccf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x13f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x140},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x141},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c24, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x142},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x143},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x144},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x145},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1433, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x146},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x147},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x148},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13ec, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x149},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x143c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa8c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x14f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x150},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x151},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x152},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cfc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x153},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0224, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x154},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0ca0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x155},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x156},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x157},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x158},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x159},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd162, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x15f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x160},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8840, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x161},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x162},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd045, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x163},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x164},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x165},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x166},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x167},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x168},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6127, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x169},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f3b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x88c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8350, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x16f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x84a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x170},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffb6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x171},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xb920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x172},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcd33, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x173},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x174},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x175},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x176},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x177},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x178},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x179},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6065, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f94, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffee, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xb820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x17f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x180},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x181},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x182},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7fa5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x183},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x184},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x185},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x186},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x187},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1433, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x188},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x189},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13ec, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x143c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa2fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x18f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x190},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8880, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x191},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x192},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0440, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x193},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcd34, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x194},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x195},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x196},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x197},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x198},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xac3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x199},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x19f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa604, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x81a8, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd19f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1a9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1aa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ab},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ac},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x63f4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ad},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ae},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1af},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4368, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8d38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1b9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ba},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x81c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x81c1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1f4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1be},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1bf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1c6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6074, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1c9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ca},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ce},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4056, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1cf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x61fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xfff9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4070, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1d9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8291, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1da},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1db},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1dc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xae80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1dd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1de},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1df},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8291, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd05a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1e9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ea},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1eb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ec},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ed},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ee},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ef},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13e4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0ccf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1f9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c24, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa340, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ff},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1433, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x200},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x201},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x202},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13ec, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x203},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8110, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x204},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x205},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x143c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x206},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x207},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa8c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x208},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x209},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cfc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0224, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0ca0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x20f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x210},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8604, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x211},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcd35, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x212},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd162, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x213},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x214},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x215},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x216},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x217},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x218},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8840, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x219},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1c4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd045, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5fba, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x21f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x220},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6127, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x221},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x222},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f3b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x223},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x88c0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x224},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x225},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x226},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8350, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x227},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x84a0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x228},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffb8, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x229},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xbb80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xb920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x22f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcd36, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x230},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x231},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x232},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x233},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7fb4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x234},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9920, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x235},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9b80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x236},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x237},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x238},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x239},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6065, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f94, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xffe8, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xb820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x23f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd71f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x240},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x7fa5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x241},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9820, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x242},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x800a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x243},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x244},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x245},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1433, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x246},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x247},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x248},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13ec, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x249},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8108, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x143c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa2fc, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa304, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8880, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x24f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x250},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0440, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x251},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcd37, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x252},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x253},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x254},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x255},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b80, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x256},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xac3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x257},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x258},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x259},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa810, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa480, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa604, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x25f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x260},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x261},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x826b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x262},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x263},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8268, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x264},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x265},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x266},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x267},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x268},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x269},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x26f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x141a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x270},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x271},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x272},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x273},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x274},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x275},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x276},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x277},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b40, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x278},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x279},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8d38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8287, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x27f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8284, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x280},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x281},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x282},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x283},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x284},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x285},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x286},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd189, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x287},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x288},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x289},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x141a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x28f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x290},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x291},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x292},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x293},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b05, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x294},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x295},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x296},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x297},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x298},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x299},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x29f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce08, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13e4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2a9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa180, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2aa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcd38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ab},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ac},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ad},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x82c1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ae},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2af},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x82b9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf013, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2b9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ba},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1b7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2be},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2bf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd13b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd055, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2c9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ca},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x141a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ce},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f7b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2cf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa302, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x141a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2d9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2da},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2db},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c12, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2dc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2dd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2de},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2df},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x82f3, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x82eb, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf013, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2e9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ea},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2eb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ec},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ed},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ee},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ef},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd040, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd16b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2f9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x141a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2fe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x2ff},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x300},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f2a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x301},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x302},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x085e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x303},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x304},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x305},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcb0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x306},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0cc7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x307},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x308},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x309},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4127, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b05, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x30f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x310},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d28, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x311},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x312},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x313},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x314},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x315},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x316},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x317},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c38, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x318},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0d18, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x319},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0f45, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x646d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x31f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8337, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x320},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x321},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x832d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x322},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x323},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x324},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x325},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x326},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x327},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x328},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf01a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x329},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf017, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x32f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x330},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd100, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x331},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x332},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf010, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x333},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x334},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x335},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x336},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x337},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x40c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x338},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x339},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x33f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x340},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x341},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x342},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x343},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x344},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x345},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x141a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x346},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x347},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x348},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x349},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f29, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x60cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x60f1, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6113, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6135, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x34f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x6157, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x350},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x351},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x352},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x353},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x354},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf008, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x355},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x356},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x357},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x358},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf004, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x359},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf002, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xce06, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13e4, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x35f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x360},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8bc0, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x361},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c3f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x362},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c09, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x363},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x364},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa120, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x365},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa310, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x366},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xa420, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x367},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcd3b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x368},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x369},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x65ad, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x43c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8381, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x36f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8379, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x370},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x371},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x372},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x373},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x374},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf024, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x375},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd15d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x376},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x377},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf021, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x378},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x379},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x37a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1c6, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x37b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x37c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf01c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x37d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd15d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x37e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x37f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf019, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x380},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x381},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x382},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd199, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x383},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x384},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf014, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x385},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x386},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x387},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf011, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x388},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x389},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x38a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8394, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x38b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x38c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x8391, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x38d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd1e5, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x38e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x38f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf009, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x390},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd191, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x391},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x392},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x393},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x394},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x395},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x396},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd16b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x397},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x398},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x399},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x13cf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x39a},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x39b},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x141a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x39c},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x39d},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f7a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x39e},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd706, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x39f},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x5f2c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x40e7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b05, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c03, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3a9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1502, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3aa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0c0f, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3ab},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b0a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3ac},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x9503, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3ad},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xcd3c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3ae},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3af},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x644d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x43c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd700, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x37c9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x83c7, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x33a9, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x83bf, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3b9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3ba},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf019, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3bb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3bc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3bd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf016, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3be},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3bf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf011, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd13e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf00e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c6},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd702, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c7},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x4098, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3c9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3ca},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf009, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3cb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3cc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd049, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3cd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf006, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3ce},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3cf},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd04b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3d0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf003, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3d1},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd17a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3d2},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd048, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3d3},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1800, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3d4},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x093a, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x3d5},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA10E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0883, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA10C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0f32, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA10A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0676, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA108, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00fa, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA106, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x04d9, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA104, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x12fe, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA102, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x01c1, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA100, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x047f, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA110, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00ff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA016, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0020, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA012, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x1ff8, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA014, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd13e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ff8},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd15c, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ff9},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd16b, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffa},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xd15d, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffb},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b0e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffc},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b0e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffd},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b0e, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1ffe},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_SWC , 0, 0xa014, 0xa012, 0x1fff},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA164, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0972, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA166, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0968, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA168, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0a0b, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA16A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0a01, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA16C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0b8a, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA16E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0bf9, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA170, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x125c, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA172, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x3fff, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0xA162, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x007F, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb820, 7 , 7 , 0x0   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8264b_algxg_conf[] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x80CD, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x25  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8065, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x15  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8175, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xa2  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8176, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xc5  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8077, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x40  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8078, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xcc  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8969, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x0f  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8957, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x2C  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8959, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x15  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x895A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x3E  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x895F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x1E  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8165, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x22  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x827E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x68  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8167, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x33  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8013, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x39  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8fd7, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x14  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8fd5, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x1e  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x82D9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x20  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x82DA, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x00  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x816E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xab  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8159, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x58  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x815A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x99  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8139, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x25  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8125, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x67  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8126, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x89  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x827D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x4c  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8205, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x4d  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8FD6, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x78  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8159, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x58  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x815A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x99  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x815B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x77  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x815C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xfb  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8125, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x67  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8126, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x89  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8127, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x77  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8128, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0xf7  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x80DF, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x51  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x80E0, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x94  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8264b_alg_giga_conf[] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x80b8, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x4d  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x80b9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xcc  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x80ba, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x80bb, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 13, 8 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x80bc, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x37  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x80bd, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 12, 8 , 0x0c  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x80be, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xBB  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x80bf, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xca  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x80c0, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x45  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x80c2, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x3b  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x80cc, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x16  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x80cd, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 10, 8 , 0x4   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x80ce, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x80cf, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 13, 8 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x80d0, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x53  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x80d1, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 12, 8 , 0x0a  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x80d2, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xB9  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x80d3, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xd0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x80d4, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x4a  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x80d6, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x35  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x80a4, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x0d  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x80a5, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xa4  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x80a6, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x59  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x80a7, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 13, 8 , 0x05  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x80a8, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xab  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x80a9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 12, 8 , 0x0b  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x80aa, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xef  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x80ab, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xae  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x80ac, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0xdf  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x80ae, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x28  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa836, 15, 15, 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa85c, 7 , 7 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa85c, 6 , 3 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8367, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x5d  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8264b_normal_conf[] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbd92, 15, 0 , 0x002e, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbd94, 15, 0 , 0x8003, RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbd96, 3 , 0 , 0xf   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbd96, 3 , 0 , 0x0   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbd94, 15, 0 , 0x800b, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbd96, 3 , 0 , 0xf   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xbd96, 3 , 0 , 0x0   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x817D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x07  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8426, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x46  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8428, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x46  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x84de, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x84e0, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00fc, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x84e2, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf61a, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x84e4, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x58  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x84e6, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x84e8, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00fc, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x84ea, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf61a, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x84ec, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x58  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x84ee, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0000, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x84f0, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x00fc, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x84f2, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0xf61a, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x84f4, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 8 , 0x58  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xae32, 5 , 5 , 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x8018, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 12, 12, 0x1   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8fdf, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 0 , 0x0496, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8fe1, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 0 , 0x03a5, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8fe3, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 0 , 0x02e5, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8fe5, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 0 , 0x020d, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8fe7, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 0 , 0x0496, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8fe9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 0 , 0x03a5, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8feb, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 0 , 0x02e5, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8fed, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 0 , 0x020d, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8fef, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 0 , 0x0496, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8ff1, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 0 , 0x03a5, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8ff3, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 0 , 0x02e5, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8ff5, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 0 , 0x020d, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8ff7, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 0 , 0x0496, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8ff9, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 0 , 0x03a5, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8ffb, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 0 , 0x02e5, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8ffd, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 0 , 0x020d, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb516, 6 , 0 , 0x0   , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8fda, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x04  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8fdb, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x05  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8132, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x77  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8134, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x88  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x80ca, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x77  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x80cc, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x88  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8062, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x77  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87c, 15, 0 , 0x8064, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb87e, 15, 8 , 0x88  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa436, 15, 0 , 0x801E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xa438, 15, 0 , 0x0013, RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8264b_dataram_conf[] = {
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb820, 7 , 7 , 0x0   , RTK_PATCH_CMP_WS  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb896, 0 , 0 , 0x0   , RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb892, 15, 8 , 0x0   , RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC037, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x33  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC038, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x2A  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC039, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x25  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC03A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x20  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC03B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x1C  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC03C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x17  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC03D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x13  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC075, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xA1  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC076, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xB1  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC077, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x2E  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC078, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x55  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC079, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x19  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC07A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xDC  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC07B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xA0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC10B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xD5  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC10C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xD5  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC10D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xD5  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC10E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xD5  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC10F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xD5  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC110, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xD5  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC149, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x08  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC14A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x08  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC14B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x08  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC14C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x08  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC14D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x08  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC14E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x08  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC166, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xEE  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC167, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xEE  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC168, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x07  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC169, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x09  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC16A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x0B  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC16B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x0D  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC16C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x13  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC16D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x0E  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC16E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x11  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC16F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x14  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC170, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x17  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC171, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x15  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC172, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0x10  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC173, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0x0B  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC128, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xF7  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC129, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xF7  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC12A, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xF8  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC12B, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xF7  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC12C, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xF6  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC12D, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xF5  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC12E, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xF2  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC12F, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xF7  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC130, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xF5  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC131, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xF2  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC132, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xF0  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC133, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xF1  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC134, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 15, 8 , 0xF4  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb88e, 15, 0 , 0xC135, RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb890, 7 , 0 , 0xF7  , RTK_PATCH_CMP_WC  , 0, 0, 0, 0},
+    {RTK_PATCH_OP_PHYOCP  , 0xf  , 0     , 0xb896, 0 , 0 , 0x1   , RTK_PATCH_CMP_W   , 0, 0, 0, 0},
+};
+
+rtk_hwpatch_t rtl8264b_rtct_conf[] = {
+};
+
diff --git a/sources/rtk-gp3000/src/hal/phy/error.h b/sources/rtk-gp3000/src/hal/phy/error.h
new file mode 100644
index 00000000..d99a996f
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/error.h
@@ -0,0 +1,165 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
+ */
+
+#ifndef __COMMON_ERROR_H__
+#define __COMMON_ERROR_H__
+
+/*
+ * Include Files
+ */
+#if defined(RTK_PHYDRV_IN_LINUX)
+  #include "type.h"
+#else
+  #include <common/type.h>
+#endif
+/*
+ * Data Type Declaration
+ */
+typedef enum rt_error_common_e
+{
+    RT_ERR_FAILED = -1,                             /* General Error                                                                    */
+
+    /* 0x0000xxxx for common error code */
+    RT_ERR_OK = 0,                                  /* 0x00000000, OK                                                                   */
+    RT_ERR_INPUT = 0xF001,                          /* 0x0000F001, invalid input parameter                                              */
+    RT_ERR_UNIT_ID,                                 /* 0x0000F002, invalid unit id                                                      */
+    RT_ERR_PORT_ID,                                 /* 0x0000F003, invalid port id                                                      */
+    RT_ERR_PORT_MASK,                               /* 0x0000F004, invalid port mask                                                    */
+    RT_ERR_PORT_LINKDOWN,                           /* 0x0000F005, link down port status                                                */
+    RT_ERR_ENTRY_INDEX,                             /* 0x0000F006, invalid entry index                                                  */
+    RT_ERR_NULL_POINTER,                            /* 0x0000F007, input parameter is null pointer                                      */
+    RT_ERR_QUEUE_ID,                                /* 0x0000F008, invalid queue id                                                     */
+    RT_ERR_QUEUE_NUM,                               /* 0x0000F009, invalid queue number                                                 */
+    RT_ERR_BUSYWAIT_TIMEOUT,                        /* 0x0000F00a, busy watting time out                                                */
+    RT_ERR_MAC,                                     /* 0x0000F00b, invalid mac address                                                  */
+    RT_ERR_OUT_OF_RANGE,                            /* 0x0000F00c, input parameter out of range                                         */
+    RT_ERR_CHIP_NOT_SUPPORTED,                      /* 0x0000F00d, functions not supported by this chip model                           */
+    RT_ERR_SMI,                                     /* 0x0000F00e, SMI error                                                            */
+    RT_ERR_NOT_INIT,                                /* 0x0000F00f, The module is not initial                                            */
+    RT_ERR_CHIP_NOT_FOUND,                          /* 0x0000F010, The chip can not found                                               */
+    RT_ERR_NOT_ALLOWED,                             /* 0x0000F011, actions not allowed by the function                                  */
+    RT_ERR_DRIVER_NOT_FOUND,                        /* 0x0000F012, The driver can not found                                             */
+    RT_ERR_SEM_LOCK_FAILED,                         /* 0x0000F013, Failed to lock semaphore                                             */
+    RT_ERR_SEM_UNLOCK_FAILED,                       /* 0x0000F014, Failed to unlock semaphore                                           */
+    RT_ERR_THREAD_EXIST,                            /* 0x0000F015, Thread exist                                                         */
+    RT_ERR_THREAD_CREATE_FAILED,                    /* 0x0000F016, Thread create fail                                                   */
+    RT_ERR_FWD_ACTION,                              /* 0x0000F017, Invalid forwarding Action                                            */
+    RT_ERR_IPV4_ADDRESS,                            /* 0x0000F018, Invalid IPv4 address                                                 */
+    RT_ERR_IPV6_ADDRESS,                            /* 0x0000F019, Invalid IPv6 address                                                 */
+    RT_ERR_PRIORITY,                                /* 0x0000F01a, Invalid Priority value                                               */
+    RT_ERR_FID,                                     /* 0x0000F01b, invalid fid                                                          */
+    RT_ERR_ENTRY_NOTFOUND,                          /* 0x0000F01c, specified entry not found                                            */
+    RT_ERR_DROP_PRECEDENCE,                         /* 0x0000F01d, invalid drop precedence                                              */
+    RT_ERR_NOT_FINISH,                              /* 0x0000F01e, Action not finish, still need to wait                                */
+    RT_ERR_TIMEOUT,                                 /* 0x0000F01f, Time out                                                             */
+    RT_ERR_REG_ARRAY_INDEX_1,                       /* 0x0000F020, invalid index 1 of register array                                    */
+    RT_ERR_REG_ARRAY_INDEX_2,                       /* 0x0000F021, invalid index 2 of register array                                    */
+    RT_ERR_ETHER_TYPE,                              /* 0x0000F022, invalid ether type                                                   */
+    RT_ERR_MBUF_PKT_NOT_AVAILABLE,                  /* 0x0000F023, mbuf->packet is not available                                        */
+    RT_ERR_QOS_INVLD_RSN,                           /* 0x0000F024, invalid pkt to CPU reason                                            */
+    RT_ERR_CB_FUNCTION_EXIST,                       /* 0x0000F025, Callback function exist                                              */
+    RT_ERR_CB_FUNCTION_FULL,                        /* 0x0000F026, Callback function number is full                                     */
+    RT_ERR_CB_FUNCTION_NOT_FOUND,                   /* 0x0000F027, Callback function can not found                                      */
+    RT_ERR_TBL_FULL,                                /* 0x0000F028, The table is full                                                    */
+    RT_ERR_TRUNK_ID,                                /* 0x0000F029, invalid trunk id                                                     */
+    RT_ERR_TYPE,                                    /* 0x0000F02a, invalid type                                                         */
+    RT_ERR_ENTRY_EXIST,                             /* 0x0000F02b, entry exists                                                         */
+    RT_ERR_CHIP_UNDEFINED_VALUE,                    /* 0x0000F02c, chip returned an undefined value                                     */
+    RT_ERR_EXCEEDS_CAPACITY,                        /* 0x0000F02d, exceeds the capacity of hardware                                     */
+    RT_ERR_ENTRY_REFERRED,                          /* 0x0000F02e, entry is still being referred                                        */
+    RT_ERR_OPER_DENIED,                             /* 0x0000F02f, operation denied                                                     */
+    RT_ERR_PORT_NOT_SUPPORTED,                      /* 0x0000F030, functions not supported by this port                                 */
+    RT_ERR_SOCKET,                                  /* 0x0000F031, socket error                                                         */
+    RT_ERR_MEM_ALLOC,                               /* 0x0000F032, insufficient memory resource                                         */
+    RT_ERR_ABORT,                                   /* 0x0000F033, operation aborted                                                    */
+    RT_ERR_DEV_ID,                                  /* 0x0000F034, invalid device id                                                    */
+    RT_ERR_DRIVER_NOT_SUPPORTED,                    /* 0x0000F035, functions not supported by this driver                               */
+    RT_ERR_NOT_SUPPORTED,                           /* 0x0000F036, functions not supported                                              */
+    RT_ERR_SER,                                     /* 0x0000F037, ECC or parity error                                                  */
+    RT_ERR_MEM_NOT_ALIGN,                           /* 0x0000F038, memory address is not aligned                                        */
+    RT_ERR_SEM_FAKELOCK_OK,                         /* 0x0000F039, attach thread lock a semaphore which was already locked              */
+    RT_ERR_CHECK_FAILED,                            /* 0x0000F03a, check result is failed                                               */
+
+    RT_ERR_COMMON_END = 0xFFFF                      /* The symbol is the latest symbol of common error                                  */
+} rt_error_common_t;
+
+/*
+ * Macro Definition
+ */
+#define RT_PARAM_CHK(expr, errCode)\
+do {\
+    if ((int32)(expr)) {\
+        return errCode; \
+    }\
+} while (0)
+
+#define RT_PARAM_CHK_EHDL(expr, errCode, err_hdl)\
+do {\
+    if ((int32)(expr)) {\
+        {err_hdl}\
+        return errCode; \
+    }\
+} while (0)
+
+#define RT_INIT_CHK(state)\
+do {\
+    if (INIT_COMPLETED != (state)) {\
+        return RT_ERR_NOT_INIT;\
+    }\
+} while (0)
+
+#define RT_INIT_REENTRY_CHK(state)\
+do {\
+    if (INIT_COMPLETED == (state)) {\
+        osal_printf(" %s had already been initialized!\n", __FUNCTION__);\
+        return RT_ERR_OK;\
+    }\
+} while (0)
+
+#define RT_INIT_REENTRY_CHK_NO_WARNING(state)\
+    do {\
+        if (INIT_COMPLETED == (state)) {\
+            return RT_ERR_OK;\
+        }\
+    } while (0)
+
+#define RT_ERR_CHK(op, ret)\
+do {\
+    if ((ret = (op)) != RT_ERR_OK)\
+        return ret;\
+} while(0)
+
+#define RT_ERR_HDL(op, errHandle, ret)\
+do {\
+    if ((ret = (op)) != RT_ERR_OK)\
+        goto errHandle;\
+} while(0)
+
+#define RT_ERR_CHK_EHDL(op, ret, err_hdl)\
+do {\
+    if ((ret = (op)) != RT_ERR_OK)\
+    {\
+        {err_hdl}\
+        return ret;\
+    }\
+} while(0)
+
+#define RT_NULL_HDL(pointer, err_label)\
+do {\
+    if (NULL == (pointer)) {\
+        goto err_label;\
+    }\
+} while (0)
+
+#define RT_ERR_VOID_CHK(op, ret)\
+do {\
+    if ((ret = (op)) != RT_ERR_OK) {\
+        osal_printf("Fail in %s %d, ret %x!\n", __FUNCTION__, __LINE__, ret);\
+        return ;}\
+} while(0)
+
+#endif /* __COMMON_ERROR_H__ */
+
diff --git a/sources/rtk-gp3000/src/hal/phy/phy_patch.c b/sources/rtk-gp3000/src/hal/phy/phy_patch.c
new file mode 100644
index 00000000..f9af3ffe
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/phy_patch.c
@@ -0,0 +1,179 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
+ */
+
+/*
+ * Include Files
+ */
+#if defined(RTK_PHYDRV_IN_LINUX)
+  #include "rtk_osal.h"
+#else
+  #include <common/rt_type.h>
+  #include <common/rt_error.h>
+  #include <common/debug/rt_log.h>
+  #include <hal/common/halctrl.h>
+  #include <hal/phy/phy_patch.h>
+#endif
+
+/*
+ * Function Declaration
+ */
+uint8 phy_patch_op_translate(uint8 patch_mode, uint8 patch_op, uint8 compare_op)
+{
+    if (patch_mode != PHY_PATCH_MODE_CMP)
+    {
+        return patch_op;
+    }
+    else
+    {
+        switch (compare_op)
+        {
+            case RTK_PATCH_CMP_WS:
+                return RTK_PATCH_OP_SKIP;
+            case RTK_PATCH_CMP_W:
+            case RTK_PATCH_CMP_WC:
+            case RTK_PATCH_CMP_SWC:
+            default:
+                return RTK_PATCH_OP_TO_CMP(patch_op, compare_op);
+        }
+    }
+}
+
+int32 phy_patch_op(rt_phy_patch_db_t *pPhy_patchDb, uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_op, uint16 portmask, uint16 pagemmd, uint16 addr, uint8 msb, uint8 lsb, uint16 data, uint8 patch_mode)
+{
+    rtk_hwpatch_t op;
+
+    op.patch_op = patch_op;
+    op.portmask = portmask;
+    op.pagemmd  = pagemmd;
+    op.addr     = addr;
+    op.msb      = msb;
+    op.lsb      = lsb;
+    op.data     = data;
+    op.compare_op = RTK_PATCH_CMP_W;
+
+    return pPhy_patchDb->fPatch_op(unit, port, portOffset, &op, patch_mode);
+}
+
+static int32 _phy_patch_process(uint32 unit, rtk_port_t port, uint8 portOffset, rtk_hwpatch_t *pPatch, int32 size, uint8 patch_mode)
+{
+    int32 i = 0;
+    int32 ret = 0;
+    int32 chk_ret = RT_ERR_OK;
+    int32 n;
+    rtk_hwpatch_t *patch = pPatch;
+    rt_phy_patch_db_t *pPatchDb = NULL;
+
+    PHYPATCH_DB_GET(unit, port, pPatchDb);
+
+    if (size <= 0)
+    {
+        return RT_ERR_OK;
+    }
+    n = size / sizeof(rtk_hwpatch_t);
+
+    for (i = 0; i < n; i++)
+    {
+        ret = pPatchDb->fPatch_op(unit, port, portOffset, &patch[i], patch_mode);
+        if ((ret != RT_ERR_ABORT) && (ret != RT_ERR_OK))
+        {
+            if ((ret == RT_ERR_CHECK_FAILED) && (patch_mode == PHY_PATCH_MODE_CMP))
+            {
+                osal_printf("PATCH CHECK: Failed entry:%u|%u|0x%X|0x%X|%u|%u|0x%X\n",
+                            i + 1, patch[i].patch_op, patch[i].pagemmd, patch[i].addr, patch[i].msb, patch[i].lsb, patch[i].data);
+                chk_ret = RT_ERR_CHECK_FAILED;
+                continue;
+            }
+            else
+            {
+                RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u %s failed! %u[%u][0x%X][0x%X][0x%X] ret=0x%X\n", unit, port, __FUNCTION__,
+                       i+1, patch[i].patch_op, patch[i].pagemmd, patch[i].addr, patch[i].data, ret);
+                return ret;
+            }
+        }
+
+    }
+    return (chk_ret == RT_ERR_CHECK_FAILED) ? chk_ret : RT_ERR_OK;
+}
+
+/* Function Name:
+ *      phy_patch
+ * Description:
+ *      apply initial patch data to PHY
+ * Input:
+ *      unit       - unit id
+ *      port       - port id
+ *      portOffset - the index offset of port based the base port in the PHY chip
+ * Output:
+ *      None
+ * Return:
+ *      RT_ERR_OK
+ *      RT_ERR_FAILED
+ *      RT_ERR_CHECK_FAILED
+ *      RT_ERR_NOT_SUPPORTED
+ * Note:
+ *      None
+ */
+int32 phy_patch(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode)
+{
+    int32 ret = RT_ERR_OK;
+    int32 chk_ret = RT_ERR_OK;
+    uint32 i = 0;
+    uint8 patch_type = 0;
+    rt_phy_patch_db_t *pPatchDb = NULL;
+    rtk_hwpatch_seq_t *table = NULL;
+
+    PHYPATCH_DB_GET(unit, port, pPatchDb);
+
+    if ((pPatchDb == NULL) || (pPatchDb->fPatch_op == NULL) || (pPatchDb->fPatch_flow == NULL))
+    {
+        RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u phy_patch, db is NULL\n", unit, port);
+        return RT_ERR_DRIVER_NOT_SUPPORTED;
+    }
+
+    if (patch_mode == PHY_PATCH_MODE_CMP)
+    {
+        table = pPatchDb->cmp_table;
+    }
+    else
+    {
+        table = pPatchDb->seq_table;
+    }
+    RT_LOG(LOG_INFO, (MOD_HAL | MOD_PHY), "phy_patch: U%u P%u portOffset:%u  patch_mode:%u\n", unit, port, portOffset, patch_mode);
+
+    for (i = 0; i < RTK_PATCH_SEQ_MAX; i++)
+    {
+        patch_type = table[i].patch_type;
+        RT_LOG(LOG_INFO, (MOD_HAL | MOD_PHY), "phy_patch: table[%u] patch_type:%u\n", i, patch_type);
+
+        if (RTK_PATCH_TYPE_IS_DATA(patch_type))
+        {
+            ret = _phy_patch_process(unit, port, portOffset, table[i].patch.data.conf, table[i].patch.data.size, patch_mode);
+
+            if (ret == RT_ERR_CHECK_FAILED)
+                chk_ret = ret;
+            else if (ret  != RT_ERR_OK)
+            {
+                RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u patch_mode:%u id:%u patch-%u failed. ret:0x%X\n", unit, port, patch_mode, i, patch_type, ret);
+                return ret;
+            }
+        }
+        else if (RTK_PATCH_TYPE_IS_FLOW(patch_type))
+        {
+            RT_ERR_CHK_EHDL(pPatchDb->fPatch_flow(unit, port, portOffset, table[i].patch.flow_id, patch_mode),
+                            ret, RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u patch_mode:%u id:%u patch-%u failed. ret:0x%X\n", unit, port, patch_mode, i, patch_type, ret););
+        }
+        else
+        {
+            break;
+        }
+    }
+
+    return (chk_ret == RT_ERR_CHECK_FAILED) ? chk_ret : RT_ERR_OK;
+}
+
+
+
+
diff --git a/sources/rtk-gp3000/src/hal/phy/phy_patch.h b/sources/rtk-gp3000/src/hal/phy/phy_patch.h
new file mode 100644
index 00000000..9781df2b
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/phy_patch.h
@@ -0,0 +1,173 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
+ */
+
+#ifndef __HAL_PHY_PATCH_H__
+#define __HAL_PHY_PATCH_H__
+
+/*
+ * Include Files
+ */
+#if defined(RTK_PHYDRV_IN_LINUX)
+  #include "rtk_phylib_def.h"
+#else
+  #include <common/rt_type.h>
+  #include <common/rt_autoconf.h>
+#endif
+
+/*
+ * Symbol Definition
+ */
+#define PHYPATCH_PHYCTRL_IN_HALCTRL   0  /* 3.6.x: 1 ,4.0.x: 1, 4.1.x+: 0 */
+#define PHYPATCH_FMAILY_IN_HWP        0  /* 3.6.x: 1 ,4.0.x: 0, 4.1.x+: 0 */
+#define PHY_PATCH_MODE_BCAST_DEFAULT  PHY_PATCH_MODE_BCAST  /* 3.6.x: PHY_PATCH_MODE_BCAST_BUS ,4.0.x+: PHY_PATCH_MODE_BCAST */
+
+#define PHY_PATCH_MODE_NORMAL       0
+#define PHY_PATCH_MODE_CMP          1
+#define PHY_PATCH_MODE_BCAST        2
+#define PHY_PATCH_MODE_BCAST_BUS    3
+
+#define RTK_PATCH_CMP_W        0  /* write */
+#define RTK_PATCH_CMP_WC       1  /* compare */
+#define RTK_PATCH_CMP_SWC      2  /* sram compare */
+#define RTK_PATCH_CMP_WS       3  /* skip */
+
+#define RTK_PATCH_OP_SECTION_SIZE           50
+#define RTK_PATCH_OP_TO_CMP(_op, _cmp)       (_op + (RTK_PATCH_OP_SECTION_SIZE * _cmp))
+/* 0~49 normal op */
+#define RTK_PATCH_OP_PHY                     0
+#define RTK_PATCH_OP_PHYOCP                  1
+#define RTK_PATCH_OP_TOP                     2
+#define RTK_PATCH_OP_TOPOCP                  3
+#define RTK_PATCH_OP_PSDS0                   4
+#define RTK_PATCH_OP_PSDS1                   5
+#define RTK_PATCH_OP_MSDS                    6
+#define RTK_PATCH_OP_MAC                     7
+
+/* 50~99 normal op for compare */
+#define RTK_PATCH_OP_CMP_PHY                 RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PHY     , RTK_PATCH_CMP_WC)
+#define RTK_PATCH_OP_CMP_PHYOCP              RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PHYOCP  , RTK_PATCH_CMP_WC)
+#define RTK_PATCH_OP_CMP_TOP                 RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_TOP     , RTK_PATCH_CMP_WC)
+#define RTK_PATCH_OP_CMP_TOPOCP              RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_TOPOCP  , RTK_PATCH_CMP_WC)
+#define RTK_PATCH_OP_CMP_PSDS0               RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PSDS0   , RTK_PATCH_CMP_WC)
+#define RTK_PATCH_OP_CMP_PSDS1               RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PSDS1   , RTK_PATCH_CMP_WC)
+#define RTK_PATCH_OP_CMP_MSDS                RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_MSDS    , RTK_PATCH_CMP_WC)
+#define RTK_PATCH_OP_CMP_MAC                 RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_MAC     , RTK_PATCH_CMP_WC)
+
+/* 100~149 normal op for sram compare */
+#define RTK_PATCH_OP_CMP_SRAM_PHY            RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PHY     , RTK_PATCH_CMP_SWC)
+#define RTK_PATCH_OP_CMP_SRAM_PHYOCP         RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PHYOCP  , RTK_PATCH_CMP_SWC)
+#define RTK_PATCH_OP_CMP_SRAM_TOP            RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_TOP     , RTK_PATCH_CMP_SWC)
+#define RTK_PATCH_OP_CMP_SRAM_TOPOCP         RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_TOPOCP  , RTK_PATCH_CMP_SWC)
+#define RTK_PATCH_OP_CMP_SRAM_PSDS0          RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PSDS0   , RTK_PATCH_CMP_SWC)
+#define RTK_PATCH_OP_CMP_SRAM_PSDS1          RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_PSDS1   , RTK_PATCH_CMP_SWC)
+#define RTK_PATCH_OP_CMP_SRAM_MSDS           RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_MSDS    , RTK_PATCH_CMP_SWC)
+#define RTK_PATCH_OP_CMP_SRAM_MAC            RTK_PATCH_OP_TO_CMP(RTK_PATCH_OP_MAC     , RTK_PATCH_CMP_SWC)
+
+/* 200~255 control op */
+#define RTK_PATCH_OP_DELAY_MS                200
+#define RTK_PATCH_OP_SKIP                    255
+
+/*
+   patch type  PHY_PATCH_TYPE_NONE => empty
+   patch type: PHY_PATCH_TYPE_TOP ~ (PHY_PATCH_TYPE_END-1)  => data array
+   patch type: PHY_PATCH_TYPE_END ~ (PHY_PATCH_TYPE_END + RTK_PATCH_TYPE_FLOW_MAX)  => flow
+*/
+#define RTK_PATCH_TYPE_IS_DATA(_patch_type)    (_patch_type > PHY_PATCH_TYPE_NONE && _patch_type < PHY_PATCH_TYPE_END)
+#define RTK_PATCH_TYPE_IS_FLOW(_patch_type)    (_patch_type >= PHY_PATCH_TYPE_END && _patch_type <= (PHY_PATCH_TYPE_END + RTK_PATCH_TYPE_FLOWID_MAX))
+
+
+/*
+ * Macro Definition
+ */
+#if PHYPATCH_PHYCTRL_IN_HALCTRL
+  #define PHYPATCH_DB_GET(_unit, _port, _pPatchDb) \
+    do {\
+        hal_control_t   *pHalCtrl = NULL;\
+        if ((pHalCtrl = hal_ctrlInfo_get(_unit)) == NULL)\
+            return RT_ERR_FAILED;\
+        _pPatchDb = (pHalCtrl->pPhy_ctrl[_port]->pPhy_patchDb);\
+    } while(0)
+#else
+  #if defined(RTK_PHYDRV_IN_LINUX)
+  #else
+    #include <hal/phy/phydef.h>
+    #include <hal/phy/phy_probe.h>
+  #endif
+  #define PHYPATCH_DB_GET(_unit, _port, _pPatchDb) \
+    do {\
+        rt_phyctrl_t *pPhyCtrl = NULL;\
+        if ((pPhyCtrl = phy_phyctrl_get(_unit, _port)) == NULL)\
+            return RT_ERR_FAILED;\
+        _pPatchDb = (pPhyCtrl->pPhy_patchDb);\
+    } while(0)
+#endif
+
+#if PHYPATCH_FMAILY_IN_HWP
+  #define PHYPATCH_IS_RTKSDS(_unit) (HWP_9300_FAMILY_ID(_unit) || HWP_9310_FAMILY_ID(_unit))
+#else
+  #define PHYPATCH_IS_RTKSDS(_unit) (RTK_9300_FAMILY_ID(_unit) || RTK_9310_FAMILY_ID(_unit) || RTK_9311B_FAMILY_ID(_unit) || RTK_9330_FAMILY_ID(_unit))
+#endif
+
+#define PHYPATCH_TABLE_ASSIGN(_pPatchDb, _table, _idx, _patch_type, _para) \
+    do {\
+        if (RTK_PATCH_TYPE_IS_DATA(_patch_type)) {\
+            _pPatchDb->_table[_idx].patch_type = _patch_type;\
+            _pPatchDb->_table[_idx].patch.data.conf = _para;\
+            _pPatchDb->_table[_idx].patch.data.size = sizeof(_para);\
+        }\
+        else if (RTK_PATCH_TYPE_IS_FLOW(_patch_type)) {\
+            _pPatchDb->_table[_idx].patch_type = _patch_type;\
+            _pPatchDb->_table[_idx].patch.flow_id = _patch_type;\
+        }\
+        else {\
+            _pPatchDb->_table[_idx].patch_type = PHY_PATCH_TYPE_NONE;\
+        }\
+    } while(0)
+#define PHYPATCH_SEQ_TABLE_ASSIGN(_pPatchDb, _idx, _patch_type, _para) PHYPATCH_TABLE_ASSIGN(_pPatchDb, seq_table, _idx, _patch_type, _para)
+#define PHYPATCH_CMP_TABLE_ASSIGN(_pPatchDb, _idx, _patch_type, _para) PHYPATCH_TABLE_ASSIGN(_pPatchDb, cmp_table, _idx, _patch_type, _para)
+
+#define PHYPATCH_COMPARE(_mmdpage, _reg, _msb, _lsb, _exp, _real, _mask) \
+    do {\
+        uint32 _rData = REG32_FIELD_GET(_real, _lsb, _mask);\
+        if (_exp != _rData) {\
+            osal_printf("PATCH CHECK: %u(0x%X).%u(0x%X)[%u:%u] = 0x%X (!= 0x%X)\n", _mmdpage, _mmdpage, _reg, _reg, _msb, _lsb, _rData, _exp);\
+            return RT_ERR_CHECK_FAILED;\
+        }\
+    } while (0)
+
+/*
+ * Function Declaration
+ */
+
+extern uint8 phy_patch_op_translate(uint8 patch_mode, uint8 patch_op, uint8 compare_op);
+extern int32 phy_patch_op(rt_phy_patch_db_t *pPhy_patchDb, uint32 unit, rtk_port_t port, uint8 portOffset,
+                            uint8 patch_op, uint16 portmask, uint16 pagemmd, uint16 addr, uint8 msb, uint8 lsb, uint16 data,
+                            uint8 patch_mode);
+
+
+/* Function Name:
+ *      phy_patch
+ * Description:
+ *      apply initial patch data to PHY
+ * Input:
+ *      unit       - unit id
+ *      port       - port id
+ *      portOffset - the index offset of port based the base port in the PHY chip
+ * Output:
+ *      None
+ * Return:
+ *      RT_ERR_OK
+ *      RT_ERR_FAILED
+ *      RT_ERR_CHECK_FAILED
+ *      RT_ERR_NOT_SUPPORTED
+ * Note:
+ *      None
+ */
+extern int32 phy_patch(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode);
+
+
+
+#endif /* __HAL_PHY_PATCH_H__ */
diff --git a/sources/rtk-gp3000/src/hal/phy/phy_rtl8224_patch.c b/sources/rtk-gp3000/src/hal/phy/phy_rtl8224_patch.c
new file mode 100644
index 00000000..357a1148
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/phy_rtl8224_patch.c
@@ -0,0 +1,641 @@
+/*
+ * Copyright (C) 2009-2022 Realtek Semiconductor Corp.
+ * All Rights Reserved.
+ *
+ * This program is the proprietary software of Realtek Semiconductor
+ * Corporation and/or its licensors, and only be used, duplicated,
+ * modified or distributed under the authorized license from Realtek.
+ *
+ * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER
+ * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED.
+ *
+ * $Revision: $
+ * $Date: $
+ *
+ * Purpose : PHY 8224 HW patch APIs.
+ *
+ * Feature : PHY 8224 HW patch APIs
+ *
+ */
+
+/*
+ * Include Files
+ */
+
+#if defined(RTK_PHYDRV_IN_LINUX)
+  #include "phy_rtl8224_patch.h"
+  #include "construct/conf_rtl8224.c"
+  #include "rtk_phylib_rtl8224.h"
+#else
+#include <common/rt_type.h>
+#include <common/rt_error.h>
+#include <common/debug/rt_log.h>
+#include <soc/type.h>
+#include <hal/common/halctrl.h>
+#include <hal/mac/miim_common_drv.h>
+#include <hal/phy/phy_construct.h>
+#include <osal/time.h>
+#include <hal/phy/construct/conftypes.h>
+#if defined(CONFIG_SDK_RTL8224)
+#include <hal/phy/phy_rtl8224.h>
+#include <hal/phy/construct/conf_rtl8224.c>
+#endif
+#endif
+
+/*
+ * Symbol Definition
+ */
+#define PHY_PATCH_OP_NORMAL             0
+#define PHY_PATCH_OP_BCAST              1
+#define PHY_PATCH_OP_BCAST_SAME_CHIP    2
+#define PHY_PATCH_WAIT_TIMEOUT          10000000
+
+#define PHY_PATCH_LOG                   LOG_INFO
+
+
+/*
+ * Data Declaration
+ */
+
+rtk_phy_hwpatch_t *patch_fwpr_conf;
+rtk_phy_hwpatch_t *patch_fwlm_conf;
+rtk_phy_hwpatch_t *patch_afe_conf;
+rtk_phy_hwpatch_t *patch_top_conf;
+rtk_phy_hwpatch_t *patch_sds_conf;
+int32 patch_fwpr_conf_size;
+int32 patch_fwlm_conf_size;
+int32 patch_afe_conf_size;
+int32 patch_top_conf_size;
+int32 patch_sds_conf_size;
+
+
+/*
+ * Macro Declaration
+ */
+
+
+/*
+ * Function Declaration
+ */
+
+uint32
+_phy_rtl8224_patch_mask(uint8 msb, uint8 lsb)
+{
+    uint32  val = 0;
+    uint8   i = 0;
+
+    for (i = lsb; i <= msb; i++)
+    {
+        val |= (1 << i);
+    }
+    return val;
+}
+
+int32
+_phy_rtl8224_patch_mask_get(uint8 msb, uint8 lsb, uint32 *mask)
+{
+    if ((msb > 15) || (lsb > 15) || (msb < lsb))
+    {
+        return RT_ERR_FAILED;
+    }
+    *mask = _phy_rtl8224_patch_mask(msb, lsb);
+    return RT_ERR_OK;
+}
+
+
+int32
+_phy_rtl8224_patch_wait(uint32 unit, rtk_port_t port, uint32 mmdAddr, uint32 mmdReg, uint32 data, uint32 mask, uint8 bcast_op)
+{
+    int32   ret = RT_ERR_OK;
+    uint32  rData = 0;
+    uint32  cnt = 0;
+    WAIT_COMPLETE_VAR()
+
+
+    WAIT_COMPLETE(PHY_PATCH_WAIT_TIMEOUT)
+    {
+        if ((ret = phy_common_general_reg_mmd_get(unit, port, mmdAddr, mmdReg, &rData)) != RT_ERR_OK)
+            return ret;
+
+        ++cnt;
+        if ((rData & mask) == data)
+            break;
+
+        osal_time_mdelay(1);
+    }
+
+    if (WAIT_COMPLETE_IS_TIMEOUT())
+    {
+        PR_ERR("U%u 8224 patch wait[%u,0x%X,0x%X,0x%X]:0x%X cnt:%u\n", unit, mmdAddr, mmdReg, data, mask, rData, cnt);
+        return RT_ERR_TIMEOUT;
+    }
+
+    return RT_ERR_OK;
+}
+
+
+int32
+_phy_rtl8224_patch_wait_not_equal(uint32 unit, rtk_port_t port, uint32 mmdAddr, uint32 mmdReg, uint32 data, uint32 mask, uint8 bcast_op)
+{
+    int32   ret = RT_ERR_OK;
+    uint32  rData = 0;
+    uint32  cnt = 0;
+    WAIT_COMPLETE_VAR()
+
+    WAIT_COMPLETE(PHY_PATCH_WAIT_TIMEOUT)
+    {
+        if ((ret = phy_common_general_reg_mmd_get(unit, port, mmdAddr, mmdReg, &rData)) != RT_ERR_OK)
+            return ret;
+
+        ++cnt;
+        if ((rData & mask) != data)
+            break;
+
+        osal_time_mdelay(1);
+    }
+    if(WAIT_COMPLETE_IS_TIMEOUT())
+    {
+        RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 8224 patch wait[%u,0x%X,0x%X,0x%X]:0x%X cnt:%u\n", unit, port, mmdAddr, mmdReg, data, mask, rData, cnt);
+        return RT_ERR_TIMEOUT;
+    }
+
+    return RT_ERR_OK;
+}
+
+int32
+_phy_rtl8224_patch_top_get(uint32 unit, rtk_port_t port, uint32 topPage, uint32 topReg, uint32 *pData)
+{
+    int32   ret = RT_ERR_OK;
+    uint32  rData = 0;
+
+    if ((ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_VEND1, topReg, &rData)) != RT_ERR_OK)
+        return ret;
+    *pData = rData;
+
+    return RT_ERR_OK;
+}
+
+int32
+_phy_rtl8224_patch_top_set(uint32 unit, rtk_port_t port, uint32 topPage, uint32 topReg, uint32 wData)
+{
+    int32   ret = RT_ERR_OK;
+
+    if ((ret = phy_common_general_reg_mmd_set(unit, port, PHY_MMD_VEND1, topReg, wData)) != RT_ERR_OK)
+        return ret;
+
+    return RT_ERR_OK;
+}
+
+int32
+_phy_rtl8224_patch_sds_get(uint32 unit, rtk_port_t port, uint32 sdsPage, uint32 sdsReg, uint32 *pData)
+{
+    int32   ret = RT_ERR_OK;
+    uint32  rData = 0;
+    uint32  sdsAddr = (0x1 << 15) | (0x0 << 14) | (sdsReg << 7) | (sdsPage << 1);
+
+    if ((ret = _phy_rtl8224_patch_top_set(unit, port, 0, 0x3F8, sdsAddr)) != RT_ERR_OK)
+        return ret;
+
+    if ((ret = _phy_rtl8224_patch_top_get(unit, port, 0, 0x3FC, &rData)) != RT_ERR_OK)
+        return ret;
+    *pData = rData;
+
+    return _phy_rtl8224_patch_wait(unit, port, PHY_MMD_VEND1, 0x3F8, 0, BIT_15, PHY_PATCH_OP_NORMAL);
+}
+
+int32
+_phy_rtl8224_patch_sds_set(uint32 unit, rtk_port_t port, uint32 sdsPage, uint32 sdsReg, uint32 wData, uint8 bcast)
+{
+    int32   ret = RT_ERR_OK;
+    uint32  sdsAddr = (0x1 << 15) | (0x1 << 14) | (sdsReg << 7) | (sdsPage << 1);
+
+    if ((ret = _phy_rtl8224_patch_top_set(unit, port, 0, 0x400, wData)) != RT_ERR_OK)
+        return ret;
+    if ((ret = _phy_rtl8224_patch_top_set(unit, port, 0, 0x3F8, sdsAddr)) != RT_ERR_OK)
+        return ret;
+
+    return _phy_rtl8224_patch_wait(unit, port, PHY_MMD_VEND1, 0x3F8, 0, BIT_15, bcast);
+}
+
+int32
+phy_rtl8224_patch_process_op(uint32 unit, rtk_port_t port, uint8 portOffset, rtk_phy_hwpatch_t *op, uint8 bcast)
+{
+    int32   ret = RT_ERR_OK;
+    uint32  mask = 0;
+    uint32  rData = 0;
+    uint32  wData = 0;
+
+    if ((op->portmask & (1 << portOffset)) == 0)
+    {
+        return RT_ERR_ABORT;
+    }
+
+    ret = _phy_rtl8224_patch_mask_get(op->msb, op->lsb, &mask);
+
+    if (ret != RT_ERR_OK)
+        return ret;
+
+    switch (op->patch_op)
+    {
+        case RTK_HWPATCH_OP_PHY:
+            if ((op->msb != 15) || (op->lsb != 0))
+            {
+                if ((ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_VEND2, op->addr, &rData)) != RT_ERR_OK)
+                {
+                    PR_ERR("\n[port = %d] addr = 0x%08x ERROR!!!!!\n",port->mdio.addr, op->addr);
+                    return ret;
+                }
+            }
+            wData = REG32_FIELD_SET(rData, op->data, op->lsb, mask);
+            if ((ret = phy_common_general_reg_mmd_set(unit, port, PHY_MMD_VEND2, op->addr, wData)) != RT_ERR_OK)
+                return ret;
+            break;
+
+        case RTK_HWPATCH_OP_MMD:
+            if ((op->msb != 15) || (op->lsb != 0))
+            {
+                if ((ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_VEND1, op->addr, &rData)) != RT_ERR_OK)
+                    return ret;
+            }
+            wData = REG32_FIELD_SET(rData, op->data, op->lsb, mask);
+            if ((ret = phy_common_general_reg_mmd_set(unit, port, PHY_MMD_VEND1, op->addr, wData)) != RT_ERR_OK)
+                return ret;
+
+            break;
+
+        case RTK_HWPATCH_OP_TOP:
+            if ((op->msb != 15) || (op->lsb != 0))
+            {
+                if ((ret = _phy_rtl8224_patch_top_get(unit, port, PHY_MMD_VEND1, op->addr, &rData)) != RT_ERR_OK)
+                    return ret;
+            }
+            wData = REG32_FIELD_SET(rData, op->data, op->lsb, mask);
+
+            if ((ret = _phy_rtl8224_patch_top_set(unit, port, PHY_MMD_VEND1, op->addr, wData)) != RT_ERR_OK)
+                return ret;
+
+            break;
+
+        case RTK_HWPATCH_OP_SDS:
+            if ((op->msb != 15) || (op->lsb != 0))
+            {
+                if ((ret = _phy_rtl8224_patch_sds_get(unit, port, op->pagemmd, op->addr, &rData)) != RT_ERR_OK)
+                    return ret;
+            }
+            wData = REG32_FIELD_SET(rData, op->data, op->lsb, mask);
+
+            if ((ret = _phy_rtl8224_patch_sds_set(unit, port, op->pagemmd, op->addr, wData, bcast)) != RT_ERR_OK)
+                return ret;
+
+            break;
+
+        case RTK_HWPATCH_OP_PHYW:
+        case RTK_HWPATCH_OP_ALGO:
+        case RTK_HWPATCH_OP_DATARAM:
+        case RTK_HWPATCH_OP_UNKNOWN:
+        default:
+            return RT_ERR_INPUT;
+    }
+
+    return RT_ERR_OK;
+}
+
+int32
+phy_rtl8224_patch_op(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_op, uint8 portmask, uint16 pagemmd, uint16 addr, uint8 msb, uint8 lsb, uint16 data)
+{
+    rtk_phy_hwpatch_t op;
+
+    op.patch_op = patch_op;
+    op.portmask = portmask;
+    op.pagemmd  = pagemmd;
+    op.addr     = addr;
+    op.msb      = msb;
+    op.lsb      = lsb;
+    op.data     = data;
+
+    return phy_rtl8224_patch_process_op(unit, port, portOffset, &op, PHY_PATCH_OP_NORMAL);
+}
+
+int32
+_phy_rtl8224_patch_process(uint32 unit, rtk_port_t port, uint8 portOffset, rtk_phy_hwpatch_t *pPatch, int32 size, uint32 *cnt, uint8 bcast)
+{
+    int32               ret = RT_ERR_OK;
+    int32               i = 0;
+    int32               n = 0;
+    rtk_phy_hwpatch_t   *patch = pPatch;
+
+    if (size <= 0)
+    {
+        *cnt = 0;
+        return RT_ERR_OK;
+    }
+    n = size/sizeof(rtk_phy_hwpatch_t);
+
+    for (i = 0; i < n; i++)
+    {
+        ret = phy_rtl8224_patch_process_op(unit, port, portOffset, &patch[i], bcast);
+        if ((ret != RT_ERR_ABORT) && (ret != RT_ERR_OK))
+        {
+            RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u %s failed! i=%u ret=0x%X\n", unit, port, __FUNCTION__, i, ret);
+            return ret;
+        }
+    }
+    *cnt = i;
+
+    return RT_ERR_OK;
+}
+
+int32
+_phy_rtl8224_patch_assign(uint32 unit, rtk_port_t port, uint32 chipVer)
+{
+    if(chipVer == PHY_RTL8224_VER_A)
+    {
+        patch_fwpr_conf = rtl8224_a_patch_fwpr_conf;
+        patch_fwlm_conf = rtl8224_a_patch_fwlm_conf;
+        patch_afe_conf = rtl8224_a_patch_afe_conf;
+        patch_top_conf = rtl8224_a_patch_top_conf;
+        patch_sds_conf = rtl8224_a_patch_sds_conf;
+        patch_fwpr_conf_size = sizeof(rtl8224_a_patch_fwpr_conf);
+        patch_fwlm_conf_size= sizeof(rtl8224_a_patch_fwlm_conf);
+        patch_afe_conf_size= sizeof(rtl8224_a_patch_afe_conf);
+        patch_top_conf_size= sizeof(rtl8224_a_patch_top_conf);
+        patch_sds_conf_size= sizeof(rtl8224_a_patch_sds_conf);
+    }
+    else if(chipVer == PHY_RTL8224_VER_B)
+    {
+        patch_fwpr_conf = rtl8224_b_patch_fwpr_conf;
+        patch_fwlm_conf = rtl8224_b_patch_fwlm_conf;
+        patch_afe_conf = rtl8224_b_patch_afe_conf;
+        patch_top_conf = rtl8224_b_patch_top_conf;
+        patch_sds_conf = rtl8224_b_patch_sds_conf;
+        patch_fwpr_conf_size = sizeof(rtl8224_b_patch_fwpr_conf);
+        patch_fwlm_conf_size= sizeof(rtl8224_b_patch_fwlm_conf);
+        patch_afe_conf_size= sizeof(rtl8224_b_patch_afe_conf);
+        patch_top_conf_size= sizeof(rtl8224_b_patch_top_conf);
+        patch_sds_conf_size= sizeof(rtl8224_b_patch_sds_conf);
+    }else{
+        patch_fwpr_conf = rtl8224_patch_fwpr_conf;
+        patch_fwlm_conf = rtl8224_patch_fwlm_conf;
+        patch_afe_conf = rtl8224_patch_afe_conf;
+        patch_top_conf = rtl8224_patch_top_conf;
+        patch_sds_conf = rtl8224_patch_sds_conf;
+        patch_fwpr_conf_size = sizeof(rtl8224_patch_fwpr_conf);
+        patch_fwlm_conf_size= sizeof(rtl8224_patch_fwlm_conf);
+        patch_afe_conf_size= sizeof(rtl8224_patch_afe_conf);
+        patch_top_conf_size= sizeof(rtl8224_patch_top_conf);
+        patch_sds_conf_size= sizeof(rtl8224_patch_sds_conf);
+    }
+    return RT_ERR_OK;
+}
+
+int32
+_phy_rtl8224_patch_version_assign(uint32 unit, rtk_port_t port, uint8 portOffset, uint32 chipVer)
+{
+    int32   ret = RT_ERR_OK;
+    //writephy_ocp $phynum 0xA438 $currentVersion
+    if((chipVer == PHY_RTL8224_VER_A) || (chipVer == PHY_RTL8224_VER_B))
+    {
+        ret = phy_rtl8224_patch_op(unit, port, portOffset, RTK_HWPATCH_OP_PHY, 0xff, 0x00, 0xA438, 15, 0, RTL8224_AB_FW_VER);
+    }
+    else
+    {
+        ret = phy_rtl8224_patch_op(unit, port, portOffset, RTK_HWPATCH_OP_PHY, 0xff, 0x00, 0xA438, 15, 0, RTL8224_FW_VER);
+    }
+    return ret;
+}
+
+
+int32
+_phy_rtl8224_patch(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 bcast)
+{
+    int32   ret = RT_ERR_OK;
+    uint32  cnt = 0;
+    uint32  chipVer = 5;
+
+    phy_8224_chipVer_get(unit, port, &chipVer);
+
+    _phy_rtl8224_patch_assign(unit, port, chipVer);
+
+    //Patch Request
+    //PP_PHYReg w $PHYID 0xB820 bit.4 0x1 patch request
+    if ((ret = phy_rtl8224_patch_op(unit, port, portOffset, RTK_HWPATCH_OP_PHY, 0xff, 0x00, 0xb820, 4, 4, 0x1)) != RT_ERR_OK)
+        return ret;
+
+
+    //PP_PHYReg_bit r $PHYID 0xB800 6 6 wait 1
+    if ((ret = _phy_rtl8224_patch_wait(unit, port, PHY_MMD_VEND2, 0xB800, BIT_6, BIT_6, bcast)) != RT_ERR_OK)
+        return ret;
+
+
+    if ((ret = _phy_rtl8224_patch_process(unit, port, portOffset, patch_fwpr_conf, patch_fwpr_conf_size, &cnt, bcast))!= RT_ERR_OK)
+    {
+        RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 8224 fwpr patch failed. ret:0x%X\n", unit, port, ret);
+        return ret;
+    }
+
+    RT_LOG(PHY_PATCH_LOG, (MOD_HAL | MOD_PHY), "U%u P%u 8224 fwpr patch done. ret:0x%X cnt:%d\n", unit, port, ret, cnt);
+
+    //PP_PHYReg w $PHYID 0xB820 0x0000
+    if ((ret = phy_rtl8224_patch_op(unit, port, portOffset, RTK_HWPATCH_OP_PHY, 0xff, 0x00, 0xb820, 4, 4, 0x0)) != RT_ERR_OK)
+        return ret;
+
+    //PP_PHYReg_bit r $PHYID 0xB800 6 6  wait 0 (Release patch request & wait patch_rdy = 0)
+    if ((ret = _phy_rtl8224_patch_wait(unit, port, PHY_MMD_VEND2, 0xB800, 0, BIT_6, bcast)) != RT_ERR_OK)
+        return ret;
+
+    //Lock Main
+    //writephybits_ocp $phynum 0xa4a0 10 10 0x1
+    if ((ret = phy_rtl8224_patch_op(unit, port, portOffset, RTK_HWPATCH_OP_PHY, 0xff, 0x00, 0xA4A0, 10, 10, 0x1)) != RT_ERR_OK)
+        return ret;
+    //[PP_PHYReg_bit r $PHYID 0xa600 7 0]
+    if ((ret = _phy_rtl8224_patch_wait(unit, port, PHY_MMD_VEND2, 0xa600, 0x1, 0xFF, bcast)) != RT_ERR_OK)
+        return ret;
+
+    if ((ret = _phy_rtl8224_patch_process(unit, port, portOffset, patch_fwlm_conf, patch_fwlm_conf_size, &cnt, bcast))!= RT_ERR_OK)
+    {
+        RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 8224 fwlm patch failed. ret:0x%X\n", unit, port, ret);
+        return ret;
+    }
+    RT_LOG(PHY_PATCH_LOG, (MOD_HAL | MOD_PHY), "U%u P%u 8224 fwlm patch done. ret:0x%X cnt:%d\n", unit, port, ret, cnt);
+
+    if ((ret = _phy_rtl8224_patch_process(unit, port, portOffset, patch_afe_conf, patch_afe_conf_size, &cnt, bcast)) != RT_ERR_OK)
+    {
+        RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 8224 afe patch failed. ret:0x%X\n", unit, port, ret);
+        return ret;
+    }
+    RT_LOG(PHY_PATCH_LOG, (MOD_HAL | MOD_PHY), "U%u P%u 8224 afe patch done. ret:0x%X cnt:%d\n", unit, port, ret, cnt);
+
+    //Patch PHY
+    if(chipVer == PHY_RTL8224_VER_A){
+        //writephy_ocp $phynum 0xa5d0 0x0
+        if ((ret = phy_rtl8224_patch_op(unit, port, portOffset, RTK_HWPATCH_OP_PHY, 0xff, 0x00, 0xa5d0, 15, 0, 0x0)) != RT_ERR_OK)
+            return ret;
+
+        //writephybits_ocp $phynum 0xa430 2 0 0x0
+        if ((ret = phy_rtl8224_patch_op(unit, port, portOffset, RTK_HWPATCH_OP_PHY, 0xff, 0x00, 0xa430, 2, 0, 0x0)) != RT_ERR_OK)
+            return ret;
+    }
+
+    //writephy_ocp $phynum 0xa47E 7 6 0x1
+    if ((ret = phy_rtl8224_patch_op(unit, port, portOffset, RTK_HWPATCH_OP_PHY, 0xff, 0x00, 0xa47E, 7, 6, 0x1)) != RT_ERR_OK)
+        return ret;
+
+    //Release Lock Main
+    //writephybits_ocp $phynum 0xa4a0 10 10 0x0
+    if ((ret = phy_rtl8224_patch_op(unit, port, portOffset, RTK_HWPATCH_OP_PHY, 0xff, 0x00, 0xA4A0, 10, 10, 0x0)) != RT_ERR_OK)
+        return ret;
+
+    //[PP_PHYReg_bit r $PHYID 0xa600 7 0]
+    if ((ret = _phy_rtl8224_patch_wait_not_equal(unit, port, PHY_MMD_VEND2, 0xa600, 0x1, 0xFF, bcast)) != RT_ERR_OK)
+        return ret;
+
+    if ((ret = _phy_rtl8224_patch_process(unit, port, portOffset, patch_top_conf, patch_top_conf_size, &cnt, bcast))!= RT_ERR_OK)
+    {
+        RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 8224 top patch failed. ret:0x%X\n", unit, port, ret);
+        return ret;
+    }
+    RT_LOG(PHY_PATCH_LOG, (MOD_HAL | MOD_PHY), "U%u P%u 8224 top patch done. ret:0x%X cnt:%d\n", unit, port, ret, cnt);
+
+    if ((ret = _phy_rtl8224_patch_process(unit, port, portOffset, patch_sds_conf, patch_sds_conf_size, &cnt, bcast))!= RT_ERR_OK)
+    {
+        RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 8224 sds patch failed. ret:0x%X\n", unit, port, ret);
+        return ret;
+    }
+    RT_LOG(PHY_PATCH_LOG, (MOD_HAL | MOD_PHY), "U%u P%u 8224 sds patch done. ret:0x%X cnt:%d\n", unit, port, ret, cnt);
+
+    //writephy_ocp $phynum 0xA436 0x801E
+    if ((ret = phy_rtl8224_patch_op(unit, port, portOffset, RTK_HWPATCH_OP_PHY, 0xff, 0x00, 0xA436, 15, 0, 0x801E)) != RT_ERR_OK)
+        return ret;
+
+    ret = _phy_rtl8224_patch_version_assign(unit, port, portOffset, chipVer);
+
+    return ret;
+}
+
+/* Function Name:
+ *      phy_rtl8224_sdsReg_get
+ * Description:
+ *      Get SerDes Register
+ * Input:
+ *      unit        - unit id
+ *      baseport    - base port id on the PHY chip
+ *      sdsPage     - the SerDes page
+ *      sdsReg      - the SerDes register
+ * Output:
+ *      pData       - return register value
+ * Return:
+ *      RT_ERR_OK
+ *      RT_ERR_FAILED
+ *      RT_ERR_NOT_SUPPORTED
+ *      RT_ERR_ABORT
+ * Note:
+ *      None
+ */
+int32
+phy_rtl8224_sdsReg_get(uint32 unit, rtk_port_t baseport, uint32 sdsPage, uint32 sdsReg, uint32 *pData)
+{
+    _phy_rtl8224_patch_sds_get(unit, baseport, sdsPage, sdsReg, pData);
+
+    return RT_ERR_OK;
+}
+
+/* Function Name:
+ *      phy_rtl8224_sdsReg_set
+ * Description:
+ *      Set SerDes Register
+ * Input:
+ *      unit        - unit id
+ *      baseport    - base port id on the PHY chip
+ *      sdsPage     - the SerDes page
+ *      sdsReg      - the SerDes register
+ *      wData       - the write data
+ * Output:
+ *      None
+ * Return:
+ *      RT_ERR_OK
+ *      RT_ERR_FAILED
+ *      RT_ERR_NOT_SUPPORTED
+ *      RT_ERR_ABORT
+ * Note:
+ *      None
+ */
+
+int32
+phy_rtl8224_sdsReg_set(uint32 unit, rtk_port_t baseport, uint32 sdsPage, uint32 sdsReg, uint32 wData)
+{
+    return _phy_rtl8224_patch_sds_set(unit, baseport, sdsPage, sdsReg, wData, 0);
+}
+
+/* Function Name:
+ *      phy_rtl8224_patch
+ * Description:
+ *      Apply initial patch data to PHY
+ * Input:
+ *      unit        - unit id
+ *      baseport    - base port id on the PHY chip
+ *      portOffset  - the index offset base on baseport for the port to patch
+ * Output:
+ *      None
+ * Return:
+ *      RT_ERR_OK
+ *      RT_ERR_FAILED
+ *      RT_ERR_NOT_SUPPORTED
+ *      RT_ERR_ABORT
+ * Note:
+ *      None
+ */
+int32
+phy_rtl8224_patch(uint32 unit, rtk_port_t port, uint8 portOffset)
+{
+    int32   ret = RT_ERR_OK;
+    uint32  phyData = 0;
+
+    if ((ret = _phy_rtl8224_patch(unit, port, portOffset, PHY_PATCH_OP_NORMAL)) != RT_ERR_OK)
+        return ret;
+
+    /*Disable 100M/1G EEE advertise ability */
+    phyData = 0;
+    if ((ret = phy_common_general_reg_mmd_set(unit, port, PHY_MMD_VEND2, 0xa5d0, phyData)) != RT_ERR_OK)
+        return ret;
+
+    /*Disable 1G lite ability */
+    if ((ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_VEND2, 0xa428, &phyData)) != RT_ERR_OK)
+        return ret;
+    phyData &= ~(BIT_9);
+    if ((ret = phy_common_general_reg_mmd_set(unit, port, PHY_MMD_VEND2, 0xa428, phyData)) != RT_ERR_OK)
+        return ret;
+
+    if (PHYPATCH_IS_RTKSDS(unit))
+    {
+        PR_INFO("\nDisable SerDes AN with Realtek switch");
+        /* Disable USXGMII AN */
+        if ((ret = phy_8224_sdsReg_get(unit, port, 7, 17, &phyData)) != RT_ERR_OK)
+            return ret;
+        phyData &= ~(uint32)(0xf);
+        if ((ret = phy_8224_sdsReg_set(unit, port, 7, 17, phyData)) != RT_ERR_OK)
+            return ret;
+    }
+
+    if (!PHYPATCH_IS_RTKSDS(unit))
+    {
+        if ((ret = phy_8224_sdsOpCode_set(unit, port, 0x3)) != RT_ERR_OK)
+            return ret;
+        if ((ret = phy_8224_sdsAmPeriod_set(unit, port, 0xa4)) != RT_ERR_OK)
+            return ret;
+    }
+    else
+    {
+        PR_INFO("\nConnect to Realtek switch");
+        if ((ret = phy_8224_sdsOpCode_set(unit, port, 0xaa)) != RT_ERR_OK)
+            return ret;
+        if ((ret = phy_8224_sdsAmPeriod_set(unit, port, 0x5078)) != RT_ERR_OK)
+            return ret;
+        if ((ret = phy_8224_sdsAllAm_set(unit, port, 0x0)) != RT_ERR_OK)
+            return ret;
+        if ((ret = phy_8224_sdsExtra_set(unit, port)) != RT_ERR_OK)
+            return ret;
+    }
+
+    return ret;
+}
+
diff --git a/sources/rtk-gp3000/src/hal/phy/phy_rtl8224_patch.h b/sources/rtk-gp3000/src/hal/phy/phy_rtl8224_patch.h
new file mode 100644
index 00000000..482b80a6
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/phy_rtl8224_patch.h
@@ -0,0 +1,128 @@
+/*
+ * Copyright (C) 2009-2022 Realtek Semiconductor Corp.
+ * All Rights Reserved.
+ *
+ * This program is the proprietary software of Realtek Semiconductor
+ * Corporation and/or its licensors, and only be used, duplicated,
+ * modified or distributed under the authorized license from Realtek.
+ *
+ * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER
+ * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED.
+ *
+ * $Revision: $
+ * $Date: $
+ *
+ * Purpose : PHY 8224 HW patch APIs.
+ *
+ * Feature : PHY 8224 HW patch APIs
+ *
+ */
+
+
+#ifndef __HAL_PHY_PHY_RTL8224_PATCH_H__
+#define __HAL_PHY_PHY_RTL8224_PATCH_H__
+
+/*
+ * Include Files
+ */
+#if defined(RTK_PHYDRV_IN_LINUX)
+  #include "rtk_osal.h"
+  #include "rtk_phylib_def.h"
+#else
+  #include <common/rt_type.h>
+  #include <rtk/port.h>
+#endif
+
+/* Function Name:
+ *      phy_rtl8224_sdsReg_get
+ * Description:
+ *      Get SerDes Register
+ * Input:
+ *      unit        - unit id
+ *      baseport    - base port id on the PHY chip
+ *      sdsPage     - the SerDes page
+ *      sdsReg      - the SerDes register
+ * Output:
+ *      pData       - return register value
+ * Return:
+ *      RT_ERR_OK
+ *      RT_ERR_FAILED
+ *      RT_ERR_NOT_SUPPORTED
+ *      RT_ERR_ABORT
+ * Note:
+ *      None
+ */
+extern int32
+phy_rtl8224_sdsReg_get(uint32 unit, rtk_port_t baseport, uint32 sdsPage, uint32 sdsReg, uint32 *pData);
+
+/* Function Name:
+ *      phy_rtl8224_sdsReg_set
+ * Description:
+ *      Set SerDes Register
+ * Input:
+ *      unit        - unit id
+ *      baseport    - base port id on the PHY chip
+ *      sdsPage     - the SerDes page
+ *      sdsReg      - the SerDes register
+ *      wData       - the write data
+ * Output:
+ *      None
+ * Return:
+ *      RT_ERR_OK
+ *      RT_ERR_FAILED
+ *      RT_ERR_NOT_SUPPORTED
+ *      RT_ERR_ABORT
+ * Note:
+ *      None
+ */
+
+extern int32
+phy_rtl8224_sdsReg_set(uint32 unit, rtk_port_t baseport, uint32 sdsPage, uint32 sdsReg, uint32 wData);
+
+
+/* Function Name:
+ *      phy_rtl8224_patch
+ * Description:
+ *      Apply patch data to PHY
+ * Input:
+ *      unit        - unit id
+ *      baseport    - base port id on the PHY chip
+ *      portOffset  - the index offset base on baseport for the port to patch
+ * Output:
+ *      None
+ * Return:
+ *      RT_ERR_OK
+ *      RT_ERR_FAILED
+ *      RT_ERR_NOT_SUPPORTED
+ *      RT_ERR_ABORT
+ * Note:
+ *      None
+ */
+extern int32
+phy_rtl8224_patch(uint32 unit, rtk_port_t baseport, uint8 portOffset);
+
+/* Function Name:
+ *      phy_rtl8224_broadcast_patch
+ * Description:
+ *      Apply patch data to PHY
+ * Input:
+ *      unit        - unit id
+ *      baseport    - base port id on the PHY chip
+ *      portOffset  - the index offset base on baseport for the port to patch
+ *      perChip     - 1 for per-chip mode, 0 for per-bus mode
+ * Output:
+ *      None
+ * Return:
+ *      RT_ERR_OK
+ *      RT_ERR_FAILED
+ *      RT_ERR_NOT_SUPPORTED
+ *      RT_ERR_ABORT
+ * Note:
+ *      None
+ */
+extern int32
+phy_rtl8224_broadcast_patch(uint32 unit, uint8 port, uint8 portOffset, uint8 perChip);
+
+
+#endif /* __HAL_PHY_PHY_RTL8224_PATCH_H__ */
+
diff --git a/sources/rtk-gp3000/src/hal/phy/phy_rtl826xb_patch.c b/sources/rtk-gp3000/src/hal/phy/phy_rtl826xb_patch.c
new file mode 100644
index 00000000..a19b56c9
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/phy_rtl826xb_patch.c
@@ -0,0 +1,1122 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
+ */
+
+/*
+ * Include Files
+ */
+
+/* set LOW_POWER_INIT_PATCH to 1 to initial chip in low power consumption mode
+   and supported max cable length will downgrade to 50M */
+#define LOW_POWER_INIT_PATCH  0
+
+#if defined(RTK_PHYDRV_IN_LINUX)
+  #include "phy_rtl826xb_patch.h"
+  #include "construct/conf_rtl8264b.c"
+  #if LOW_POWER_INIT_PATCH
+    #include "construct/conf_rtl8261n_c_lp.c"
+  #else
+    #include "construct/conf_rtl8261n_c.c"
+  #endif
+#else
+  #include <common/rt_type.h>
+  #include <common/rt_error.h>
+  #include <common/debug/rt_log.h>
+  #include <soc/type.h>
+  #include <hal/common/halctrl.h>
+  #include <hal/mac/miim_common_drv.h>
+  #include <hal/phy/phy_construct.h>
+  #include <osal/time.h>
+  #include <hal/phy/construct/conftypes.h>
+  #include <hal/phy/phy_probe.h>
+  #include <hal/phy/phy_patch.h>
+  #include <osal/memory.h>
+  #if defined(CONFIG_SDK_RTL826XB)
+    #include <hal/phy/phy_rtl826xb.h>
+    #include <hal/phy/construct/conf_rtl8264b.c>
+    #include <hal/phy/construct/conf_rtl8261n_c.c>
+  #endif
+#endif
+/*
+ * Symbol Definition
+ */
+#define PHY_PATCH_WAIT_TIMEOUT     10000000
+
+#define PHY_PATCH_LOG    LOG_INFO
+
+/*
+ * Data Declaration
+ */
+
+/*
+ * Macro Declaration
+ */
+
+/*
+ * Function Declaration
+ */
+static uint16 _phy_rtl826xb_mmd_convert(uint16 page, uint16 addr)
+{
+    uint16 reg = 0;
+    if (addr < 16)
+    {
+        reg = 0xA400 + (page * 2);
+    }
+    else if (addr < 24)
+    {
+        reg = (16*page) + ((addr - 16) * 2);
+    }
+    else
+    {
+        reg = 0xA430 + ((addr - 24) * 2);
+    }
+    return reg;
+}
+
+int32
+_phy_rtl826xb_patch_wait(uint32 unit, rtk_port_t port, uint32 mmdAddr, uint32 mmdReg, uint32 data, uint32 mask, uint8 patch_mode)
+{
+    int32  ret = 0;
+    uint32 rData = 0;
+    uint32 cnt = 0;
+    WAIT_COMPLETE_VAR()
+
+    rtk_port_t  p = 0;
+    uint8  smiBus = HWP_PORT_SMI(unit, port);
+    uint32 phyChip = HWP_PHY_MODEL_BY_PORT(unit, port);
+    uint8  bcast_phyad = HWP_PHY_ADDR(unit, port);
+
+    if (patch_mode == PHY_PATCH_MODE_BCAST_BUS)
+    {
+        if ((ret = phy_826xb_ctrl_set(unit, port, RTK_PHY_CTRL_MIIM_BCAST, 0)) != RT_ERR_OK)
+        {
+            RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826XB patch wait disable broadcast failed! 0x%X\n", unit, p, ret);
+            return ret;
+        }
+
+        HWP_PORT_TRAVS_EXCEPT_CPU(unit, p)
+        {
+            if ((HWP_PORT_SMI(unit, p) == smiBus) && (HWP_PHY_MODEL_BY_PORT(unit, p) == phyChip))
+            {
+                WAIT_COMPLETE(PHY_PATCH_WAIT_TIMEOUT)
+                {
+                    if ((ret = phy_common_general_reg_mmd_get(unit, p, mmdAddr, mmdReg, &rData)) != RT_ERR_OK)
+                    {
+                        return ret;
+                    }
+                    ++cnt;
+
+                    if ((rData & mask) == data)
+                        break;
+
+                    //osal_time_udelay(10);
+                }
+
+                if (WAIT_COMPLETE_IS_TIMEOUT())
+                {
+                    RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826XB patch wait[%u,0x%X,0x%X,0x%X]:0x%X cnt:%u\n", unit, p, mmdAddr, mmdReg, data, mask, rData, cnt);
+                    return RT_ERR_TIMEOUT;
+                }
+            }
+        }
+
+        osal_time_mdelay(1);
+        //for port in same SMI bus, set mdio broadcast ENABLE
+        HWP_PORT_TRAVS_EXCEPT_CPU(unit, p)
+        {
+            if ((HWP_PORT_SMI(unit, p) == smiBus) && (HWP_PHY_MODEL_BY_PORT(unit, p) == phyChip))
+            {
+                if ((ret = phy_826xb_ctrl_set(unit, p, RTK_PHY_CTRL_MIIM_BCAST_PHYAD, (uint32)bcast_phyad)) != RT_ERR_OK)
+                {
+                    RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826XB patch wait set broadcast PHYAD failed! 0x%X\n", unit, p, ret);
+                    return ret;
+                }
+
+                if ((ret = phy_826xb_ctrl_set(unit, p, RTK_PHY_CTRL_MIIM_BCAST, 1)) != RT_ERR_OK)
+                {
+                    RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826XB patch wait enable broadcast failed! 0x%X\n", unit, p, ret);
+                    return ret;
+                }
+            }
+        }
+    }
+    else if (patch_mode == PHY_PATCH_MODE_BCAST)
+    {
+        if ((ret = phy_826xb_ctrl_set(unit, port, RTK_PHY_CTRL_MIIM_BCAST, 0)) != RT_ERR_OK)
+        {
+            RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826x patch wait disable broadcast failed! 0x%X\n", unit, p, ret);
+            return ret;
+        }
+
+        HWP_PORT_TRAVS_EXCEPT_CPU(unit, p)
+        {
+            if (HWP_PHY_BASE_MACID(unit, p) == HWP_PHY_BASE_MACID(unit, port))
+            {
+                WAIT_COMPLETE(PHY_PATCH_WAIT_TIMEOUT)
+                {
+                    if ((ret = phy_common_general_reg_mmd_get(unit, p, mmdAddr, mmdReg, &rData)) != RT_ERR_OK)
+                    {
+                        return ret;
+                    }
+                    ++cnt;
+
+                    if ((rData & mask) == data)
+                        break;
+                    //osal_time_udelay(10);
+                }
+
+                if (WAIT_COMPLETE_IS_TIMEOUT())
+                {
+                    RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826x patch wait[%u,0x%X,0x%X,0x%X]:0x%X cnt:%u\n", unit, p, mmdAddr, mmdReg, data, mask, rData, cnt);
+                    return RT_ERR_TIMEOUT;
+                }
+            }
+        }
+
+        osal_time_mdelay(1);
+        //for port in same PHY, set mdio broadcast ENABLE
+        HWP_PORT_TRAVS_EXCEPT_CPU(unit, p)
+        {
+            if (HWP_PHY_BASE_MACID(unit, p) == HWP_PHY_BASE_MACID(unit, port))
+            {
+                if ((ret = phy_826xb_ctrl_set(unit, p, RTK_PHY_CTRL_MIIM_BCAST_PHYAD, (uint32)bcast_phyad)) != RT_ERR_OK)
+                {
+                    RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826XB patch wait set broadcast PHYAD failed! 0x%X\n", unit, p, ret);
+                    return ret;
+                }
+
+                if ((ret = phy_826xb_ctrl_set(unit, p, RTK_PHY_CTRL_MIIM_BCAST, 1)) != RT_ERR_OK)
+                {
+                    RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826XB patch wait enable broadcast failed! 0x%X\n", unit, p, ret);
+                    return ret;
+                }
+            }
+        }
+    }
+    else
+    {
+        WAIT_COMPLETE(PHY_PATCH_WAIT_TIMEOUT)
+        {
+            if ((ret = phy_common_general_reg_mmd_get(unit, port, mmdAddr, mmdReg, &rData)) != RT_ERR_OK)
+                return ret;
+
+            ++cnt;
+            if ((rData & mask) == data)
+                break;
+
+            osal_time_mdelay(1);
+        }
+
+        if (WAIT_COMPLETE_IS_TIMEOUT())
+        {
+            RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826XB patch wait[%u,0x%X,0x%X,0x%X]:0x%X cnt:%u\n", unit, port, mmdAddr, mmdReg, data, mask, rData, cnt);
+            return RT_ERR_TIMEOUT;
+        }
+    }
+
+    return RT_ERR_OK;
+}
+
+int32
+_phy_rtl826xb_patch_wait_not_equal(uint32 unit, rtk_port_t port, uint32 mmdAddr, uint32 mmdReg, uint32 data, uint32 mask, uint8 patch_mode)
+{
+    int32  ret = 0;
+    uint32 rData = 0;
+    uint32 cnt = 0;
+    WAIT_COMPLETE_VAR()
+
+    rtk_port_t  p = 0;
+    uint8  smiBus = HWP_PORT_SMI(unit, port);
+    uint32 phyChip = HWP_PHY_MODEL_BY_PORT(unit, port);
+    uint8  bcast_phyad = HWP_PHY_ADDR(unit, port);
+
+    if (patch_mode == PHY_PATCH_MODE_BCAST_BUS)
+    {
+        if ((ret = phy_826xb_ctrl_set(unit, port, RTK_PHY_CTRL_MIIM_BCAST, 0)) != RT_ERR_OK)
+        {
+            RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826XB patch wait disable broadcast failed! 0x%X\n", unit, p, ret);
+            return ret;
+        }
+
+        HWP_PORT_TRAVS_EXCEPT_CPU(unit, p)
+        {
+            if ((HWP_PORT_SMI(unit, p) == smiBus) && (HWP_PHY_MODEL_BY_PORT(unit, p) == phyChip))
+            {
+                WAIT_COMPLETE(PHY_PATCH_WAIT_TIMEOUT)
+                {
+                    if ((ret = phy_common_general_reg_mmd_get(unit, p, mmdAddr, mmdReg, &rData)) != RT_ERR_OK)
+                    {
+                        return ret;
+                    }
+                    ++cnt;
+
+                    if ((rData & mask) != data)
+                        break;
+
+                    //osal_time_udelay(10);
+                }
+                if (WAIT_COMPLETE_IS_TIMEOUT())
+                {
+                    RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826XB patch wait[%u,0x%X,0x%X,0x%X]:0x%X cnt:%u\n", unit, p, mmdAddr, mmdReg, data, mask, rData, cnt);
+                    return RT_ERR_TIMEOUT;
+                }
+            }
+        }
+
+        osal_time_mdelay(1);
+        //for port in same SMI bus, set mdio broadcast ENABLE
+        HWP_PORT_TRAVS_EXCEPT_CPU(unit, p)
+        {
+            if ((HWP_PORT_SMI(unit, p) == smiBus) && (HWP_PHY_MODEL_BY_PORT(unit, p) == phyChip))
+            {
+                if ((ret = phy_826xb_ctrl_set(unit, p, RTK_PHY_CTRL_MIIM_BCAST_PHYAD, (uint32)bcast_phyad)) != RT_ERR_OK)
+                {
+                    RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826XB patch wait set broadcast PHYAD failed! 0x%X\n", unit, p, ret);
+                    return ret;
+                }
+
+                if ((ret = phy_826xb_ctrl_set(unit, p, RTK_PHY_CTRL_MIIM_BCAST, 1)) != RT_ERR_OK)
+                {
+                    RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826XB patch wait enable broadcast failed! 0x%X\n", unit, p, ret);
+                    return ret;
+                }
+            }
+        }
+    }
+    else if (patch_mode == PHY_PATCH_MODE_BCAST)
+    {
+        if ((ret = phy_826xb_ctrl_set(unit, port, RTK_PHY_CTRL_MIIM_BCAST, 0)) != RT_ERR_OK)
+        {
+            RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826x patch wait disable broadcast failed! 0x%X\n", unit, p, ret);
+            return ret;
+        }
+
+        HWP_PORT_TRAVS_EXCEPT_CPU(unit, p)
+        {
+            if (HWP_PHY_BASE_MACID(unit, p) == HWP_PHY_BASE_MACID(unit, port))
+            {
+                WAIT_COMPLETE(PHY_PATCH_WAIT_TIMEOUT)
+                {
+                    if ((ret = phy_common_general_reg_mmd_get(unit, p, mmdAddr, mmdReg, &rData)) != RT_ERR_OK)
+                    {
+                        return ret;
+                    }
+                    ++cnt;
+
+                    if (((rData & mask) != data))
+                        break;
+
+                    //osal_time_udelay(10);
+                }
+
+                if (WAIT_COMPLETE_IS_TIMEOUT())
+                {
+                    RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826XB patch wait[%u,0x%X,0x%X,0x%X]:0x%X cnt:%u\n", unit, p, mmdAddr, mmdReg, data, mask, rData, cnt);
+                    return RT_ERR_TIMEOUT;
+                }
+            }
+        }
+
+        osal_time_mdelay(1);
+        //for port in same PHY, set mdio broadcast ENABLE
+        HWP_PORT_TRAVS_EXCEPT_CPU(unit, p)
+        {
+            if (HWP_PHY_BASE_MACID(unit, p) == HWP_PHY_BASE_MACID(unit, port))
+            {
+                if ((ret = phy_826xb_ctrl_set(unit, p, RTK_PHY_CTRL_MIIM_BCAST_PHYAD, (uint32)bcast_phyad)) != RT_ERR_OK)
+                {
+                    RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826XB patch wait set broadcast PHYAD failed! 0x%X\n", unit, p, ret);
+                    return ret;
+                }
+
+                if ((ret = phy_826xb_ctrl_set(unit, p, RTK_PHY_CTRL_MIIM_BCAST, 1)) != RT_ERR_OK)
+                {
+                    RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826XB patch wait enable broadcast failed! 0x%X\n", unit, p, ret);
+                    return ret;
+                }
+            }
+        }
+    }
+    else
+    {
+        WAIT_COMPLETE(PHY_PATCH_WAIT_TIMEOUT)
+        {
+            if ((ret = phy_common_general_reg_mmd_get(unit, port, mmdAddr, mmdReg, &rData)) != RT_ERR_OK)
+                return ret;
+
+            ++cnt;
+            if ((rData & mask) != data)
+                break;
+
+            osal_time_mdelay(1);
+        }
+        if (WAIT_COMPLETE_IS_TIMEOUT())
+        {
+            RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u 826xb patch wait[%u,0x%X,0x%X,0x%X]:0x%X cnt:%u\n", unit, port, mmdAddr, mmdReg, data, mask, rData, cnt);
+            return RT_ERR_TIMEOUT;
+        }
+
+    }
+
+    return RT_ERR_OK;
+}
+
+int32
+_phy_rtl826xb_patch_top_get(uint32 unit, rtk_port_t port, uint32 topPage, uint32 topReg, uint32 *pData)
+{
+    int32  ret = 0;
+    uint32 rData = 0;
+    uint32 topAddr = (topPage * 8) + (topReg - 16);
+
+    if ((ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_VEND1, topAddr, &rData)) != RT_ERR_OK)
+        return ret;
+    *pData = rData;
+    return RT_ERR_OK;
+}
+
+int32
+_phy_rtl826xb_patch_top_set(uint32 unit, rtk_port_t port, uint32 topPage, uint32 topReg, uint32 wData)
+{
+    int32  ret = 0;
+    uint32 topAddr = (topPage * 8) + (topReg - 16);
+    if ((ret = phy_common_general_reg_mmd_set(unit, port, PHY_MMD_VEND1, topAddr, wData)) != RT_ERR_OK)
+        return ret;
+    return RT_ERR_OK;
+}
+
+int32
+_phy_rtl826xb_patch_sds_get(uint32 unit, rtk_port_t port, uint32 sdsPage, uint32 sdsReg, uint32 *pData)
+{
+    int32  ret = 0;
+    uint32 rData = 0;
+    uint32 sdsAddr = 0x8000 + (sdsReg << 6) + sdsPage;
+
+    if ((ret = _phy_rtl826xb_patch_top_set(unit, port, 40, 19, sdsAddr)) != RT_ERR_OK)
+        return ret;
+    if ((ret = _phy_rtl826xb_patch_top_get(unit, port, 40, 18, &rData)) != RT_ERR_OK)
+        return ret;
+    *pData = rData;
+    return _phy_rtl826xb_patch_wait(unit, port, PHY_MMD_VEND1, 0x143, 0, BIT_15, PHY_PATCH_MODE_NORMAL);
+}
+
+int32
+_phy_rtl826xb_patch_sds_set(uint32 unit, rtk_port_t port, uint32 sdsPage, uint32 sdsReg, uint32 wData, uint8 patch_mode)
+{
+    int32  ret = 0;
+    uint32 sdsAddr = 0x8800 + (sdsReg << 6) + sdsPage;
+
+    if ((ret = _phy_rtl826xb_patch_top_set(unit, port, 40, 17, wData)) != RT_ERR_OK)
+        return ret;
+    if ((ret = _phy_rtl826xb_patch_top_set(unit, port, 40, 19, sdsAddr)) != RT_ERR_OK)
+        return ret;
+    return _phy_rtl826xb_patch_wait(unit, port, PHY_MMD_VEND1, 0x143, 0, BIT_15, patch_mode);
+}
+
+static int32 _phy_rtl826xb_flow_r1(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode)
+{
+    int32 ret = RT_ERR_OK;
+    rt_phy_patch_db_t *pPatchDb = NULL;
+
+    PHYPATCH_DB_GET(unit, port, pPatchDb);
+
+    //PHYReg_bit w $PHYID 0xb82 16 4 4 0x1
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xb82, 16, 4, 4, 0x1, patch_mode), ret);
+    //PHYReg_bit w $PHYID 0xb82 16 4 4 0x1
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xb82, 16, 4, 4, 0x1, patch_mode), ret);
+
+    //set patch_rdy [PHYReg_bit r $PHYID 0xb80 16 6 6] ; Wait for patch ready = 1
+    RT_ERR_CHK(_phy_rtl826xb_patch_wait(unit, port, 31, _phy_rtl826xb_mmd_convert(0xb80, 16), BIT_6, BIT_6, patch_mode), ret);
+
+    //PHYReg w $PHYID 0xa43 27 $0x8023
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 27, 15, 0, 0x8023, patch_mode), ret);
+    //PHYReg w $PHYID 0xa43 28 $0x3802
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 28, 15, 0, 0x3802, patch_mode), ret);
+    //PHYReg w $PHYID 0xa43 27 0xB82E
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 27, 15, 0, 0xB82E, patch_mode), ret);
+    //PHYReg w $PHYID 0xa43 28 0x1
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 28, 15, 0, 0x1, patch_mode), ret);
+
+     return RT_ERR_OK;
+}
+
+static int32 _phy_rtl826xb_flow_r12(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode)
+{
+    int32 ret = RT_ERR_OK;
+    rt_phy_patch_db_t *pPatchDb = NULL;
+
+    PHYPATCH_DB_GET(unit, port, pPatchDb);
+
+    //PHYReg_bit w $PHYID 0xb82 16 4 4 0x1
+    //RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xb82, 16, 4, 4, 0x1, patch_mode), ret);
+    //PHYReg_bit w $PHYID 0xb82 16 4 4 0x1
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xb82, 16, 4, 4, 0x1, patch_mode), ret);
+
+    //set patch_rdy [PHYReg_bit r $PHYID 0xb80 16 6 6] ; Wait for patch ready = 1
+    RT_ERR_CHK(_phy_rtl826xb_patch_wait(unit, port, 31, _phy_rtl826xb_mmd_convert(0xb80, 16), BIT_6, BIT_6, patch_mode), ret);
+
+    //PHYReg w $PHYID 0xa43 27 $0x8023
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 27, 15, 0, 0x8023, patch_mode), ret);
+    //PHYReg w $PHYID 0xa43 28 $0x3800
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 28, 15, 0, 0x3800, patch_mode), ret);
+    //PHYReg w $PHYID 0xa43 27 0xB82E
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 27, 15, 0, 0xB82E, patch_mode), ret);
+    //PHYReg w $PHYID 0xa43 28 0x1
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 28, 15, 0, 0x1, patch_mode), ret);
+
+    return RT_ERR_OK;
+}
+
+
+static int32 _phy_rtl826xb_flow_r2(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode)
+{
+    int32 ret = RT_ERR_OK;
+    rt_phy_patch_db_t *pPatchDb = NULL;
+
+    PHYPATCH_DB_GET(unit, port, pPatchDb);
+
+    //PHYReg w $PHYID 0xa43 27 0x0000
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 27, 15, 0, 0x0000, patch_mode), ret);
+    //PHYReg w $PHYID 0xa43 28 0x0000
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 28, 15, 0, 0x0000, patch_mode), ret);
+    //PHYReg_bit w $PHYID 0xB82 23 0 0 0x0
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xB82, 23, 0, 0, 0x0, patch_mode), ret);
+    //PHYReg w $PHYID 0xa43 27 $0x8023
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 27, 15, 0, 0x8023, patch_mode), ret);
+    //PHYReg w $PHYID 0xa43 28 0x0000
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa43, 28, 15, 0, 0x0000, patch_mode), ret);
+
+    //PHYReg_bit w $PHYID 0xb82 16 4 4 0x0
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xb82, 16, 4, 4, 0x0, patch_mode), ret);
+    //set patch_rdy [PHYReg_bit r $PHYID 0xb80 16 6 6] ; Wait for patch ready != 1
+    RT_ERR_CHK( _phy_rtl826xb_patch_wait_not_equal(unit, port, 31, _phy_rtl826xb_mmd_convert(0xb80, 16), BIT_6, BIT_6, patch_mode), ret);
+
+    return RT_ERR_OK;
+}
+
+static int32 _phy_rtl826xb_flow_l1(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode)
+{
+    int32 ret = RT_ERR_OK;
+    rt_phy_patch_db_t *pPatchDb = NULL;
+
+    PHYPATCH_DB_GET(unit, port, pPatchDb);
+
+    //PHYReg_bit w $PHYID 0xa4a 16 10 10 0x1
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa4a, 16, 10, 10, 0x1, patch_mode), ret);
+    //PHYReg_bit w $PHYID 0xa4a 16 10 10 0x1
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa4a, 16, 10, 10, 0x1, patch_mode), ret);
+
+    //set pcs_state [PHYReg_bit r $PHYID 0xa60 16 7 0] ; Wait for pcs state = 1
+    RT_ERR_CHK( _phy_rtl826xb_patch_wait(unit, port, 31, _phy_rtl826xb_mmd_convert(0xa60, 16), 0x1, 0xFF, patch_mode), ret);
+
+    return RT_ERR_OK;
+}
+
+static int32 _phy_rtl826xb_flow_l2(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode)
+{
+    int32 ret = RT_ERR_OK;
+    rt_phy_patch_db_t *pPatchDb = NULL;
+
+    PHYPATCH_DB_GET(unit, port, pPatchDb);
+
+    //PHYReg_bit w $PHYID 0xa4a 16 10 10 0x0
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa4a, 16, 10, 10, 0x0, patch_mode), ret);
+
+    //set pcs_state [PHYReg_bit r $PHYID 0xa60 16 7 0] ; Wait for pcs state != 1
+    RT_ERR_CHK( _phy_rtl826xb_patch_wait_not_equal(unit, port, 31, _phy_rtl826xb_mmd_convert(0xa60, 16), 0x1, 0xFF, patch_mode), ret);
+
+     return RT_ERR_OK;
+}
+
+static int32 _phy_rtl826xb_flow_pi(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode)
+{
+    int32 ret = RT_ERR_OK;
+    rt_phy_patch_db_t *pPatchDb = NULL;
+    uint32 rData = 0, cnt = 0;
+
+    PHYPATCH_DB_GET(unit, port, pPatchDb);
+
+    _phy_rtl826xb_flow_l1(unit, port, portOffset, patch_mode);
+
+    //  PP_PHYReg_bit w $PHYID 0xbf86 9 9 0x1; #SS_EN_XG = 1
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 9, 9, 0x1, patch_mode), ret);
+    //   PP_PHYReg_bit w $PHYID 0xbf86 8 8 0x0;
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 8, 8, 0x0, patch_mode), ret);
+    //   PP_PHYReg_bit w $PHYID 0xbf86 7 7 0x1;
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 7, 7, 0x1, patch_mode), ret);
+    //   PP_PHYReg_bit w $PHYID 0xbf86 6 6 0x1;
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 6, 6, 0x1, patch_mode), ret);
+    //   PP_PHYReg_bit w $PHYID 0xbf86 5 5 0x1;
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 5, 5, 0x1, patch_mode), ret);
+    //   PP_PHYReg_bit w $PHYID 0xbf86 4 4 0x1;
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 4, 4, 0x1, patch_mode), ret);
+    //   PP_PHYReg_bit w $PHYID 0xbf86 6 6 0x0;
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 6, 6, 0x0, patch_mode), ret);
+    //   PP_PHYReg_bit w $PHYID 0xbf86 9 9 0x0;
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 9, 9, 0x0, patch_mode), ret);
+    //   PP_PHYReg_bit w $PHYID 0xbf86 7 7 0x0;
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 7, 7, 0x0, patch_mode), ret);
+
+    //PP_PHYReg_bit r $PHYID 0xbc62 12 8
+    if ((ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_VEND2, 0xbc62, &rData)) != RT_ERR_OK)
+        return ret;
+    rData = REG32_FIELD_GET(rData, 8, 0x1F00);
+    for (cnt = 0; cnt <= rData; cnt++)
+    {
+        //PP_PHYReg_bit w $PHYID 0xbc62 12 8 $t
+        RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbc62, 12, 8, cnt, patch_mode), ret);
+    }
+
+    //   PP_PHYReg_bit w $PHYID 0xbc02 2 2 0x1
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbc02, 2, 2, 0x1, patch_mode), ret);
+    //   PP_PHYReg_bit w $PHYID 0xbc02 3 3 0x1
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbc02, 3, 3, 0x1, patch_mode), ret);
+    //   PP_PHYReg_bit w $PHYID 0xbf86 6 6 0x1
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 6, 6, 0x1, patch_mode), ret);
+    //   PP_PHYReg_bit w $PHYID 0xbf86 9 9 0x1
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 9, 9, 0x1, patch_mode), ret);
+    //   PP_PHYReg_bit w $PHYID 0xbf86 7 7 0x1
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbf86, 7, 7, 0x1, patch_mode), ret);
+    //   PP_PHYReg_bit w $PHYID 0xbc04 9 2 0xff
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 31, 0xbc04, 9, 2, 0xff, patch_mode), ret);
+
+    _phy_rtl826xb_flow_l2(unit, port, portOffset, patch_mode);
+    return RT_ERR_OK;
+}
+
+static int32 _phy_rtl826xb_flow_n01(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode)
+{
+    int32 ret = RT_ERR_OK;
+    rt_phy_patch_db_t *pPatchDb = NULL;
+
+    PHYPATCH_DB_GET(unit, port, pPatchDb);
+
+    //PHYReg_bit w $PHYID 0xa01 21 15 0 0x1
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 21, 15, 0, 0x1, patch_mode), ret);
+    //PHYReg_bit w $PHYID 0xa01 19 15 0 0x0000
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 19, 15, 0, 0x0000, patch_mode), ret);
+    //# PHYReg_bit w $PHYID 0xa01 17 15 0 0x0000
+    //RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 17, 15, 0, 0x0000, patch_mode), ret);
+
+    return RT_ERR_OK;
+}
+
+static int32 _phy_rtl826xb_flow_n02(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode)
+{
+    int32 ret = RT_ERR_OK;
+    rt_phy_patch_db_t *pPatchDb = NULL;
+
+    PHYPATCH_DB_GET(unit, port, pPatchDb);
+
+    //PHYReg_bit w $PHYID 0xa01 21 15 0 0x0
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 21, 15, 0, 0x0, patch_mode), ret);
+    //PHYReg_bit w $PHYID 0xa01 19 15 0 0x0000
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 19, 15, 0, 0x0000, patch_mode), ret);
+    //PHYReg_bit w $PHYID 0xa01 17 15 0 0x0000
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 17, 15, 0, 0x0000, patch_mode), ret);
+    return RT_ERR_OK;
+}
+
+static int32 _phy_rtl826xb_flow_n11(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode)
+{
+    int32 ret = RT_ERR_OK;
+    rt_phy_patch_db_t *pPatchDb = NULL;
+
+    PHYPATCH_DB_GET(unit, port, pPatchDb);
+
+    //PHYReg_bit w $PHYID 0xa01 21 15 0 0x1
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 21, 15, 0, 0x1, patch_mode), ret);
+    //PHYReg_bit w $PHYID 0xa01 19 15 0 0x0010
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 19, 15, 0, 0x0010, patch_mode), ret);
+    //# PHYReg_bit w $PHYID 0xa01 17 15 0 0x0000
+    //RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 17, 15, 0, 0x0000, patch_mode), ret);
+
+    return RT_ERR_OK;
+}
+
+static int32 _phy_rtl826xb_flow_n12(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode)
+{
+    int32 ret = RT_ERR_OK;
+    rt_phy_patch_db_t *pPatchDb = NULL;
+
+    PHYPATCH_DB_GET(unit, port, pPatchDb);
+
+    //PHYReg_bit w $PHYID 0xa01 21 15 0 0x0
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 21, 15, 0, 0x0, patch_mode), ret);
+    //PHYReg_bit w $PHYID 0xa01 19 15 0 0x0010
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 19, 15, 0, 0x0010, patch_mode), ret);
+    //PHYReg_bit w $PHYID 0xa01 17 15 0 0x0000
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 17, 15, 0, 0x0000, patch_mode), ret);
+
+    return RT_ERR_OK;
+}
+
+static int32 _phy_rtl826xb_flow_n21(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode)
+{
+    int32 ret = RT_ERR_OK;
+    rt_phy_patch_db_t *pPatchDb = NULL;
+
+    PHYPATCH_DB_GET(unit, port, pPatchDb);
+
+    //PHYReg_bit w $PHYID 0xa01 21 15 0 0x1
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 21, 15, 0, 0x1, patch_mode), ret);
+    //PHYReg_bit w $PHYID 0xa01 19 15 0 0x0020
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 19, 15, 0, 0x0020, patch_mode), ret);
+    //# PHYReg_bit w $PHYID 0xa01 17 15 0 0x0000
+    //RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 17, 15, 0, 0x0000, patch_mode), ret);
+
+    return RT_ERR_OK;
+}
+
+static int32 _phy_rtl826xb_flow_n22(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode)
+{
+    int32 ret = RT_ERR_OK;
+    rt_phy_patch_db_t *pPatchDb = NULL;
+
+    PHYPATCH_DB_GET(unit, port, pPatchDb);
+
+    //PHYReg_bit w $PHYID 0xa01 21 15 0 0x0
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 21, 15, 0, 0x0, patch_mode), ret);
+    //PHYReg_bit w $PHYID 0xa01 19 15 0 0x0020
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 19, 15, 0, 0x0020, patch_mode), ret);
+    //PHYReg_bit w $PHYID 0xa01 17 15 0 0x0000
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHY, 0xFF, 0xa01, 17, 15, 0, 0x0000, patch_mode), ret);
+
+    return RT_ERR_OK;
+}
+
+static int32 _phy_rtl826xb_flow_s(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode)
+{
+    int32 ret = RT_ERR_OK;
+    rt_phy_patch_db_t *pPatchDb = NULL;
+
+    if (PHYPATCH_IS_RTKSDS(unit))
+    {
+        PHYPATCH_DB_GET(unit, port, pPatchDb);
+
+        RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PSDS0, 0xff, 0x07, 0x10, 15, 0, 0x80aa, patch_mode), ret);
+        RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PSDS0, 0xff, 0x06, 0x12, 15, 0, 0x5078, patch_mode), ret);
+    }
+
+    return RT_ERR_OK;
+}
+
+static int32 _phy_rtl826xb_flow_cmpstart(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode)
+{
+    int32 ret = RT_ERR_OK;
+    rt_phy_patch_db_t *pPatchDb = NULL;
+
+    PHYPATCH_DB_GET(unit, port, pPatchDb);
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 1, 0, 11, 11, 0x0, patch_mode), ret);
+    return RT_ERR_OK;
+}
+
+static int32 _phy_rtl826xb_flow_cmpend(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_mode)
+{
+    int32 ret = RT_ERR_OK;
+    rt_phy_patch_db_t *pPatchDb = NULL;
+
+    PHYPATCH_DB_GET(unit, port, pPatchDb);
+    RT_ERR_CHK(phy_patch_op(pPatchDb, unit, port, portOffset, RTK_PATCH_OP_PHYOCP, 0xFF, 1, 0, 11, 11, 0x1, patch_mode), ret);
+    return RT_ERR_OK;
+}
+
+int32 phy_rtl826xb_patch_op(uint32 unit, rtk_port_t port, uint8 portOffset, rtk_hwpatch_t *pPatch_data, uint8 patch_mode)
+{
+    int32 ret = RT_ERR_OK;
+    uint32 rData = 0, wData = 0;
+    uint16 reg = 0;
+    uint8 patch_op = 0;
+    uint32 mask = 0;
+
+    if ((pPatch_data->portmask & (1 << portOffset)) == 0)
+    {
+        return RT_ERR_ABORT;
+    }
+    mask = UINT32_BITS_MASK(pPatch_data->msb, pPatch_data->lsb);
+    patch_op = phy_patch_op_translate(patch_mode, pPatch_data->patch_op, pPatch_data->compare_op);
+
+    #if 0
+    osal_printf("[%s,%d]u%up%u, patch_mode:%u/patch_op:%u/compare_op:%u => op: %u\n", __FUNCTION__, __LINE__, unit, port,
+                           patch_mode, pPatch_data->patch_op, pPatch_data->compare_op,
+                           patch_op);
+    #endif
+
+    switch (patch_op)
+    {
+        case RTK_PATCH_OP_PHY:
+            reg = _phy_rtl826xb_mmd_convert(pPatch_data->pagemmd, pPatch_data->addr);
+            if ((pPatch_data->msb != 15) || (pPatch_data->lsb != 0))
+            {
+                RT_ERR_CHK(phy_common_general_reg_mmd_get(unit, port, 31, reg, &rData), ret);
+            }
+            wData = REG32_FIELD_SET(rData, pPatch_data->data, pPatch_data->lsb, mask);
+            RT_ERR_CHK(phy_common_general_reg_mmd_set(unit, port, 31, reg, wData), ret);
+            break;
+        case RTK_PATCH_OP_CMP_PHY:
+            reg = _phy_rtl826xb_mmd_convert(pPatch_data->pagemmd, pPatch_data->addr);
+            RT_ERR_CHK(phy_common_general_reg_mmd_get(unit, port, 31, reg, &rData), ret);
+            PHYPATCH_COMPARE(pPatch_data->pagemmd, pPatch_data->addr, pPatch_data->msb, pPatch_data->lsb, pPatch_data->data, rData, mask);
+            break;
+        case RTK_PATCH_OP_CMP_SRAM_PHY:
+            reg = _phy_rtl826xb_mmd_convert(pPatch_data->sram_p, pPatch_data->sram_rw);
+            RT_ERR_CHK(phy_common_general_reg_mmd_set(unit, port, 31, reg, pPatch_data->sram_a), ret);
+            reg = _phy_rtl826xb_mmd_convert(pPatch_data->sram_p, pPatch_data->sram_rr);
+            RT_ERR_CHK(phy_common_general_reg_mmd_get(unit, port, 31, reg, &rData), ret);
+            PHYPATCH_COMPARE(pPatch_data->pagemmd, pPatch_data->addr, pPatch_data->msb, pPatch_data->lsb, pPatch_data->data, rData, mask);
+            break;
+
+        case RTK_PATCH_OP_PHYOCP:
+            if ((pPatch_data->msb != 15) || (pPatch_data->lsb != 0))
+            {
+                RT_ERR_CHK(phy_common_general_reg_mmd_get(unit, port, 31, pPatch_data->addr, &rData), ret);
+            }
+            wData = REG32_FIELD_SET(rData, pPatch_data->data, pPatch_data->lsb, mask);
+            RT_ERR_CHK(phy_common_general_reg_mmd_set(unit, port, 31, pPatch_data->addr, wData), ret);
+            break;
+        case RTK_PATCH_OP_CMP_PHYOCP:
+            RT_ERR_CHK(phy_common_general_reg_mmd_get(unit, port, 31, pPatch_data->addr, &rData), ret);
+            PHYPATCH_COMPARE(pPatch_data->pagemmd, pPatch_data->addr, pPatch_data->msb, pPatch_data->lsb, pPatch_data->data, rData, mask);
+            break;
+        case RTK_PATCH_OP_CMP_SRAM_PHYOCP:
+            RT_ERR_CHK(phy_common_general_reg_mmd_set(unit, port, 31, pPatch_data->sram_rw, pPatch_data->sram_a), ret);
+            RT_ERR_CHK(phy_common_general_reg_mmd_get(unit, port, 31, pPatch_data->sram_rr, &rData), ret);
+            PHYPATCH_COMPARE(pPatch_data->pagemmd, pPatch_data->addr, pPatch_data->msb, pPatch_data->lsb, pPatch_data->data, rData, mask);
+            break;
+
+        case RTK_PATCH_OP_TOP:
+            if ((pPatch_data->msb != 15) || (pPatch_data->lsb != 0))
+            {
+                RT_ERR_CHK(_phy_rtl826xb_patch_top_get(unit, port, pPatch_data->pagemmd, pPatch_data->addr, &rData), ret);
+            }
+            wData = REG32_FIELD_SET(rData, pPatch_data->data, pPatch_data->lsb, mask);
+            RT_ERR_CHK(_phy_rtl826xb_patch_top_set(unit, port, pPatch_data->pagemmd, pPatch_data->addr, wData), ret);
+            break;
+        case RTK_PATCH_OP_CMP_TOP:
+            RT_ERR_CHK(_phy_rtl826xb_patch_top_get(unit, port, pPatch_data->pagemmd, pPatch_data->addr, &rData), ret);
+            PHYPATCH_COMPARE(pPatch_data->pagemmd, pPatch_data->addr, pPatch_data->msb, pPatch_data->lsb, pPatch_data->data, rData, mask);
+            break;
+        case RTK_PATCH_OP_CMP_SRAM_TOP:
+            RT_ERR_CHK(_phy_rtl826xb_patch_top_set(unit, port, pPatch_data->sram_p, pPatch_data->sram_rw, pPatch_data->sram_a), ret);
+            RT_ERR_CHK(_phy_rtl826xb_patch_top_get(unit, port, pPatch_data->sram_p, pPatch_data->sram_rr, &rData), ret);
+            PHYPATCH_COMPARE(pPatch_data->pagemmd, pPatch_data->addr, pPatch_data->msb, pPatch_data->lsb, pPatch_data->data, rData, mask);
+            break;
+
+        case RTK_PATCH_OP_PSDS0:
+            if ((pPatch_data->msb != 15) || (pPatch_data->lsb != 0))
+            {
+                RT_ERR_CHK(_phy_rtl826xb_patch_sds_get(unit, port, pPatch_data->pagemmd, pPatch_data->addr, &rData), ret);
+            }
+            wData = REG32_FIELD_SET(rData, pPatch_data->data, pPatch_data->lsb, mask);
+            RT_ERR_CHK(_phy_rtl826xb_patch_sds_set(unit, port, pPatch_data->pagemmd, pPatch_data->addr, wData, patch_mode), ret);
+            break;
+        case RTK_PATCH_OP_CMP_PSDS0:
+            RT_ERR_CHK(_phy_rtl826xb_patch_sds_get(unit, port, pPatch_data->pagemmd, pPatch_data->addr, &rData), ret);
+            PHYPATCH_COMPARE(pPatch_data->pagemmd, pPatch_data->addr, pPatch_data->msb, pPatch_data->lsb, pPatch_data->data, rData, mask);
+            break;
+        case RTK_PATCH_OP_CMP_SRAM_PSDS0:
+            RT_ERR_CHK(_phy_rtl826xb_patch_sds_set(unit, port, pPatch_data->sram_p, pPatch_data->sram_rw, pPatch_data->sram_a, patch_mode), ret);
+            RT_ERR_CHK(_phy_rtl826xb_patch_sds_get(unit, port, pPatch_data->sram_p, pPatch_data->sram_rr, &rData), ret);
+            PHYPATCH_COMPARE(pPatch_data->pagemmd, pPatch_data->addr, pPatch_data->msb, pPatch_data->lsb, pPatch_data->data, rData, mask);
+            break;
+
+        case RTK_PATCH_OP_DELAY_MS:
+            osal_time_mdelay(pPatch_data->data);
+            break;
+
+        case RTK_PATCH_OP_SKIP:
+            return RT_ERR_ABORT;
+
+        default:
+            RT_LOG(LOG_MAJOR_ERR, (MOD_HAL | MOD_PHY), "U%u P%u patch_op:%u not implemented yet!\n", unit, port, pPatch_data->patch_op);
+            return RT_ERR_DRIVER_NOT_SUPPORTED;
+    }
+
+    return ret;
+}
+
+int32 phy_rtl826xb_patch_flow(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_flow, uint8 patch_mode)
+{
+    int32 ret = RT_ERR_OK;
+
+    RT_LOG(LOG_INFO, (MOD_HAL | MOD_PHY), "[%s]U%u,P%u,flow%u\n", __FUNCTION__, unit, port, (patch_flow - PHY_PATCH_TYPE_END));
+    switch (patch_flow)
+    {
+        case RTK_PATCH_TYPE_FLOW(0):
+            RT_ERR_CHK(_phy_rtl826xb_flow_r1(unit, port, portOffset, patch_mode), ret);
+            break;
+        case RTK_PATCH_TYPE_FLOW(1):
+            RT_ERR_CHK(_phy_rtl826xb_flow_r2(unit, port, portOffset, patch_mode), ret);
+            break;
+
+        case RTK_PATCH_TYPE_FLOW(2):
+            RT_ERR_CHK(_phy_rtl826xb_flow_l1(unit, port, portOffset, patch_mode), ret);
+            break;
+        case RTK_PATCH_TYPE_FLOW(3):
+            RT_ERR_CHK(_phy_rtl826xb_flow_l2(unit, port, portOffset, patch_mode), ret);
+            break;
+
+        case RTK_PATCH_TYPE_FLOW(4):
+            RT_ERR_CHK(_phy_rtl826xb_flow_n01(unit, port, portOffset, patch_mode), ret);
+            break;
+        case RTK_PATCH_TYPE_FLOW(5):
+            RT_ERR_CHK(_phy_rtl826xb_flow_n02(unit, port, portOffset, patch_mode), ret);
+            break;
+
+        case RTK_PATCH_TYPE_FLOW(6):
+            RT_ERR_CHK(_phy_rtl826xb_flow_n11(unit, port, portOffset, patch_mode), ret);
+            break;
+        case RTK_PATCH_TYPE_FLOW(7):
+            RT_ERR_CHK(_phy_rtl826xb_flow_n12(unit, port, portOffset, patch_mode), ret);
+            break;
+
+        case RTK_PATCH_TYPE_FLOW(8):
+            RT_ERR_CHK(_phy_rtl826xb_flow_n21(unit, port, portOffset, patch_mode), ret);
+            break;
+        case RTK_PATCH_TYPE_FLOW(9):
+            RT_ERR_CHK(_phy_rtl826xb_flow_n22(unit, port, portOffset, patch_mode), ret);
+            break;
+
+        case RTK_PATCH_TYPE_FLOW(10):
+            RT_ERR_CHK(_phy_rtl826xb_flow_s(unit, port, portOffset, patch_mode), ret);
+            break;
+
+        case RTK_PATCH_TYPE_FLOW(11):
+            RT_ERR_CHK(_phy_rtl826xb_flow_pi(unit, port, portOffset, patch_mode), ret);
+            break;
+        case RTK_PATCH_TYPE_FLOW(12):
+            RT_ERR_CHK(_phy_rtl826xb_flow_r12(unit, port, portOffset, patch_mode), ret);
+            break;
+
+        case RTK_PATCH_TYPE_FLOW(13):
+            RT_ERR_CHK(_phy_rtl826xb_flow_cmpstart(unit, port, portOffset, patch_mode), ret);
+            break;
+        case RTK_PATCH_TYPE_FLOW(14):
+            RT_ERR_CHK(_phy_rtl826xb_flow_cmpend(unit, port, portOffset, patch_mode), ret);
+            break;
+
+        default:
+            return RT_ERR_INPUT;
+    }
+    return RT_ERR_OK;
+}
+
+int32 phy_rtl826xb_patch_db_init(uint32 unit, rtk_port_t port, rt_phy_patch_db_t **pPhy_patchDb)
+{
+    int32 ret = RT_ERR_OK;
+    rt_phy_patch_db_t *patch_db = NULL;
+    uint32 rData = 0;
+
+    patch_db = osal_alloc(sizeof(rt_phy_patch_db_t));
+    RT_PARAM_CHK(NULL == patch_db, RT_ERR_MEM_ALLOC);
+    osal_memset(patch_db, 0x0, sizeof(rt_phy_patch_db_t));
+
+    /* patch callback */
+    patch_db->fPatch_op = phy_rtl826xb_patch_op;
+    patch_db->fPatch_flow = phy_rtl826xb_patch_flow;
+
+    /* patch table */
+    RT_ERR_CHK(phy_common_general_reg_mmd_get(unit, port, 30, 0x104, &rData), ret);
+    if ((rData & 0xFFC0) == 0x1140) /* RTL8261BE */
+    {
+        /* patch */
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db,  0, RTK_PATCH_TYPE_FLOW(0), NULL);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db,  1, PHY_PATCH_TYPE_NCTL0, rtl8261n_c_nctl0_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db,  2, PHY_PATCH_TYPE_NCTL1, rtl8261n_c_nctl1_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db,  3, PHY_PATCH_TYPE_NCTL2, rtl8261n_c_nctl2_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db,  4, PHY_PATCH_TYPE_UC2, rtl8261n_c_uc2_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db,  5, PHY_PATCH_TYPE_UC, rtl8261n_c_uc_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db,  6, PHY_PATCH_TYPE_DATARAM, rtl8261n_c_dataram_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db,  7, RTK_PATCH_TYPE_FLOW(1), NULL);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db,  8, RTK_PATCH_TYPE_FLOW(2), NULL);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db,  9, PHY_PATCH_TYPE_ALGXG, rtl8261n_c_algxg_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 10, PHY_PATCH_TYPE_ALG1G, rtl8261n_c_alg_giga_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 11, PHY_PATCH_TYPE_NORMAL, rtl8261n_c_normal_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 12, PHY_PATCH_TYPE_TOP, rtl8261n_c_top_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 13, PHY_PATCH_TYPE_SDS, rtl8261n_c_sds_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 14, PHY_PATCH_TYPE_AFE, rtl8261n_c_afe_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 15, PHY_PATCH_TYPE_RTCT, rtl8261n_c_rtct_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 16, RTK_PATCH_TYPE_FLOW(3), NULL);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 17, RTK_PATCH_TYPE_FLOW(10), NULL);
+
+        /* compare */
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db,  0, RTK_PATCH_TYPE_FLOW(13), NULL);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db,  1, PHY_PATCH_TYPE_TOP, rtl8261n_c_top_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db,  2, PHY_PATCH_TYPE_SDS, rtl8261n_c_sds_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db,  3, PHY_PATCH_TYPE_AFE, rtl8261n_c_afe_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db,  4, RTK_PATCH_TYPE_FLOW(4), NULL);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db,  5, PHY_PATCH_TYPE_NCTL0, rtl8261n_c_nctl0_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db,  6, RTK_PATCH_TYPE_FLOW(5), NULL);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db,  7, RTK_PATCH_TYPE_FLOW(6), NULL);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db,  8, PHY_PATCH_TYPE_NCTL1, rtl8261n_c_nctl1_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db,  9, RTK_PATCH_TYPE_FLOW(7), NULL);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 10, RTK_PATCH_TYPE_FLOW(8), NULL);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 11, PHY_PATCH_TYPE_NCTL2, rtl8261n_c_nctl2_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 12, RTK_PATCH_TYPE_FLOW(9), NULL);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 13, PHY_PATCH_TYPE_UC, rtl8261n_c_uc_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 14, PHY_PATCH_TYPE_UC2, rtl8261n_c_uc2_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 15, RTK_PATCH_TYPE_FLOW(0), NULL);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 16, PHY_PATCH_TYPE_DATARAM, rtl8261n_c_dataram_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 17, RTK_PATCH_TYPE_FLOW(1), NULL);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 18, PHY_PATCH_TYPE_ALGXG, rtl8261n_c_algxg_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 19, PHY_PATCH_TYPE_ALG1G, rtl8261n_c_alg_giga_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 20, PHY_PATCH_TYPE_NORMAL, rtl8261n_c_normal_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 21, PHY_PATCH_TYPE_RTCT, rtl8261n_c_rtct_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 22, RTK_PATCH_TYPE_FLOW(14), NULL);
+    }
+    else if ((rData & 0xF) == 0x0)
+    {
+        /* patch */
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db,  0, RTK_PATCH_TYPE_FLOW(12), NULL);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db,  1, PHY_PATCH_TYPE_NCTL0, rtl8264b_nctl0_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db,  2, PHY_PATCH_TYPE_NCTL1, rtl8264b_nctl1_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db,  3, PHY_PATCH_TYPE_NCTL2, rtl8264b_nctl2_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db,  4, PHY_PATCH_TYPE_UC2, rtl8264b_uc2_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db,  5, PHY_PATCH_TYPE_UC, rtl8264b_uc_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db,  6, PHY_PATCH_TYPE_DATARAM, rtl8264b_dataram_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db,  7, RTK_PATCH_TYPE_FLOW(1), NULL);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db,  8, RTK_PATCH_TYPE_FLOW(2), NULL);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db,  9, PHY_PATCH_TYPE_ALGXG, rtl8264b_algxg_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 10, PHY_PATCH_TYPE_ALG1G, rtl8264b_alg_giga_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 11, PHY_PATCH_TYPE_NORMAL, rtl8264b_normal_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 12, PHY_PATCH_TYPE_TOP, rtl8264b_top_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 13, PHY_PATCH_TYPE_SDS, rtl8264b_sds_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 14, PHY_PATCH_TYPE_AFE, rtl8264b_afe_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 15, PHY_PATCH_TYPE_RTCT, rtl8264b_rtct_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 16, RTK_PATCH_TYPE_FLOW(3), NULL);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 17, RTK_PATCH_TYPE_FLOW(11), NULL);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 18, RTK_PATCH_TYPE_FLOW(10), NULL);
+
+        /* compare */
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db,  0, RTK_PATCH_TYPE_FLOW(13), NULL);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db,  1, PHY_PATCH_TYPE_TOP, rtl8264b_top_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db,  2, PHY_PATCH_TYPE_SDS, rtl8264b_sds_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db,  3, PHY_PATCH_TYPE_AFE, rtl8264b_afe_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db,  4, RTK_PATCH_TYPE_FLOW(4), NULL);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db,  5, PHY_PATCH_TYPE_NCTL0, rtl8264b_nctl0_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db,  6, RTK_PATCH_TYPE_FLOW(5), NULL);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db,  7, RTK_PATCH_TYPE_FLOW(6), NULL);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db,  8, PHY_PATCH_TYPE_NCTL1, rtl8264b_nctl1_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db,  9, RTK_PATCH_TYPE_FLOW(7), NULL);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 10, RTK_PATCH_TYPE_FLOW(8), NULL);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 11, PHY_PATCH_TYPE_NCTL2, rtl8264b_nctl2_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 12, RTK_PATCH_TYPE_FLOW(9), NULL);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 13, PHY_PATCH_TYPE_UC, rtl8264b_uc_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 14, PHY_PATCH_TYPE_UC2, rtl8264b_uc2_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 15, RTK_PATCH_TYPE_FLOW(12), NULL);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 16, PHY_PATCH_TYPE_DATARAM, rtl8264b_dataram_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 17, RTK_PATCH_TYPE_FLOW(1), NULL);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 18, PHY_PATCH_TYPE_ALGXG, rtl8264b_algxg_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 19, PHY_PATCH_TYPE_ALG1G, rtl8264b_alg_giga_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 20, PHY_PATCH_TYPE_NORMAL, rtl8264b_normal_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 21, PHY_PATCH_TYPE_RTCT, rtl8264b_rtct_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 22, RTK_PATCH_TYPE_FLOW(14), NULL);
+    }
+    else
+    {
+        /* patch */
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db,  0, RTK_PATCH_TYPE_FLOW(0), NULL);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db,  1, PHY_PATCH_TYPE_NCTL0, rtl8261n_c_nctl0_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db,  2, PHY_PATCH_TYPE_NCTL1, rtl8261n_c_nctl1_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db,  3, PHY_PATCH_TYPE_NCTL2, rtl8261n_c_nctl2_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db,  4, PHY_PATCH_TYPE_UC2, rtl8261n_c_uc2_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db,  5, PHY_PATCH_TYPE_UC, rtl8261n_c_uc_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db,  6, PHY_PATCH_TYPE_DATARAM, rtl8261n_c_dataram_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db,  7, RTK_PATCH_TYPE_FLOW(1), NULL);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db,  8, RTK_PATCH_TYPE_FLOW(2), NULL);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db,  9, PHY_PATCH_TYPE_ALGXG, rtl8261n_c_algxg_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 10, PHY_PATCH_TYPE_ALG1G, rtl8261n_c_alg_giga_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 11, PHY_PATCH_TYPE_NORMAL, rtl8261n_c_normal_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 12, PHY_PATCH_TYPE_TOP, rtl8261n_c_top_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 13, PHY_PATCH_TYPE_SDS, rtl8261n_c_sds_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 14, PHY_PATCH_TYPE_AFE, rtl8261n_c_afe_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 15, PHY_PATCH_TYPE_RTCT, rtl8261n_c_rtct_conf);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 16, RTK_PATCH_TYPE_FLOW(3), NULL);
+        PHYPATCH_SEQ_TABLE_ASSIGN(patch_db, 17, RTK_PATCH_TYPE_FLOW(10), NULL);
+
+        /* compare */
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db,  0, RTK_PATCH_TYPE_FLOW(13), NULL);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db,  1, PHY_PATCH_TYPE_TOP, rtl8261n_c_top_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db,  2, PHY_PATCH_TYPE_SDS, rtl8261n_c_sds_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db,  3, PHY_PATCH_TYPE_AFE, rtl8261n_c_afe_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db,  4, RTK_PATCH_TYPE_FLOW(4), NULL);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db,  5, PHY_PATCH_TYPE_NCTL0, rtl8261n_c_nctl0_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db,  6, RTK_PATCH_TYPE_FLOW(5), NULL);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db,  7, RTK_PATCH_TYPE_FLOW(6), NULL);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db,  8, PHY_PATCH_TYPE_NCTL1, rtl8261n_c_nctl1_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db,  9, RTK_PATCH_TYPE_FLOW(7), NULL);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 10, RTK_PATCH_TYPE_FLOW(8), NULL);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 11, PHY_PATCH_TYPE_NCTL2, rtl8261n_c_nctl2_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 12, RTK_PATCH_TYPE_FLOW(9), NULL);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 13, PHY_PATCH_TYPE_UC, rtl8261n_c_uc_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 14, PHY_PATCH_TYPE_UC2, rtl8261n_c_uc2_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 15, RTK_PATCH_TYPE_FLOW(0), NULL);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 16, PHY_PATCH_TYPE_DATARAM, rtl8261n_c_dataram_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 17, RTK_PATCH_TYPE_FLOW(1), NULL);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 18, PHY_PATCH_TYPE_ALGXG, rtl8261n_c_algxg_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 19, PHY_PATCH_TYPE_ALG1G, rtl8261n_c_alg_giga_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 20, PHY_PATCH_TYPE_NORMAL, rtl8261n_c_normal_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 21, PHY_PATCH_TYPE_RTCT, rtl8261n_c_rtct_conf);
+        PHYPATCH_CMP_TABLE_ASSIGN(patch_db, 22, RTK_PATCH_TYPE_FLOW(14), NULL);
+    }
+    *pPhy_patchDb = patch_db;
+    return ret;
+}
+
+/* Function Name:
+ *      phy_rtl826xb_patch
+ * Description:
+ *      apply initial patch data to PHY
+ * Input:
+ *      unit       - unit id
+ *      baseport   - base port id on the PHY chip
+ *      portOffset - the index offset base on baseport for the port to patch
+ * Output:
+ *      None
+ * Return:
+ *      RT_ERR_OK
+ *      RT_ERR_FAILED
+ *      RT_ERR_NOT_SUPPORTED
+ *      RT_ERR_ABORT
+ * Note:
+ *      None
+ */
+int32 phy_rtl826xb_patch(uint32 unit, rtk_port_t port, uint8 portOffset)
+{
+    return phy_patch( unit, port, portOffset, PHY_PATCH_MODE_NORMAL);
+}
+
+/* Function Name:
+ *      phy_rtl826xb_broadcast_patch
+ * Description:
+ *      apply patch data to PHY
+ * Input:
+ *      unit       - unit id
+ *      baseport   - base port id on the PHY chip
+ *      portOffset - the index offset base on baseport for the port to patch
+ *      perChip    - 1 for per-chip mode, 0 for per-bus mode
+ * Output:
+ *      None
+ * Return:
+ *      RT_ERR_OK
+ *      RT_ERR_FAILED
+ *      RT_ERR_NOT_SUPPORTED
+ *      RT_ERR_ABORT
+ * Note:
+ *      None
+ */
+int32 phy_rtl826xb_broadcast_patch(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 perChip)
+{
+    int32 ret = 0;
+    if (perChip == 0)
+    {
+        ret = phy_patch(unit, port, portOffset, PHY_PATCH_MODE_BCAST_BUS);
+    }
+    else
+    {
+        ret = phy_patch(unit, port, portOffset, PHY_PATCH_MODE_BCAST);
+    }
+    return ret;
+}
+
diff --git a/sources/rtk-gp3000/src/hal/phy/phy_rtl826xb_patch.h b/sources/rtk-gp3000/src/hal/phy/phy_rtl826xb_patch.h
new file mode 100644
index 00000000..c2311ef2
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/phy_rtl826xb_patch.h
@@ -0,0 +1,63 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
+ */
+
+#ifndef __HAL_PHY_PHY_RTL826XB_PATCH_H__
+#define __HAL_PHY_PHY_RTL826XB_PATCH_H__
+
+/*
+ * Include Files
+ */
+#if defined(RTK_PHYDRV_IN_LINUX)
+  #include "rtk_osal.h"
+  #include "rtk_phylib_def.h"
+#else
+  #include <common/rt_type.h>
+  #include <rtk/port.h>
+#endif
+
+/* Function Name:
+ *      phy_rtl826xb_patch
+ * Description:
+ *      apply patch data to PHY
+ * Input:
+ *      unit       - unit id
+ *      baseport   - base port id on the PHY chip
+ *      portOffset - the index offset base on baseport for the port to patch
+ * Output:
+ *      None
+ * Return:
+ *      RT_ERR_OK
+ *      RT_ERR_FAILED
+ *      RT_ERR_NOT_SUPPORTED
+ *      RT_ERR_ABORT
+ * Note:
+ *      None
+ */
+extern int32 phy_rtl826xb_patch(uint32 unit, rtk_port_t baseport, uint8 portOffset);
+
+/* Function Name:
+ *      phy_rtl826xb_broadcast_patch
+ * Description:
+ *      apply patch data to PHY
+ * Input:
+ *      unit       - unit id
+ *      baseport   - base port id on the PHY chip
+ *      portOffset - the index offset base on baseport for the port to patch
+ *      perChip    - 1 for per-chip mode, 0 for per-bus mode
+ * Output:
+ *      None
+ * Return:
+ *      RT_ERR_OK
+ *      RT_ERR_FAILED
+ *      RT_ERR_NOT_SUPPORTED
+ *      RT_ERR_ABORT
+ * Note:
+ *      None
+ */
+extern int32 phy_rtl826xb_broadcast_patch(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 perChip);
+
+extern int32 phy_rtl826xb_patch_db_init(uint32 unit, rtk_port_t port, rt_phy_patch_db_t **pPhy_patchDb);
+#endif /* __HAL_PHY_PHY_RTL826XB_PATCH_H__ */
diff --git a/sources/rtk-gp3000/src/hal/phy/rtk_macsec.c b/sources/rtk-gp3000/src/hal/phy/rtk_macsec.c
new file mode 100644
index 00000000..543129a0
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/rtk_macsec.c
@@ -0,0 +1,885 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
+ */
+
+#include <linux/version.h>
+#include <linux/phy.h>
+#include <crypto/aes.h>
+#include <net/macsec.h>
+#include "rtk_phylib_macsec.h"
+#include "rtk_phylib_rtl826xb.h"
+#include "rtk_phylib.h"
+#include "rtk_phy.h"
+
+static int rtk_macsec_del_txsa(struct macsec_context *ctx);
+static int rtk_macsec_del_rxsa(struct macsec_context *ctx);
+
+static int __rtk_macsec_clear_txsc(struct macsec_context *ctx, uint32 sc_id)
+{
+    int32 ret = 0;
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sc_del(ctx->phydev, RTK_MACSEC_DIR_EGRESS, sc_id));
+    return ret;
+}
+
+static int __rtk_macsec_clear_rxsc(struct macsec_context *ctx, uint32 sc_id)
+{
+    int32 ret = 0;
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sc_del(ctx->phydev, RTK_MACSEC_DIR_INGRESS, sc_id));
+    return ret;
+}
+
+static int rtk_macsec_dev_open(struct macsec_context *ctx)
+{
+  #if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0))
+    if (ctx->prepare)
+        return 0;
+  #endif
+
+    return rtk_phylib_macsec_enable_set(ctx->phydev, 1);
+}
+
+static int rtk_macsec_dev_stop(struct macsec_context *ctx)
+{
+  #if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0))
+    if (ctx->prepare)
+        return 0;
+  #endif
+
+    return rtk_phylib_macsec_enable_set(ctx->phydev, 0);
+}
+
+static int rtk_macsec_add_secy(struct macsec_context *ctx)
+{
+    int32 ret = 0;
+    struct rtk_phy_priv *priv = ctx->phydev->priv;
+    rtk_macsec_port_info_t *macsec_db = priv->macsec;
+
+  #if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0))
+    if (ctx->prepare)
+        return 0;
+  #endif
+
+    if(MACSEC_SC_IS_USED(macsec_db, RTK_MACSEC_DIR_EGRESS, 0))
+    {
+        PR_ERR("[%s]MACSEC_SC_IS_USED\n",__FUNCTION__);
+        return -EEXIST;
+    }
+
+    /* create TX SC */
+    {
+        uint32 sc_id = 0;
+        rtk_macsec_sc_t sc;
+        memset(&sc, 0x0, sizeof(rtk_macsec_sc_t));
+
+        switch (ctx->secy->key_len)
+        {
+            case 16:
+                sc.tx.cipher_suite = (ctx->secy->xpn) ? RTK_MACSEC_CIPHER_GCM_ASE_XPN_128 : RTK_MACSEC_CIPHER_GCM_ASE_128;
+                break;
+            case 32:
+                sc.tx.cipher_suite = (ctx->secy->xpn) ? RTK_MACSEC_CIPHER_GCM_ASE_XPN_256 : RTK_MACSEC_CIPHER_GCM_ASE_256;
+                break;
+            default:
+                PR_ERR("Not support key_len %d\n", ctx->secy->key_len);
+                return -EINVAL;
+        }
+
+        RTK_PHYLIB_VAL_TO_BYTE_ARRAY(ctx->secy->sci, 8, sc.tx.sci, 0, 8);
+        PR_DBG("[%s]secy->sci: 0x%llX\n", __FUNCTION__, ctx->secy->sci);
+        sc.tx.flow_match =    RTK_MACSEC_MATCH_NON_CTRL;
+        sc.tx.protect_frame = ctx->secy->protect_frames;
+        sc.tx.include_sci =   ctx->secy->tx_sc.send_sci;
+        sc.tx.use_es =        ctx->secy->tx_sc.end_station;
+        sc.tx.use_scb =       ctx->secy->tx_sc.scb;
+        sc.tx.conf_protect =  ctx->secy->tx_sc.encrypt;
+
+        RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sc_create(ctx->phydev, RTK_MACSEC_DIR_EGRESS, &sc, &sc_id, (ctx->secy->tx_sc.active) ? 1 : 0));
+    }
+
+    return ret;
+}
+
+static int rtk_macsec_del_secy(struct macsec_context *ctx)
+{
+    int32 ret = 0;
+    struct rtk_phy_priv *priv = ctx->phydev->priv;
+    rtk_macsec_port_info_t *macsec_db = priv->macsec;
+    uint32 i = 0;
+
+  #if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0))
+    if (ctx->prepare)
+        return 0;
+  #endif
+
+    for (i = 0; i < MACSEC_SC_MAX(macsec_db); i++)
+    {
+        if(MACSEC_SC_IS_USED(macsec_db, RTK_MACSEC_DIR_EGRESS, i))
+        {
+            PR_DBG("[%s] clear TX SC %u\n", __FUNCTION__, i);
+            RTK_PHYLIB_ERR_CHK(__rtk_macsec_clear_txsc(ctx, i));
+        }
+
+        if(MACSEC_SC_IS_USED(macsec_db, RTK_MACSEC_DIR_INGRESS, i))
+        {
+            PR_DBG("[%s] clear RX SC %u\n", __FUNCTION__, i);
+            RTK_PHYLIB_ERR_CHK(__rtk_macsec_clear_rxsc(ctx, i));
+        }
+    }
+    memset(&(macsec_db->port_stats), 0x0, sizeof(rtk_macsec_sc_t));
+    return ret;
+}
+
+static int rtk_macsec_upd_secy(struct macsec_context *ctx)
+{
+    int32 ret = 0;
+    struct rtk_phy_priv *priv = ctx->phydev->priv;
+    rtk_macsec_port_info_t *macsec_db = priv->macsec;
+
+    rtk_macsec_cipher_t    cipher_suite;
+
+  #if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0))
+    if (ctx->prepare)
+        return 0;
+  #endif
+
+    if(MACSEC_SC_IS_CLEAR(macsec_db, RTK_MACSEC_DIR_EGRESS, 0))
+    {
+        PR_ERR("[%s]MACSEC_SC_IS_CLEAR\n",__FUNCTION__);
+        return -ENOENT;
+    }
+
+    /* create TX SC */
+    {
+        uint32 sc_id = 0;
+        rtk_macsec_sc_t sc;
+        rtk_macsec_sc_t cur_sc;
+        RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sc_get(ctx->phydev, RTK_MACSEC_DIR_EGRESS, 0, &sc));
+        memcpy(&cur_sc, &sc, sizeof(rtk_macsec_sc_t));
+
+        switch (ctx->secy->key_len)
+        {
+            case 16:
+                cipher_suite = (ctx->secy->xpn) ? RTK_MACSEC_CIPHER_GCM_ASE_XPN_128 : RTK_MACSEC_CIPHER_GCM_ASE_128;
+                break;
+            case 32:
+                cipher_suite = (ctx->secy->xpn) ? RTK_MACSEC_CIPHER_GCM_ASE_XPN_256 : RTK_MACSEC_CIPHER_GCM_ASE_256;
+                break;
+            default:
+                PR_ERR("Not support key_len %d\n", ctx->secy->key_len);
+                return -EINVAL;
+        }
+
+        RTK_PHYLIB_VAL_TO_BYTE_ARRAY(ctx->secy->sci, 8, sc.tx.sci, 0, 8);
+      #ifdef MACSEC_DBG_PRINT
+        PR_DBG("[%s]secy->sci: 0x%llX\n", __FUNCTION__, ctx->secy->sci);
+        PR_DBG("cipher_suite  %u => %u\n", sc.tx.cipher_suite, cipher_suite);
+        PR_DBG("flow_match    %u => %u\n", sc.tx.flow_match, RTK_MACSEC_MATCH_NON_CTRL);
+        PR_DBG("protect_frame %u => %u\n", sc.tx.protect_frame, ctx->secy->protect_frames);
+        PR_DBG("include_sci   %u => %u\n", sc.tx.include_sci, ctx->secy->tx_sc.send_sci);
+        PR_DBG("use_es        %u => %u\n", sc.tx.use_es, ctx->secy->tx_sc.end_station);
+        PR_DBG("use_scb       %u => %u\n", sc.tx.use_scb, ctx->secy->tx_sc.scb);
+        PR_DBG("conf_protect  %u => %u\n", sc.tx.conf_protect, ctx->secy->tx_sc.encrypt);
+      #endif
+        sc.tx.cipher_suite = cipher_suite;
+        sc.tx.flow_match =    RTK_MACSEC_MATCH_NON_CTRL;
+        sc.tx.protect_frame = ctx->secy->protect_frames;
+        sc.tx.include_sci =   ctx->secy->tx_sc.send_sci;
+        sc.tx.use_es =        ctx->secy->tx_sc.end_station;
+        sc.tx.use_scb =       ctx->secy->tx_sc.scb;
+        sc.tx.conf_protect =  ctx->secy->tx_sc.encrypt;
+
+        if(memcmp(&cur_sc, &sc, sizeof(rtk_macsec_sc_t)) != 0)
+            RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sc_update(ctx->phydev, RTK_MACSEC_DIR_EGRESS, &sc, &sc_id, (ctx->secy->tx_sc.active) ? 1 : 0));
+    }
+
+    return ret;
+}
+
+static int rtk_macsec_add_rxsc(struct macsec_context *ctx)
+{
+    int32 ret = 0;
+    uint32 sc_id = 0;
+    rtk_macsec_sc_t sc;
+    memset(&sc, 0x0, sizeof(rtk_macsec_sc_t));
+
+  #if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0))
+    if (ctx->prepare)
+        return 0;
+  #endif
+
+    ret = rtk_phylib_macsec_sci_to_scid(ctx->phydev, RTK_MACSEC_DIR_INGRESS, ctx->rx_sc->sci, &sc_id);
+    if(ret != RTK_PHYLIB_ERR_ENTRY_NOTFOUND) //sc is existed
+    {
+        PR_DBG("[%s] ret:%d sc_id:%d is existed \n", __FUNCTION__, ret, sc_id);
+        return -EEXIST;
+    }
+    PR_DBG("[%s]rx_sc->sci: 0x%llX\n", __FUNCTION__, ctx->rx_sc->sci);
+
+    switch (ctx->secy->key_len)
+    {
+        case 16:
+            sc.rx.cipher_suite = (ctx->secy->xpn) ? RTK_MACSEC_CIPHER_GCM_ASE_XPN_128 : RTK_MACSEC_CIPHER_GCM_ASE_128;
+            break;
+        case 32:
+            sc.rx.cipher_suite = (ctx->secy->xpn) ? RTK_MACSEC_CIPHER_GCM_ASE_XPN_256 : RTK_MACSEC_CIPHER_GCM_ASE_256;
+            break;
+        default:
+            PR_ERR("Not support key_len %d\n", ctx->secy->key_len);
+            return -EINVAL;
+    }
+
+    PR_DBG("[%s]rx_sc->sci: 0x%llX\n", __FUNCTION__, ctx->rx_sc->sci);
+    RTK_PHYLIB_VAL_TO_BYTE_ARRAY(ctx->rx_sc->sci, 8, sc.rx.sci, 0, 8);
+    sc.rx.flow_match =    RTK_MACSEC_MATCH_SCI;
+
+    switch (ctx->secy->validate_frames)
+    {
+        case MACSEC_VALIDATE_DISABLED:
+            sc.rx.validate_frames = RTK_MACSEC_VALIDATE_DISABLE;
+            break;
+        case MACSEC_VALIDATE_CHECK:
+            sc.rx.validate_frames = RTK_MACSEC_VALIDATE_CHECK;
+            break;
+        case MACSEC_VALIDATE_STRICT:
+            sc.rx.validate_frames = RTK_MACSEC_VALIDATE_STRICT;
+            break;
+        default:
+            PR_ERR("Not support validate_frames %d\n", ctx->secy->validate_frames);
+            return -EINVAL;
+    }
+
+    sc.rx.replay_protect =        ctx->secy->replay_protect;
+    sc.rx.replay_window =       ctx->secy->replay_window;
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sc_create(ctx->phydev, RTK_MACSEC_DIR_INGRESS, &sc, &sc_id, (ctx->rx_sc->active) ? 1 : 0));
+    return ret;
+}
+
+static int rtk_macsec_del_rxsc(struct macsec_context *ctx)
+{
+    int32 ret = 0;
+    uint32 sc_id = 0;
+
+  #if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0))
+    if (ctx->prepare)
+        return 0;
+  #endif
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sci_to_scid(ctx->phydev, RTK_MACSEC_DIR_INGRESS, ctx->rx_sc->sci, &sc_id));
+    RTK_PHYLIB_ERR_CHK(__rtk_macsec_clear_rxsc(ctx, sc_id));
+
+    return ret;
+}
+
+static int rtk_macsec_upd_rxsc(struct macsec_context *ctx)
+{
+    int32 ret = 0;
+    uint32 sc_id = 0;
+    rtk_macsec_sc_t sc;
+    rtk_macsec_sc_t cur_sc;
+
+  #if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0))
+    if (ctx->prepare)
+        return 0;
+  #endif
+
+    ret = rtk_phylib_macsec_sci_to_scid(ctx->phydev, RTK_MACSEC_DIR_INGRESS, ctx->rx_sc->sci, &sc_id);
+    if(ret == RTK_PHYLIB_ERR_ENTRY_NOTFOUND) //sc is not existed
+    {
+        PR_DBG("[%s] ret:%d sc_id:%d is not existed \n", __FUNCTION__, ret, sc_id);
+        return -ENOENT;
+    }
+    PR_DBG("[%s]rx_sc->sci: 0x%llX\n", __FUNCTION__, ctx->rx_sc->sci);
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sc_get(ctx->phydev, RTK_MACSEC_DIR_INGRESS, sc_id, &sc));
+    memcpy(&cur_sc, &sc, sizeof(rtk_macsec_sc_t));
+
+    switch (ctx->secy->key_len)
+    {
+        case 16:
+            sc.rx.cipher_suite = (ctx->secy->xpn) ? RTK_MACSEC_CIPHER_GCM_ASE_XPN_128 : RTK_MACSEC_CIPHER_GCM_ASE_128;
+            break;
+        case 32:
+            sc.rx.cipher_suite = (ctx->secy->xpn) ? RTK_MACSEC_CIPHER_GCM_ASE_XPN_256 : RTK_MACSEC_CIPHER_GCM_ASE_256;
+            break;
+        default:
+            PR_ERR("Not support key_len %d\n", ctx->secy->key_len);
+            return -EINVAL;
+    }
+
+    PR_DBG("[%s]rx_sc->sci: 0x%llX\n", __FUNCTION__, ctx->rx_sc->sci);
+    RTK_PHYLIB_VAL_TO_BYTE_ARRAY(ctx->rx_sc->sci, 8, sc.rx.sci, 0, 8);
+    sc.rx.flow_match =    RTK_MACSEC_MATCH_SCI;
+
+    switch (ctx->secy->validate_frames)
+    {
+        case MACSEC_VALIDATE_DISABLED:
+            sc.rx.validate_frames = RTK_MACSEC_VALIDATE_DISABLE;
+            break;
+        case MACSEC_VALIDATE_CHECK:
+            sc.rx.validate_frames = RTK_MACSEC_VALIDATE_CHECK;
+            break;
+        case MACSEC_VALIDATE_STRICT:
+            sc.rx.validate_frames = RTK_MACSEC_VALIDATE_STRICT;
+            break;
+        default:
+            PR_ERR("Not support validate_frames %d\n", ctx->secy->validate_frames);
+            return -EINVAL;
+    }
+
+    sc.rx.replay_protect = ctx->secy->replay_protect;
+    sc.rx.replay_window = ctx->secy->replay_window;
+
+    if(memcmp(&cur_sc, &sc, sizeof(rtk_macsec_sc_t)) != 0)
+        RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sc_update(ctx->phydev, RTK_MACSEC_DIR_INGRESS, &sc, &sc_id, (ctx->rx_sc->active) ? 1 : 0));
+
+    return ret;
+}
+
+static int __rtk_macsec_set_rxsa(struct macsec_context *ctx, bool update)
+{
+    int32 ret = 0;
+    uint32 sc_id = 0;
+    rtk_macsec_sa_t sa;
+    memset(&sa, 0x0, sizeof(rtk_macsec_sa_t));
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sci_to_scid(ctx->phydev, RTK_MACSEC_DIR_INGRESS, ctx->sa.rx_sa->sc->sci, &sc_id));
+
+    if (update)
+    {
+        RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sa_get(ctx->phydev, RTK_MACSEC_DIR_INGRESS, sc_id, ctx->sa.assoc_num, &sa));
+    }
+    else
+    {
+        sa.key_bytes = ctx->secy->key_len;
+        memcpy(sa.key, ctx->sa.key, sa.key_bytes);
+        if(ctx->secy->xpn)
+        {
+            memcpy(sa.salt, ctx->sa.rx_sa->key.salt.bytes, MACSEC_SALT_LEN);
+            RTK_PHYLIB_VAL_TO_BYTE_ARRAY(ctx->sa.rx_sa->ssci, 4, sa.ssci, 0, 4);
+        }
+    }
+
+    sa.pn = ctx->sa.tx_sa->next_pn_halves.lower;
+    sa.pn_h = ctx->sa.tx_sa->next_pn_halves.upper;
+
+    #ifdef MACSEC_DBG_PRINT
+    {
+        PR_DBG("[%s,%d] update:%u \n", __FUNCTION__, __LINE__, update);
+        PR_DBG("  KEY 0-15 = 0x%02X%02X%02X%02X%02X%02X%02X%02X %02X%02X%02X%02X%02X%02X%02X%02X\n",
+            sa.key[0], sa.key[1], sa.key[2], sa.key[3],
+            sa.key[4], sa.key[5], sa.key[6], sa.key[7],
+            sa.key[8], sa.key[9], sa.key[10],sa.key[11],
+            sa.key[12],sa.key[13],sa.key[14],sa.key[15]);
+        if (ctx->secy->key_len == 32)
+        {
+            PR_DBG("  KEY16-31 = 0x%02X%02X%02X%02X%02X%02X%02X%02X %02X%02X%02X%02X%02X%02X%02X%02X\n",
+                sa.key[16],sa.key[17],sa.key[18],sa.key[19],
+                sa.key[20],sa.key[21],sa.key[22],sa.key[23],
+                sa.key[24],sa.key[25],sa.key[26],sa.key[27],
+                sa.key[28],sa.key[29],sa.key[30],sa.key[31]);
+        }
+        PR_DBG("  ctx->sa.rx_sa->active: %u\n", ctx->sa.rx_sa->active);
+        PR_DBG("  ctx->secy->xpn: %u\n", ctx->secy->xpn);
+        PR_DBG("  sa.pn: 0x%X, sa.pn_h: 0x%X\n", sa.pn, sa.pn_h);
+        if(ctx->secy->xpn)
+        {
+            PR_DBG("  ctx->sa.tx_sa->key.salt = 0x%02X%02X%02X%02X %02X%02X%02X%02X %02X%02X%02X%02X\n",
+                sa.salt[0], sa.salt[1], sa.salt[2],  sa.salt[3],
+                sa.salt[4], sa.salt[5], sa.salt[6],  sa.salt[7],
+                sa.salt[8], sa.salt[9], sa.salt[10], sa.salt[11]);
+        }
+    }
+    #endif
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sa_create(ctx->phydev, RTK_MACSEC_DIR_INGRESS, sc_id, ctx->sa.assoc_num, &sa));
+
+    if (ctx->sa.rx_sa->active)
+    {
+        RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sa_activate(ctx->phydev, RTK_MACSEC_DIR_INGRESS, sc_id, ctx->sa.assoc_num));
+    }
+    else
+    {
+        RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_rxsa_disable(ctx->phydev, sc_id, ctx->sa.assoc_num));
+    }
+
+    return ret;
+}
+
+static int rtk_macsec_add_rxsa(struct macsec_context *ctx)
+{
+    int32 ret = 0;
+    uint32 sc_id = 0, sa_id = 0;
+    struct rtk_phy_priv *priv = ctx->phydev->priv;
+    rtk_macsec_port_info_t *macsec_db = priv->macsec;
+
+  #if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0))
+    if (ctx->prepare)
+        return 0;
+  #endif
+
+    RTK_PHYLIB_ERR_CHK(__rtk_macsec_set_rxsa(ctx, false));
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sci_to_scid(ctx->phydev, RTK_MACSEC_DIR_INGRESS, ctx->sa.rx_sa->sc->sci, &sc_id));
+    sa_id = PHY_MACSEC_HW_SA_ID(sc_id, ctx->sa.assoc_num);
+    macsec_db->rxsa_stats[sa_id] = kzalloc(sizeof(rtk_macsec_rxsa_stats_t), GFP_KERNEL);
+    if (macsec_db->rxsa_stats[sa_id] == NULL)
+    {
+        rtk_macsec_del_rxsa(ctx);
+        return -ENOMEM;
+    }
+
+    return ret;
+}
+
+static int rtk_macsec_del_rxsa(struct macsec_context *ctx)
+{
+    int32 ret = 0;
+    uint32 sc_id = 0, sa_id = 0;
+    struct rtk_phy_priv *priv = ctx->phydev->priv;
+    rtk_macsec_port_info_t *macsec_db = priv->macsec;
+
+  #if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0))
+    if (ctx->prepare)
+        return 0;
+  #endif
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sci_to_scid(ctx->phydev, RTK_MACSEC_DIR_INGRESS, ctx->sa.rx_sa->sc->sci, &sc_id));
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sa_del(ctx->phydev, RTK_MACSEC_DIR_INGRESS, sc_id, ctx->sa.assoc_num));
+
+    sa_id = PHY_MACSEC_HW_SA_ID(sc_id, ctx->sa.assoc_num);
+    if (macsec_db->rxsa_stats[sa_id] != NULL)
+    {
+        kfree(macsec_db->rxsa_stats[sa_id]);
+        macsec_db->rxsa_stats[sa_id] = NULL;
+    }
+
+    return ret;
+}
+
+static int rtk_macsec_upd_rxsa(struct macsec_context *ctx)
+{
+    int32 ret = 0;
+
+  #if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0))
+    if (ctx->prepare)
+        return 0;
+  #endif
+
+    RTK_PHYLIB_ERR_CHK(__rtk_macsec_set_rxsa(ctx, true));
+    return ret;
+}
+
+static int __rtk_macsec_set_txsa(struct macsec_context *ctx, bool update)
+{
+    int32 ret = 0;
+    uint32 sc_id = 0;
+    rtk_macsec_sa_t sa;
+    memset(&sa, 0x0, sizeof(rtk_macsec_sa_t));
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sci_to_scid(ctx->phydev, RTK_MACSEC_DIR_EGRESS, ctx->secy->sci, &sc_id));
+
+    if (update)
+    {
+        RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sa_get(ctx->phydev, RTK_MACSEC_DIR_EGRESS, sc_id, ctx->sa.assoc_num, &sa));
+    }
+    else
+    {
+        sa.key_bytes = ctx->secy->key_len;
+        memcpy(sa.key, ctx->sa.key, sa.key_bytes);
+        if(ctx->secy->xpn)
+        {
+            memcpy(sa.salt, ctx->sa.tx_sa->key.salt.bytes, MACSEC_SALT_LEN);
+            RTK_PHYLIB_VAL_TO_BYTE_ARRAY(ctx->sa.tx_sa->ssci, 4, sa.ssci, 0, 4);
+        }
+    }
+
+    sa.pn = ctx->sa.tx_sa->next_pn_halves.lower;
+    sa.pn_h = ctx->sa.tx_sa->next_pn_halves.upper;
+
+    #ifdef MACSEC_DBG_PRINT
+    {
+        PR_DBG("[%s,%d] update:%u \n", __FUNCTION__, __LINE__, update);
+        PR_DBG("  KEY 0-15 = 0x%02X%02X%02X%02X%02X%02X%02X%02X %02X%02X%02X%02X%02X%02X%02X%02X\n",
+            sa.key[0], sa.key[1], sa.key[2], sa.key[3],
+            sa.key[4], sa.key[5], sa.key[6], sa.key[7],
+            sa.key[8], sa.key[9], sa.key[10],sa.key[11],
+            sa.key[12],sa.key[13],sa.key[14],sa.key[15]);
+        if (ctx->secy->key_len == 32)
+        {
+            PR_DBG("  KEY16-31 = 0x%02X%02X%02X%02X%02X%02X%02X%02X %02X%02X%02X%02X%02X%02X%02X%02X\n",
+                sa.key[16],sa.key[17],sa.key[18],sa.key[19],
+                sa.key[20],sa.key[21],sa.key[22],sa.key[23],
+                sa.key[24],sa.key[25],sa.key[26],sa.key[27],
+                sa.key[28],sa.key[29],sa.key[30],sa.key[31]);
+        }
+        PR_DBG("  ctx->sa.tx_sa->active: %u\n", ctx->sa.tx_sa->active);
+        PR_DBG("  ctx->secy->xpn: %u\n", ctx->secy->xpn);
+        PR_DBG("  sa.pn: 0x%X, sa.pn_h: 0x%X\n", sa.pn, sa.pn_h);
+        if(ctx->secy->xpn)
+        {
+            PR_DBG("  ctx->sa.tx_sa->key.salt = 0x%02X%02X%02X%02X %02X%02X%02X%02X %02X%02X%02X%02X\n",
+                sa.salt[0], sa.salt[1], sa.salt[2],  sa.salt[3],
+                sa.salt[4], sa.salt[5], sa.salt[6],  sa.salt[7],
+                sa.salt[8], sa.salt[9], sa.salt[10], sa.salt[11]);
+        }
+    }
+    #endif
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sa_create(ctx->phydev, RTK_MACSEC_DIR_EGRESS, sc_id, ctx->sa.assoc_num, &sa));
+
+    if (ctx->sa.tx_sa->active)
+    {
+        RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sa_activate(ctx->phydev, RTK_MACSEC_DIR_EGRESS, sc_id, ctx->sa.assoc_num));
+    }
+    else
+    {
+        RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_txsa_disable(ctx->phydev, sc_id));
+
+    }
+    return ret;
+}
+
+static int rtk_macsec_add_txsa(struct macsec_context *ctx)
+{
+    int32 ret = 0;
+    uint32 sc_id = 0, sa_id = 0;
+    struct rtk_phy_priv *priv = ctx->phydev->priv;
+    rtk_macsec_port_info_t *macsec_db = priv->macsec;
+
+  #if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0))
+    if (ctx->prepare)
+        return 0;
+  #endif
+
+    RTK_PHYLIB_ERR_CHK(__rtk_macsec_set_txsa(ctx, false));
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sci_to_scid(ctx->phydev, RTK_MACSEC_DIR_EGRESS, ctx->secy->sci, &sc_id));
+    sa_id = PHY_MACSEC_HW_SA_ID(sc_id, ctx->sa.assoc_num);
+    macsec_db->txsa_stats[sa_id] = kzalloc(sizeof(rtk_macsec_txsa_stats_t), GFP_KERNEL);
+    if (macsec_db->txsa_stats[sa_id] == NULL)
+    {
+        rtk_macsec_del_txsa(ctx);
+        return -ENOMEM;
+    }
+
+    return ret;
+}
+
+static int rtk_macsec_del_txsa(struct macsec_context *ctx)
+{
+    int32 ret = 0;
+    uint32 sc_id = 0, sa_id = 0;
+    struct rtk_phy_priv *priv = ctx->phydev->priv;
+    rtk_macsec_port_info_t *macsec_db = priv->macsec;
+
+  #if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0))
+    if (ctx->prepare)
+        return 0;
+  #endif
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sci_to_scid(ctx->phydev, RTK_MACSEC_DIR_EGRESS, ctx->secy->sci, &sc_id));
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sa_del(ctx->phydev, RTK_MACSEC_DIR_EGRESS, sc_id, ctx->sa.assoc_num));
+
+    sa_id = PHY_MACSEC_HW_SA_ID(sc_id, ctx->sa.assoc_num);
+    if (macsec_db->txsa_stats[sa_id] != NULL)
+    {
+        kfree(macsec_db->txsa_stats[sa_id]);
+        macsec_db->txsa_stats[sa_id] = NULL;
+    }
+
+    return ret;
+}
+
+static int rtk_macsec_upd_txsa(struct macsec_context *ctx)
+{
+    int32 ret = 0;
+
+  #if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0))
+    if (ctx->prepare)
+        return 0;
+  #endif
+
+    RTK_PHYLIB_ERR_CHK(__rtk_macsec_set_txsa(ctx, true));
+    return ret;
+}
+
+
+static int rtk_macsec_get_dev_stats(struct macsec_context *ctx)
+{
+    int32 ret = 0;
+    uint64 cnt = 0;
+    uint32 sc_id = 0, an = 0;
+
+  #if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0))
+    if (ctx->prepare)
+        return 0;
+  #endif
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_stat_port_get(ctx->phydev, RTK_MACSEC_STAT_OutPktsUntagged, &cnt));
+    ctx->stats.dev_stats->OutPktsUntagged = cnt;
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_stat_port_get(ctx->phydev, RTK_MACSEC_STAT_InPktsUntagged, &cnt));
+    ctx->stats.dev_stats->InPktsUntagged = cnt;
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_stat_port_get(ctx->phydev, RTK_MACSEC_STAT_InPktsNoTag, &cnt));
+    ctx->stats.dev_stats->InPktsNoTag = cnt;
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_stat_port_get(ctx->phydev, RTK_MACSEC_STAT_InPktsBadTag, &cnt));
+    ctx->stats.dev_stats->InPktsBadTag = cnt;
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_stat_port_get(ctx->phydev, RTK_MACSEC_STAT_InPktsUnknownSCI, &cnt));
+    ctx->stats.dev_stats->InPktsUnknownSCI = cnt;
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_stat_port_get(ctx->phydev, RTK_MACSEC_STAT_InPktsNoSCI, &cnt));
+    ctx->stats.dev_stats->InPktsNoSCI = cnt;
+
+    ctx->stats.dev_stats->InPktsOverrun = 0; /* not support */
+
+    /* accumulate over each egress SA */
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sci_to_scid(ctx->phydev, RTK_MACSEC_DIR_EGRESS, ctx->secy->sci, &sc_id));
+    for (an = 0; an < MACSEC_NUM_AN; an++)
+    {
+        if (0 == rtk_phylib_macsec_stat_txsa_get(ctx->phydev, sc_id, an, RTK_MACSEC_TXSA_STAT_OutPktsTooLong, &cnt))
+        {
+            ctx->stats.dev_stats->OutPktsTooLong += cnt;
+        }
+    }
+
+    return ret;
+}
+
+static int rtk_macsec_get_txsc_stats(struct macsec_context *ctx)
+{
+    int32 ret = 0;
+    uint64 cnt = 0;
+    uint32 sc_id = 0, an = 0;
+
+  #if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0))
+    if (ctx->prepare)
+        return 0;
+  #endif
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sci_to_scid(ctx->phydev, RTK_MACSEC_DIR_EGRESS, ctx->secy->sci, &sc_id));
+
+    /* accumulate over each egress SA */
+    for (an = 0; an < MACSEC_NUM_AN; an++)
+    {
+        if (0 == rtk_phylib_macsec_stat_txsa_get(ctx->phydev, sc_id, an, RTK_MACSEC_TXSA_STAT_OutPktsProtectedEncrypted, &cnt))
+        {
+            if (ctx->secy->tx_sc.encrypt)
+            {
+                ctx->stats.tx_sc_stats->OutPktsEncrypted += cnt;
+            }
+            else
+            {
+                ctx->stats.tx_sc_stats->OutPktsProtected += cnt;
+            }
+        }
+
+        if (0 == rtk_phylib_macsec_stat_txsa_get(ctx->phydev, sc_id, an, RTK_MACSEC_TXSA_STAT_OutOctetsProtectedEncrypted, &cnt))
+        {
+            if (ctx->secy->tx_sc.encrypt)
+            {
+                ctx->stats.tx_sc_stats->OutOctetsEncrypted += cnt;
+            }
+            else
+            {
+                ctx->stats.tx_sc_stats->OutOctetsProtected += cnt;
+            }
+        }
+
+    }
+
+    return ret;
+}
+
+static int rtk_macsec_get_rxsc_stats(struct macsec_context *ctx)
+{
+    int32 ret = 0;
+    uint64 cnt = 0;
+    uint32 sc_id = 0, an = 0;
+
+  #if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0))
+    if (ctx->prepare)
+        return 0;
+  #endif
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sci_to_scid(ctx->phydev, RTK_MACSEC_DIR_INGRESS, ctx->rx_sc->sci, &sc_id));
+
+    /* accumulate over each ingress SA */
+    for (an = 0; an < MACSEC_NUM_AN; an++)
+    {
+        if (0 == rtk_phylib_macsec_stat_rxsa_get(ctx->phydev, sc_id, an, RTK_MACSEC_RXSA_STAT_InOctetsDecryptedValidated, &cnt))
+        {
+            ctx->stats.rx_sc_stats->InOctetsValidated += cnt;
+            ctx->stats.rx_sc_stats->InOctetsDecrypted = ctx->stats.rx_sc_stats->InOctetsValidated;
+        }
+        if (0 == rtk_phylib_macsec_stat_rxsa_get(ctx->phydev, sc_id, an, RTK_MACSEC_RXSA_STAT_InPktsUnchecked, &cnt))
+        {
+            ctx->stats.rx_sc_stats->InPktsUnchecked += cnt;
+        }
+        if (0 == rtk_phylib_macsec_stat_rxsa_get(ctx->phydev, sc_id, an, RTK_MACSEC_RXSA_STAT_InPktsDelayed, &cnt))
+        {
+            ctx->stats.rx_sc_stats->InPktsDelayed += cnt;
+        }
+        if (0 == rtk_phylib_macsec_stat_rxsa_get(ctx->phydev, sc_id, an, RTK_MACSEC_RXSA_STAT_InPktsOK, &cnt))
+        {
+            ctx->stats.rx_sc_stats->InPktsOK += cnt;
+        }
+        if (0 == rtk_phylib_macsec_stat_rxsa_get(ctx->phydev, sc_id, an, RTK_MACSEC_RXSA_STAT_InPktsInvalid, &cnt))
+        {
+            ctx->stats.rx_sc_stats->InPktsInvalid += cnt;
+        }
+        if (0 == rtk_phylib_macsec_stat_rxsa_get(ctx->phydev, sc_id, an, RTK_MACSEC_RXSA_STAT_InPktsLate, &cnt))
+        {
+            ctx->stats.rx_sc_stats->InPktsLate += cnt;
+        }
+        if (0 == rtk_phylib_macsec_stat_rxsa_get(ctx->phydev, sc_id, an, RTK_MACSEC_RXSA_STAT_InPktsNotValid, &cnt))
+        {
+            ctx->stats.rx_sc_stats->InPktsNotValid += cnt;
+        }
+        if (0 == rtk_phylib_macsec_stat_rxsa_get(ctx->phydev, sc_id, an, RTK_MACSEC_RXSA_STAT_InPktsNotUsingSA, &cnt))
+        {
+            ctx->stats.rx_sc_stats->InPktsNotUsingSA += cnt;
+        }
+        if (0 == rtk_phylib_macsec_stat_rxsa_get(ctx->phydev, sc_id, an, RTK_MACSEC_RXSA_STAT_InPktsUnusedSA, &cnt))
+        {
+            ctx->stats.rx_sc_stats->InPktsUnusedSA += cnt;
+        }
+    }
+
+    return ret;
+}
+
+static int rtk_macsec_get_txsa_stats(struct macsec_context *ctx)
+{
+    int32 ret = 0;
+    uint64 cnt = 0;
+    uint32 sc_id = 0;
+    rtk_macsec_sa_t sa;
+
+  #if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0))
+    if (ctx->prepare)
+        return 0;
+  #endif
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sci_to_scid(ctx->phydev, RTK_MACSEC_DIR_EGRESS, ctx->secy->sci, &sc_id));
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_stat_txsa_get(ctx->phydev, sc_id, ctx->sa.assoc_num, RTK_MACSEC_TXSA_STAT_OutPktsProtectedEncrypted, &cnt));
+    if (ctx->secy->tx_sc.encrypt)
+    {
+        ctx->stats.tx_sa_stats->OutPktsEncrypted = (uint32)cnt;
+    }
+    else
+    {
+        ctx->stats.tx_sa_stats->OutPktsProtected = (uint32)cnt;
+    }
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sa_get(ctx->phydev, RTK_MACSEC_DIR_EGRESS, sc_id, ctx->sa.assoc_num, &sa));
+    ctx->sa.tx_sa->next_pn_halves.lower = sa.pn;
+    ctx->sa.tx_sa->next_pn_halves.upper = sa.pn_h;
+
+    return ret;
+}
+
+static int rtk_macsec_get_rxsa_stats(struct macsec_context *ctx)
+{
+    int32 ret = 0;
+    uint64 cnt = 0;
+    uint32 sc_id = 0;
+    rtk_macsec_sa_t sa;
+
+  #if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0))
+    if (ctx->prepare)
+        return 0;
+  #endif
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sci_to_scid(ctx->phydev, RTK_MACSEC_DIR_INGRESS, ctx->rx_sc->sci, &sc_id));
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_stat_rxsa_get(ctx->phydev, sc_id, ctx->sa.assoc_num, RTK_MACSEC_RXSA_STAT_InPktsOK, &cnt));
+    ctx->stats.rx_sa_stats->InPktsOK = (uint32)cnt;
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_stat_rxsa_get(ctx->phydev, sc_id, ctx->sa.assoc_num, RTK_MACSEC_RXSA_STAT_InPktsInvalid, &cnt));
+    ctx->stats.rx_sa_stats->InPktsInvalid = (uint32)cnt;
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_stat_rxsa_get(ctx->phydev, sc_id, ctx->sa.assoc_num, RTK_MACSEC_RXSA_STAT_InPktsNotValid, &cnt));
+    ctx->stats.rx_sa_stats->InPktsNotValid = (uint32)cnt;
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_stat_rxsa_get(ctx->phydev, sc_id, ctx->sa.assoc_num, RTK_MACSEC_RXSA_STAT_InPktsNotUsingSA, &cnt));
+    ctx->stats.rx_sa_stats->InPktsNotUsingSA = (uint32)cnt;
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_stat_rxsa_get(ctx->phydev, sc_id, ctx->sa.assoc_num, RTK_MACSEC_RXSA_STAT_InPktsUnusedSA, &cnt));
+    ctx->stats.rx_sa_stats->InPktsUnusedSA = (uint32)cnt;
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sa_get(ctx->phydev, RTK_MACSEC_DIR_INGRESS, sc_id, ctx->sa.assoc_num, &sa));
+    ctx->sa.rx_sa->next_pn_halves.lower = sa.pn;
+    ctx->sa.rx_sa->next_pn_halves.upper = sa.pn_h;
+
+    return ret;
+}
+
+static const struct macsec_ops rtk_macsec_ops = {
+    /* Device wide */
+    .mdo_dev_open = rtk_macsec_dev_open,
+    .mdo_dev_stop = rtk_macsec_dev_stop,
+    /* SecY */
+    .mdo_add_secy = rtk_macsec_add_secy,
+    .mdo_upd_secy = rtk_macsec_upd_secy,
+    .mdo_del_secy = rtk_macsec_del_secy,
+    /* Security channels */
+    .mdo_add_rxsc = rtk_macsec_add_rxsc,
+    .mdo_upd_rxsc = rtk_macsec_upd_rxsc,
+    .mdo_del_rxsc = rtk_macsec_del_rxsc,
+    /* Security associations */
+    .mdo_add_rxsa = rtk_macsec_add_rxsa,
+    .mdo_upd_rxsa = rtk_macsec_upd_rxsa,
+    .mdo_del_rxsa = rtk_macsec_del_rxsa,
+    .mdo_add_txsa = rtk_macsec_add_txsa,
+    .mdo_upd_txsa = rtk_macsec_upd_txsa,
+    .mdo_del_txsa = rtk_macsec_del_txsa,
+    /* Statistics */
+    .mdo_get_dev_stats = rtk_macsec_get_dev_stats,
+    .mdo_get_tx_sc_stats = rtk_macsec_get_txsc_stats,
+    .mdo_get_rx_sc_stats = rtk_macsec_get_rxsc_stats,
+    .mdo_get_tx_sa_stats = rtk_macsec_get_txsa_stats,
+    .mdo_get_rx_sa_stats = rtk_macsec_get_rxsa_stats,
+};
+
+int rtk_macsec_init(struct phy_device *phydev)
+{
+    int32 ret = 0;
+    struct rtk_phy_priv *priv = phydev->priv;
+
+    priv->macsec = kzalloc(sizeof(*(priv->macsec)), GFP_KERNEL);
+    if (!priv->macsec)
+        return -ENOMEM;
+    memset(priv->macsec, 0, sizeof(*(priv->macsec)));
+
+    switch (phydev->drv->phy_id)
+    {
+        case REALTEK_PHY_ID_RTL8261N:
+        case REALTEK_PHY_ID_RTL8264B:
+            phydev->macsec_ops = &rtk_macsec_ops;
+            priv->macsec->max_sa_num = 64;
+            priv->macsec->max_sc_num = 64/4;
+            ret = rtk_phylib_826xb_macsec_init(phydev);
+            if (ret != 0)
+            {
+                phydev_err(phydev, "[%s]rtk_phylib_826xb_macsec_init failed!! 0x%X\n", __FUNCTION__, ret);
+                return ret;
+            }
+            break;
+        default:
+            PR_ERR("[%s]phy_id: 0x%X not support!\n", __FUNCTION__, phydev->drv->phy_id);
+            kfree(priv->macsec);
+            priv->macsec = NULL;
+            return -EOPNOTSUPP;
+    }
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_init(phydev));
+
+    return 0;
+}
diff --git a/sources/rtk-gp3000/src/hal/phy/rtk_osal.c b/sources/rtk-gp3000/src/hal/phy/rtk_osal.c
new file mode 100644
index 00000000..c119f606
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/rtk_osal.c
@@ -0,0 +1,58 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
+ */
+
+#include "type.h"
+#include "error.h"
+#include "rtk_phylib_def.h"
+
+#include <linux/version.h>
+#include <linux/jiffies.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/sched.h>
+#include <linux/wait.h>
+#include <linux/sched/signal.h>
+#include <linux/phy.h>
+
+#ifndef CONFIG_OPENWRT_SDK
+int32
+osal_time_usecs_get(osal_usecs_t *pUsec)
+{
+    struct timespec64 ts;
+
+    RT_PARAM_CHK((NULL == pUsec), RT_ERR_NULL_POINTER);
+
+    ktime_get_ts64(&ts);
+    *pUsec = (osal_usecs_t)((ts.tv_sec * USEC_PER_SEC) + (ts.tv_nsec / NSEC_PER_USEC));
+    return RT_ERR_OK;
+}
+
+void *
+osal_alloc(uint32 size)
+{
+    void *p;
+    p = kmalloc((size_t)size, GFP_ATOMIC);
+    return p;
+}
+#endif
+
+int32
+phy_common_general_reg_mmd_get(uint32 unit, rtk_port_t port, uint32 mmdAddr, uint32 mmdReg, uint32 *pData)
+{
+    int32 rData = 0;
+    rData = phy_read_mmd(port, mmdAddr, mmdReg);
+    if (rData < 0)
+        return RT_ERR_FAILED;
+    *pData = (uint32)rData;
+    return RT_ERR_OK;
+}
+
+int32
+phy_common_general_reg_mmd_set(uint32 unit, rtk_port_t port, uint32 mmdAddr, uint32 mmdReg, uint32 data)
+{
+    int ret = phy_write_mmd(port, mmdAddr, mmdReg, data);
+    return (ret < 0) ? RT_ERR_FAILED : RT_ERR_OK;
+}
diff --git a/sources/rtk-gp3000/src/hal/phy/rtk_osal.h b/sources/rtk-gp3000/src/hal/phy/rtk_osal.h
new file mode 100644
index 00000000..0f8abb1e
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/rtk_osal.h
@@ -0,0 +1,100 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
+ */
+
+#ifndef __RTK_PHY_OSAL_H
+#define __RTK_PHY_OSAL_H
+
+#include <linux/kernel.h>
+#include <linux/phy.h>
+#include "type.h"
+#include "error.h"
+#include "phy_patch.h"
+#include "rtk_phylib.h"
+
+#ifdef PHYPATCH_DB_GET
+    #undef PHYPATCH_DB_GET
+#endif
+
+#define PHYPATCH_DB_GET(_unit, _pPhy_device, _pPatchDb) \
+    do { \
+        struct rtk_phy_priv *_pPriv = (_pPhy_device)->priv; \
+        rt_phy_patch_db_t *_pDb = _pPriv->patch; _pPatchDb = _pDb; \
+        /*printk("[PHYPATCH_DB_GET] ? [%s]\n", (_pDb != NULL) ? "E":"N");*/ \
+    } while(0)
+
+#define HWP_9300_FAMILY_ID(_unit)       1
+#define HWP_9310_FAMILY_ID(_unit)       0
+#define RTK_9300_FAMILY_ID(_unit)       1
+#define RTK_9310_FAMILY_ID(_unit)       0
+#define RTK_9311B_FAMILY_ID(_unit)      0
+#define RTK_9330_FAMILY_ID(_unit)       0
+
+#ifndef WAIT_COMPLETE_VAR
+#define WAIT_COMPLETE_VAR() \
+    osal_usecs_t    _t, _now, _t_wait=0, _timeout;  \
+    int32           _chkCnt=0;
+
+#define WAIT_COMPLETE(_timeout_us)     \
+    _timeout = _timeout_us;  \
+    for(osal_time_usecs_get(&_t),osal_time_usecs_get(&_now),_t_wait=0,_chkCnt=0 ; \
+        (_t_wait <= _timeout); \
+        osal_time_usecs_get(&_now), _chkCnt++, _t_wait += ((_now >= _t) ? (_now - _t) : (0xFFFFFFFF - _t + _now)),_t = _now \
+       )
+
+#define WAIT_COMPLETE_IS_TIMEOUT()   (_t_wait > _timeout)
+#endif
+
+/* OSAL */
+#include <linux/slab.h>
+int32 osal_time_usecs_get(osal_usecs_t *pUsec);
+void *osal_alloc(uint32 size);
+#define osal_time_mdelay  mdelay
+
+#include <linux/ctype.h>    /* for Kernel Space */
+#include <linux/kernel.h>
+#include <linux/string.h>
+#define osal_strlen   strlen
+#define osal_strcmp   strcmp
+#define osal_strcpy   strcpy
+#define osal_strncpy  strncpy
+#define osal_strcat   strcat
+#define osal_strchr   strchr
+#define osal_memset   memset
+#define osal_memcpy   memcpy
+#define osal_memcmp   memcmp
+#define osal_strdup   strdup
+#define osal_strncmp  strncmp
+#define osal_strstr   strstr
+#define osal_strtok   strtok
+#define osal_strtok_r   strtok_r
+#define osal_toupper  toupper
+
+#define osal_printf   printk
+
+/* HWP */
+#define HWP_PORT_SMI(unit, port)               0
+#define HWP_PHY_MODEL_BY_PORT(unit, port)      0
+#define HWP_PHY_ADDR(unit, port)               0
+#define HWP_PHY_BASE_MACID(unit, p)            0
+#define HWP_PORT_TRAVS_EXCEPT_CPU(unit, p)     if (bcast_phyad < 0x1F && p != NULL)
+
+
+/* RT_LOG */
+//#define RT_LOG(level, module, fmt, args...)               do { printk("RT_LOG:"fmt, ## args); } while(0)
+#define RT_LOG(level, module, fmt, args...)               do {} while(0)
+#define RT_ERR(error_code, module, fmt, args...)          do {} while(0)
+#define RT_INIT_ERR(error_code, module, fmt, args...)     do {} while(0)
+#define RT_INIT_MSG(fmt, args...)                         do {} while(0)
+
+#define phy_826xb_ctrl_set(unit, p, RTK_PHY_CTRL_MIIM_BCAST_PHYAD, bcast_phyad)  0
+#define phy_8224_ctrl_set(unit, p, RTK_PHY_CTRL_MIIM_BCAST_PHYAD, bcast_phyad)  0
+
+/* reg access */
+int32 phy_common_general_reg_mmd_get(uint32 unit, rtk_port_t port, uint32 mmdAddr, uint32 mmdReg, uint32 *pData);
+int32 phy_common_general_reg_mmd_set(uint32 unit, rtk_port_t port, uint32 mmdAddr, uint32 mmdReg, uint32 data);
+
+
+#endif /* __RTK_PHY_OSAL_H */
diff --git a/sources/rtk-gp3000/src/hal/phy/rtk_phy.c b/sources/rtk-gp3000/src/hal/phy/rtk_phy.c
new file mode 100644
index 00000000..9d592b22
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/rtk_phy.c
@@ -0,0 +1,613 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/phy.h>
+#include <linux/ethtool.h>
+#include <linux/ethtool_netlink.h>
+#include <linux/netdevice.h>
+
+#include "phy_rtl826xb_patch.h"
+
+#include "rtk_phylib_rtl826xb.h"
+#include "rtk_phylib_rtl8224.h"
+#include "rtk_phylib_macsec.h"
+#include "rtk_phylib.h"
+
+#include "rtk_phy.h"
+#include "rtk_phy_rtl8224.h"
+
+static int rtk_phy_cable_test_report_trans(rtk_rtct_channel_result_t *result)
+{
+    if(result->cable_status == 0)
+        return ETHTOOL_A_CABLE_RESULT_CODE_OK;
+
+    if(result->cable_status & RTK_PHYLIB_CABLE_STATUS_INTER_PAIR_SHORT)
+        return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
+    if(result->cable_status & RTK_PHYLIB_CABLE_STATUS_SHORT)
+        return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
+    if(result->cable_status & RTK_PHYLIB_CABLE_STATUS_OPEN)
+        return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
+    if(result->cable_status & RTK_PHYLIB_CABLE_STATUS_CROSS)
+        return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
+
+    return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
+}
+
+static int rtl826xb_get_features(struct phy_device *phydev)
+{
+    int ret;
+    struct rtk_phy_priv *priv = phydev->priv;
+
+    ret = genphy_c45_pma_read_abilities(phydev);
+    if (ret)
+        return ret;
+
+    linkmode_or(phydev->supported, phydev->supported, PHY_BASIC_FEATURES);
+
+    linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
+                       phydev->supported);
+    linkmode_set_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
+                       phydev->supported);
+
+    /* not support 10M modes */
+    linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
+                       phydev->supported);
+    linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
+                       phydev->supported);
+
+    switch (priv->phytype)
+    {
+        case RTK_PHYLIB_RTL8251L:
+        case RTK_PHYLIB_RTL8254B:
+            linkmode_clear_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
+                       phydev->supported);
+            break;
+
+        default:
+            break;
+    }
+
+    return 0;
+}
+
+static int rtl826xb_probe(struct phy_device *phydev)
+{
+    struct rtk_phy_priv *priv = NULL;
+    int data = 0;
+
+    priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct rtk_phy_priv), GFP_KERNEL);
+    if (!priv)
+    {
+        return -ENOMEM;
+    }
+    memset(priv, 0, sizeof(struct rtk_phy_priv));
+
+    if (phy_rtl826xb_patch_db_init(0, phydev, &(priv->patch)) != RT_ERR_OK)
+        return -ENOMEM;
+
+    if (phydev->drv->phy_id == REALTEK_PHY_ID_RTL8261N)
+    {
+        data =  phy_read_mmd(phydev, 30, 0x103);
+        if (data < 0)
+            return data;
+
+        if (data == 0x8251)
+        {
+            priv->phytype = RTK_PHYLIB_RTL8251L;
+        }
+        else
+        {
+            priv->phytype = RTK_PHYLIB_RTL8261N;
+        }
+    }
+    else if (phydev->drv->phy_id == REALTEK_PHY_ID_RTL8264B)
+    {
+        data =  phy_read_mmd(phydev, 30, 0x103);
+        if (data < 0)
+            return data;
+
+        if (data == 0x8254)
+        {
+            priv->phytype = RTK_PHYLIB_RTL8254B;
+        }
+        else
+        {
+            priv->phytype = RTK_PHYLIB_RTL8264B;
+        }
+    }
+    priv->isBasePort = (phydev->drv->phy_id == REALTEK_PHY_ID_RTL8261N) ? (1) : (((phydev->mdio.addr % 4) == 0) ? (1) : (0));
+    phydev->priv = priv;
+
+    return 0;
+}
+
+static int rtkphy_config_init(struct phy_device *phydev)
+{
+    int ret = 0;
+    switch (phydev->drv->phy_id)
+    {
+        case REALTEK_PHY_ID_RTL8261N:
+        case REALTEK_PHY_ID_RTL8264B:
+            phydev_info(phydev, "%s:%u [RTL8261N/RTL826XB] phy_id: 0x%X PHYAD:%d\n", __FUNCTION__, __LINE__, phydev->drv->phy_id, phydev->mdio.addr);
+
+          #if 1 /* toggle reset */
+            phy_write_mmd(phydev, 30, 0x145, 0x0001);
+            phy_write_mmd(phydev, 30, 0x145, 0x0000);
+            mdelay(30);
+          #endif
+
+            ret = phy_patch(0, phydev, 0, PHY_PATCH_MODE_NORMAL);
+            if (ret)
+            {
+                phydev_err(phydev, "%s:%u [RTL8261N/RTL826XB] patch failed!! 0x%X\n", __FUNCTION__, __LINE__, ret);
+                return ret;
+            }
+
+            ret = rtk_phylib_826xb_intr_init(phydev);
+            if (ret)
+            {
+                phydev_err(phydev, "%s:%u [RTL8261N/RTL826XB] rtk_phylib_826xb_intr_init failed!! 0x%X\n", __FUNCTION__, __LINE__, ret);
+                return ret;
+            }
+
+            ret = rtk_macsec_init(phydev);
+            if (ret)
+            {
+                phydev_err(phydev, "%s:%u [RTL8261N/RTL826XB] rtk_macsec_init failed!! 0x%X\n", __FUNCTION__, __LINE__, ret);
+                return ret;
+            }
+            ret = rtk_phylib_826xb_sds_write(phydev, 6, 3, 15, 0, 0x88C6);
+            if (ret)
+            {
+                phydev_err(phydev, "%s:%u [RTL8261N/RTL826XB] SerDes init failed!! 0x%X\n", __FUNCTION__, __LINE__, ret);
+                return ret;
+            }
+
+          #if 0 /* Debug: patch check */
+            ret = phy_patch(0, phydev, 0, PHY_PATCH_MODE_CMP);
+            if (ret)
+            {
+                phydev_err(phydev, "%s:%u [RTL8261N/RTL826XB] phy_patch failed!! 0x%X\n", __FUNCTION__, __LINE__, ret);
+                return ret;
+            }
+            printk("[%s,%u] patch chk %s\n", __FUNCTION__, __LINE__, (ret == 0) ? "PASS" : "FAIL");
+          #endif
+          #if 0 /* Debug: USXGMII*/
+            {
+                uint32 data = 0;
+                rtk_phylib_826xb_sds_read(phydev, 0x07, 0x10, 15, 0, &data);
+                printk("[%s,%u] SDS 0x07, 0x10 : 0x%X\n", __FUNCTION__, __LINE__, data);
+                rtk_phylib_826xb_sds_read(phydev, 0x06, 0x12, 15, 0, &data);
+                printk("[%s,%u] SDS 0x06, 0x12 : 0x%X\n", __FUNCTION__, __LINE__, data);
+            }
+            {
+                u16 sdspage = 0x5, sdsreg = 0x0;
+                u16 regData = (sdspage & 0x3f) | ((sdsreg & 0x1f) << 6) | BIT(15);
+                u16 readData = 0;
+                phy_write_mmd(phydev, 30, 323, regData);
+                do
+                {
+                    udelay(10);
+                    readData = phy_read_mmd(phydev, 30, 323);
+                } while ((readData & BIT(15)) != 0);
+                readData = phy_read_mmd(phydev, 30, 322);
+                printk("[%s,%d] sds link [%s] (0x%X)\n", __FUNCTION__, __LINE__, (readData & BIT(12)) ? "UP" : "DOWN", readData);
+            }
+          #endif
+
+            break;
+        default:
+            phydev_err(phydev, "%s:%u Unknow phy_id: 0x%X\n", __FUNCTION__, __LINE__, phydev->drv->phy_id);
+            return -EPERM;
+    }
+
+    return ret;
+}
+
+static int rtkphy_c45_suspend(struct phy_device *phydev)
+{
+    int ret = 0;
+
+    ret = rtk_phylib_c45_power_low(phydev);
+
+    phydev->speed = SPEED_UNKNOWN;
+    phydev->duplex = DUPLEX_UNKNOWN;
+    phydev->pause = 0;
+    phydev->asym_pause = 0;
+
+    return ret;
+}
+
+static int rtkphy_c45_resume(struct phy_device *phydev)
+{
+    return rtk_phylib_c45_power_normal(phydev);
+}
+
+static int rtkphy_c45_config_aneg(struct phy_device *phydev)
+{
+    bool changed = false;
+    u16 reg = 0;
+    int ret = 0;
+
+    phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
+    if (phydev->autoneg == AUTONEG_DISABLE)
+    {
+        if (phydev->speed != SPEED_100)
+        {
+            return -EPERM;
+        }
+        return genphy_c45_pma_setup_forced(phydev);
+    }
+
+    ret = genphy_c45_an_config_aneg(phydev);
+    if (ret < 0)
+        return ret;
+    if (ret > 0)
+        changed = true;
+
+    reg = 0;
+    if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+                  phydev->advertising))
+        reg |= BIT(9);
+
+    if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
+                  phydev->advertising))
+        reg |= BIT(8);
+
+    ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, 0xA412,
+                     BIT(9) | BIT(8) , reg);
+    if (ret < 0)
+        return ret;
+    if (ret > 0)
+        changed = true;
+
+    return genphy_c45_check_and_restart_aneg(phydev, changed);
+}
+
+static int rtkphy_c45_aneg_done(struct phy_device *phydev)
+{
+    return genphy_c45_aneg_done(phydev);
+}
+
+static int rtkphy_c45_read_status(struct phy_device *phydev)
+{
+    int ret = 0, status = 0;
+    phydev->speed = SPEED_UNKNOWN;
+    phydev->duplex = DUPLEX_UNKNOWN;
+    phydev->pause = 0;
+    phydev->asym_pause = 0;
+
+    ret = genphy_c45_read_link(phydev);
+    if (ret)
+        return ret;
+
+    if (phydev->autoneg == AUTONEG_ENABLE)
+    {
+        linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+           phydev->lp_advertising);
+
+        ret = genphy_c45_read_lpa(phydev);
+        if (ret)
+            return ret;
+
+        status =  phy_read_mmd(phydev, 31, 0xA414);
+        if (status < 0)
+            return status;
+        linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+            phydev->lp_advertising, status & BIT(11));
+
+        phy_resolve_aneg_linkmode(phydev);
+    }
+    else
+    {
+        ret = genphy_c45_read_pma(phydev);
+    }
+
+    /* mdix*/
+    status = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBT_SWAPPOL);
+    if (status < 0)
+        return status;
+
+    switch (status & 0x3)
+    {
+        case MDIO_PMA_10GBT_SWAPPOL_ABNX | MDIO_PMA_10GBT_SWAPPOL_CDNX:
+            phydev->mdix = ETH_TP_MDI;
+            break;
+
+        case 0:
+            phydev->mdix = ETH_TP_MDI_X;
+            break;
+
+        default:
+            phydev->mdix = ETH_TP_MDI_INVALID;
+            break;
+    }
+
+    return ret;
+}
+
+static int rtkphy_c45_pcs_loopback(struct phy_device *phydev, bool enable)
+{
+    return rtk_phylib_c45_pcs_loopback(phydev, (enable == true) ? 1 : 0);
+}
+
+static int rtl826xb_cable_test_start(struct phy_device *phydev)
+{
+    return rtk_phylib_826xb_cable_test_start(phydev);
+}
+
+static int rtl826xb_cable_test_get_status(struct phy_device *phydev, bool *finished)
+{
+    uint32 finish_read = 0;
+    int32 ret = 0;
+    uint32 pair = 0;
+    rtk_rtct_channel_result_t reslut;
+
+    *finished = false;
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_cable_test_finished_get(phydev, &finish_read));
+    *finished = (finish_read == 1) ? true : false;
+
+    if (finish_read == 1)
+    {
+        for (pair = 0; pair < 4; pair++)
+        {
+            RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_cable_test_result_get(phydev, pair, &reslut));
+            ethnl_cable_test_result(phydev, pair, rtk_phy_cable_test_report_trans(&reslut));
+
+            if(reslut.cable_status != RTK_PHYLIB_CABLE_STATUS_NORMAL)
+                ethnl_cable_test_fault_length(phydev, pair, reslut.length_cm);
+        }
+    }
+    return ret;
+}
+
+static int rtl826xb_config_intr(struct phy_device *phydev)
+{
+    int32 ret = 0;
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_intr_enable(phydev, (phydev->interrupts == PHY_INTERRUPT_ENABLED)? 1 : 0));
+    return ret;
+}
+
+static int rtl826xb_ack_intr(struct phy_device *phydev)
+{
+    int32 ret = 0;
+    uint32 status = 0;
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_intr_read_clear(phydev, &status));
+    if (status & RTK_PHY_INTR_WOL)
+    {
+        rtk_phylib_826xb_wol_reset(phydev);
+    }
+
+    return ret;
+}
+
+static irqreturn_t rtl826xb_handle_intr(struct phy_device *phydev)
+{
+    irqreturn_t ret;
+    uint32 status = 0;
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_intr_read_clear(phydev, &status));
+    if (status & RTK_PHY_INTR_LINK_CHANGE)
+    {
+        pr_debug("[%s,%d] RTK_PHY_INTR_LINK_CHANGE\n", __FUNCTION__, __LINE__);
+        phy_mac_interrupt(phydev);
+    }
+
+    if (status & RTK_PHY_INTR_WOL)
+    {
+        pr_debug("[%s,%d] RTK_PHY_INTR_WOL\n", __FUNCTION__, __LINE__);
+        rtk_phylib_826xb_wol_reset(phydev);
+    }
+
+    return IRQ_HANDLED;
+}
+
+static int rtl826xb_get_tunable(struct phy_device *phydev, struct ethtool_tunable *tuna, void *data)
+{
+    int32 ret = 0;
+    uint32 val = 0;
+
+    switch (tuna->id)
+    {
+        case ETHTOOL_PHY_EDPD:
+            RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_link_down_power_saving_get(phydev, &val));
+            *(u16 *)data = (val == 0) ? ETHTOOL_PHY_EDPD_DISABLE : ETHTOOL_PHY_EDPD_DFLT_TX_MSECS;
+            return 0;
+
+        default:
+            return -EOPNOTSUPP;
+    }
+}
+
+static int rtl826xb_set_tunable(struct phy_device *phydev, struct ethtool_tunable *tuna, const void *data)
+{
+    int32 ret = 0;
+    uint32 val = 0;
+
+    switch (tuna->id)
+    {
+        case ETHTOOL_PHY_EDPD:
+            switch (*(const u16 *)data)
+            {
+                case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS:
+                    val = 1;
+                    break;
+                case ETHTOOL_PHY_EDPD_DISABLE:
+                    val = 0;
+                    break;
+                default:
+                    return -EINVAL;
+            }
+            RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_link_down_power_saving_set(phydev, val));
+            return 0;
+
+        default:
+            return -EOPNOTSUPP;
+    }
+}
+
+static int rtl826xb_set_wol(struct phy_device *phydev,
+              struct ethtool_wolinfo *wol)
+{
+    int32 ret = 0;
+    uint8 *mac_addr = NULL;
+    uint32 rtk_wol_opts = 0;
+
+    struct net_device *ndev = phydev->attached_dev;
+    if (!ndev)
+        return RTK_PHYLIB_ERR_FAILED;
+
+    if (wol->wolopts & ~( WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST))
+        return -EOPNOTSUPP;
+
+    if (wol->wolopts & (WAKE_MAGIC | WAKE_UCAST))
+    {
+        mac_addr = (uint8 *) ndev->dev_addr;
+        RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_wol_unicast_addr_set(phydev, mac_addr));
+    }
+
+    if (wol->wolopts & WAKE_MCAST)
+    {
+        RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_wol_multicast_mask_reset(phydev));
+
+        if (!netdev_mc_empty(ndev))
+        {
+            struct netdev_hw_addr *ha;
+            netdev_for_each_mc_addr(ha, ndev)
+            {
+                pr_info("[%s,%d] mac: %pM \n", __FUNCTION__, __LINE__, ha->addr);
+                RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_wol_multicast_mask_add(phydev, rtk_phylib_826xb_wol_multicast_mac2offset(ha->addr)));
+            }
+        }
+    }
+
+    if (wol->wolopts & WAKE_PHY)
+        rtk_wol_opts |= RTK_WOL_OPT_LINK;
+    if (wol->wolopts & WAKE_MAGIC)
+        rtk_wol_opts |= RTK_WOL_OPT_MAGIC;
+    if (wol->wolopts & WAKE_UCAST)
+        rtk_wol_opts |= RTK_WOL_OPT_UCAST;
+    if (wol->wolopts & WAKE_BCAST)
+        rtk_wol_opts |= RTK_WOL_OPT_BCAST;
+    if (wol->wolopts & WAKE_MCAST)
+        rtk_wol_opts |= RTK_WOL_OPT_MCAST;
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_wol_set(phydev, rtk_wol_opts));
+
+    return 0;
+}
+
+
+static void rtl826xb_get_wol(struct phy_device *phydev,
+               struct ethtool_wolinfo *wol)
+{
+    int32 ret = 0;
+    uint32 rtk_wol_opts = 0;
+
+    wol->supported = WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST;
+    wol->wolopts = 0;
+
+    ret = rtk_phylib_826xb_wol_get(phydev, &rtk_wol_opts);
+    if (ret != 0)
+        return;
+
+    if (rtk_wol_opts & RTK_WOL_OPT_LINK)
+        wol->wolopts |= WAKE_PHY;
+    if (rtk_wol_opts & RTK_WOL_OPT_MAGIC)
+        wol->wolopts |= WAKE_MAGIC;
+    if (rtk_wol_opts & RTK_WOL_OPT_UCAST)
+        wol->wolopts |= WAKE_UCAST;
+    if (rtk_wol_opts & RTK_WOL_OPT_MCAST)
+        wol->wolopts |= WAKE_MCAST;
+    if (rtk_wol_opts & RTK_WOL_OPT_BCAST)
+        wol->wolopts |= WAKE_BCAST;
+}
+
+static struct phy_driver rtk_phy_drivers[] = {
+    {
+        PHY_ID_MATCH_EXACT(REALTEK_PHY_ID_RTL8261N),
+        .name               = "Realtek RTL8261N/8261BE/8251L",
+        .get_features       = rtl826xb_get_features,
+        .config_init        = rtkphy_config_init,
+        .probe              = rtl826xb_probe,
+        .suspend            = rtkphy_c45_suspend,
+        .resume             = rtkphy_c45_resume,
+        .config_aneg        = rtkphy_c45_config_aneg,
+        .aneg_done          = rtkphy_c45_aneg_done,
+        .read_status        = rtkphy_c45_read_status,
+        .set_loopback       = rtkphy_c45_pcs_loopback,
+        .cable_test_start      = rtl826xb_cable_test_start,
+        .cable_test_get_status = rtl826xb_cable_test_get_status,
+        .config_intr        = rtl826xb_config_intr,
+        .ack_interrupt      = rtl826xb_ack_intr,
+        .handle_interrupt   = rtl826xb_handle_intr,
+        .get_tunable        = rtl826xb_get_tunable,
+        .set_tunable        = rtl826xb_set_tunable,
+        .set_wol            = rtl826xb_set_wol,
+        .get_wol            = rtl826xb_get_wol,
+    },
+    {
+        PHY_ID_MATCH_EXACT(REALTEK_PHY_ID_RTL8264B),
+        .name               = "Realtek RTL8264B/8254B",
+        .get_features       = rtl826xb_get_features,
+        .config_init        = rtkphy_config_init,
+        .probe              = rtl826xb_probe,
+        .suspend            = rtkphy_c45_suspend,
+        .resume             = rtkphy_c45_resume,
+        .config_aneg        = rtkphy_c45_config_aneg,
+        .aneg_done          = rtkphy_c45_aneg_done,
+        .read_status        = rtkphy_c45_read_status,
+        .set_loopback       = rtkphy_c45_pcs_loopback,
+        .cable_test_start      = rtl826xb_cable_test_start,
+        .cable_test_get_status = rtl826xb_cable_test_get_status,
+        .config_intr        = rtl826xb_config_intr,
+        .ack_interrupt      = rtl826xb_ack_intr,
+        .handle_interrupt   = rtl826xb_handle_intr,
+        .get_tunable        = rtl826xb_get_tunable,
+        .set_tunable        = rtl826xb_set_tunable,
+        .set_wol            = rtl826xb_set_wol,
+        .get_wol            = rtl826xb_get_wol,
+    },
+    {
+        PHY_ID_MATCH_EXACT(REALTEK_PHY_ID_RTL8224),
+        .name               = "Realtek RTL8224/8224N",
+        .get_features       = rtl8224_get_features,
+        .config_init        = rtl8224_config_init,
+        .probe              = rtl8224_probe,
+        .suspend            = rtkphy_c45_suspend,
+        .resume             = rtkphy_c45_resume,
+        .config_aneg        = rtkphy_c45_config_aneg,
+        .aneg_done          = rtkphy_c45_aneg_done,
+        .read_status        = rtkphy_c45_read_status,
+        .set_loopback       = rtkphy_c45_pcs_loopback,
+        .cable_test_start      = rtl8224_cable_test_start,
+        .cable_test_get_status = rtl8224_cable_test_get_status,
+        .get_tunable        = rtl8224_get_tunable,
+        .set_tunable        = rtl8224_set_tunable,
+        .config_intr        = rtl8224_config_intr,
+        .ack_interrupt      = rtl8224_ack_intr,
+        .handle_interrupt   = rtl8224_handle_intr,
+    },
+};
+
+module_phy_driver(rtk_phy_drivers);
+
+
+static struct mdio_device_id __maybe_unused rtk_phy_tbl[] = {
+    { PHY_ID_MATCH_EXACT(REALTEK_PHY_ID_RTL8261N) },
+    { PHY_ID_MATCH_EXACT(REALTEK_PHY_ID_RTL8264B) },
+    { PHY_ID_MATCH_EXACT(REALTEK_PHY_ID_RTL8224) },
+    { },
+};
+
+MODULE_DEVICE_TABLE(mdio, rtk_phy_tbl);
+
+MODULE_AUTHOR("Realtek");
+MODULE_DESCRIPTION("Realtek PHY drivers");
+MODULE_LICENSE("GPL");
diff --git a/sources/rtk-gp3000/src/hal/phy/rtk_phy.h b/sources/rtk-gp3000/src/hal/phy/rtk_phy.h
new file mode 100644
index 00000000..4e2536f6
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/rtk_phy.h
@@ -0,0 +1,22 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
+ */
+
+#define REALTEK_PHY_ID_RTL8261N         0x001CCAF3
+#define REALTEK_PHY_ID_RTL8264B         0x001CC813
+#define REALTEK_PHY_ID_RTL8224          0x001CCAD0
+
+
+#if IS_ENABLED(CONFIG_MACSEC)
+int rtk_macsec_init(struct phy_device *phydev);
+#else
+static inline int rtk_macsec_init(struct phy_device *phydev)
+{
+	return 0;
+}
+#endif
+
+
+
diff --git a/sources/rtk-gp3000/src/hal/phy/rtk_phy_rtl8224.c b/sources/rtk-gp3000/src/hal/phy/rtk_phy_rtl8224.c
new file mode 100644
index 00000000..f687beb8
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/rtk_phy_rtl8224.c
@@ -0,0 +1,573 @@
+
+#include <linux/phy.h>
+#include <linux/ethtool.h>
+#include <linux/ethtool_netlink.h>
+#include "rtk_phylib.h"
+#include "rtk_phy.h"
+#include "rtk_phylib_rtl8224.h"
+#include "rtk_phy_rtl8224.h"
+#include "phy_rtl8224_patch.h"
+#include "error.h"
+#include "rtk_osal.h"
+
+//#define RTL8224_INTERNAL_INFO                1
+
+#ifdef RTL8224_INTERNAL_INFO
+#define RTL8224_INTERNAL_PORT_CHECK(port)\
+                            do{\
+                                printk("\n[%s] addr(%d)\n",__FUNCTION__,port->mdio.addr);\
+                            }while(0)
+#else
+#define RTL8224_INTERNAL_PORT_CHECK(port)\
+                            do{\
+                            }while(0)
+#endif
+
+static int _phy_8224_cable_test_report_trans(uint32 pair, rtk_rtctResult_t *result)
+{
+    switch(pair)
+    {
+        case 0:
+            if(result->un.ge_result.channelAShort)
+                return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
+            if(result->un.ge_result.channelAOpen)
+                return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
+            if(result->un.ge_result.channelAMismatch)
+                return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
+            if(result->un.ge_result.channelAPairBusy)
+                return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
+            break;
+        case 1:
+            if(result->un.ge_result.channelBShort)
+                return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
+            if(result->un.ge_result.channelBOpen)
+                return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
+            if(result->un.ge_result.channelBMismatch)
+                return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
+            if(result->un.ge_result.channelBPairBusy)
+                return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
+            break;
+        case 2:
+            if(result->un.ge_result.channelCShort)
+                return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
+            if(result->un.ge_result.channelCOpen)
+                return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
+            if(result->un.ge_result.channelCMismatch)
+                return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
+            if(result->un.ge_result.channelCPairBusy)
+                return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
+            break;
+        case 3:
+            if(result->un.ge_result.channelDShort)
+                return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
+            if(result->un.ge_result.channelDOpen)
+                return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
+            if(result->un.ge_result.channelDMismatch)
+                return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
+            if(result->un.ge_result.channelDPairBusy)
+                return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
+
+            break;
+        default:
+            return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
+
+    }
+    return ETHTOOL_A_CABLE_RESULT_CODE_OK;
+}
+
+static int _phy_8224_cable_test_length_get(uint32 pair, rtk_rtctResult_t *result, uint32 *length_cm)
+{
+    switch(pair)
+    {
+        case 0:
+            if(result->un.ge_result.channelAShort)
+                return -1;
+            if(result->un.ge_result.channelAOpen)
+                return -1;
+            if(result->un.ge_result.channelAMismatch)
+                return -1;
+            if(result->un.ge_result.channelAPairBusy)
+                return -1;
+            *length_cm = result->un.ge_result.channelALen;
+            break;
+        case 1:
+            if(result->un.ge_result.channelBShort)
+                return -1;
+            if(result->un.ge_result.channelBOpen)
+                return -1;
+            if(result->un.ge_result.channelBMismatch)
+                return -1;
+            if(result->un.ge_result.channelBPairBusy)
+                return -1;
+            *length_cm = result->un.ge_result.channelBLen;
+            break;
+        case 2:
+            if(result->un.ge_result.channelCShort)
+                return -1;
+            if(result->un.ge_result.channelCOpen)
+                return -1;
+            if(result->un.ge_result.channelCMismatch)
+                return -1;
+            if(result->un.ge_result.channelCPairBusy)
+                return -1;
+            *length_cm = result->un.ge_result.channelCLen;
+            break;
+        case 3:
+            if(result->un.ge_result.channelDShort)
+                return -1;
+            if(result->un.ge_result.channelDOpen)
+                return -1;
+            if(result->un.ge_result.channelDMismatch)
+                return -1;
+            if(result->un.ge_result.channelDPairBusy)
+                return -1;
+            *length_cm = result->un.ge_result.channelDLen;
+            break;
+        default:
+            return -1;
+
+    }
+    return 0;
+}
+
+static int _phy_8224_dbCompleted_check(struct phy_device *phydev)
+{
+    struct rtl8224_priv_info *priv = (struct rtl8224_priv_info *)phydev->priv;
+    struct phy_device *base_phydev = NULL;
+    struct rtl8224_priv_info *base_priv = NULL;
+    struct phy_device *tmp_phydev = NULL;
+    struct rtl8224_priv_info *tmp_priv = NULL;
+    int phy_addr, loop, ret = 0;
+
+
+    base_phydev = priv->basePort;
+    base_priv = (struct rtl8224_priv_info *)base_phydev->priv;
+    phy_addr = base_phydev->mdio.addr;
+
+    for(loop = 0; loop < RTL8224_PORT_NUM; loop++)
+    {
+        tmp_phydev = mdiobus_get_phy(base_phydev->mdio.bus, (phy_addr + loop));
+        tmp_priv = (struct rtl8224_priv_info *)tmp_phydev->priv;
+
+        if((loop == 0) && (tmp_phydev != base_phydev))
+        {
+            PR_ERR("[%d][loop %d] base port is WRONG!!!",__LINE__,loop);
+            ret = -1;
+            goto db_not_ready;
+        }
+
+        if(tmp_phydev != base_priv->memberPort[loop])
+        {
+            PR_ERR("[%d][loop %d] member port is WRONG!!!",__LINE__,loop);
+            ret = -2;
+            goto db_not_ready;
+        }
+
+        if(tmp_priv->port_offset != loop)
+        {
+            PR_ERR("[%d][loop %d] port offset is WRONG!!!",__LINE__,loop);
+            ret = -3;
+            goto db_not_ready;
+        }
+
+        if((tmp_priv->is_basePort != 0) && (loop != 0))
+        {
+            PR_ERR("[%d][loop %d] is_basePort is WRONG!!!",__LINE__,loop);
+            ret = -4;
+            goto db_not_ready;
+        }
+
+    }
+
+    return ret;
+db_not_ready:
+    PR_ERR("[%d][loop %d] dbCompleted is NOT Ready!!!",__LINE__,loop);
+
+    return ret;
+}
+
+/* updated base port db*/
+static struct phy_device *phy_8224_basePort_db_updated(struct phy_device *phydev, int *reg_data1, int *reg_data2)
+{
+    struct rtl8224_priv_info *phy_priv = (struct rtl8224_priv_info *)phydev->priv;
+
+    *reg_data1 =  phy_read_mmd(phydev, 30, 0x4);
+    if (*reg_data1 < 0)
+        goto bus_read_error;
+    *reg_data2 =  phy_read_mmd(phydev, 30, 0x5);
+    if (*reg_data2 < 0)
+        goto bus_read_error;
+
+    if(*reg_data2 == 0x8224) /* base port match */
+    {
+        phy_priv->basePort = phydev;
+        phy_priv->is_basePort = 1;
+        phy_priv->port_offset = 0;
+        phy_priv->memberPort[RTL8224_BASE_PORT_OFFSET]= phydev;
+        if(*reg_data1 == 0x0)
+            phy_priv->phytype = RTK_PHYLIB_RTL8224;
+        else if(*reg_data1 == 0x7000)
+            phy_priv->phytype = RTK_PHYLIB_RTL8224N;
+        else
+            goto basePort_match_error;
+    }
+    else
+    {
+        phy_priv->is_basePort = 0;
+        return NULL;
+    }
+    return phydev;
+bus_read_error:
+    PR_ERR("\n[%s] read error!\n",__FUNCTION__);
+    return NULL;
+basePort_match_error:
+    PR_ERR("\n[%s] base port match error!\n",__FUNCTION__);
+    return NULL;
+}
+
+/* updated member port db*/
+int phy_8224_member_db_updated(struct phy_device *phydev)
+{
+    struct rtl8224_priv_info *phy_priv = (struct rtl8224_priv_info *)phydev->priv;
+    struct phy_device *tmp_phydev = NULL;
+    struct rtl8224_priv_info *temp_priv;
+    int index = RTL8224_PORT_NUM;
+    int port_offset = 0;
+    int phy_addr = phydev->mdio.addr;
+
+    /* base port's phy address is the first always, */
+    /* and 4 phy addresses are continuous */
+    while(index > 0)
+    {
+        phy_addr--;
+        index --;
+        tmp_phydev = mdiobus_get_phy(phydev->mdio.bus, phy_addr); /* get other port's phy device by phy address*/
+        temp_priv = (struct rtl8224_priv_info *)tmp_phydev->priv;
+        if(tmp_phydev == NULL)
+        {
+            /* to find next one */
+            continue;
+        }
+        else
+        {
+            if(temp_priv->is_basePort == 1)
+            {
+                /* Record base port*/
+                phy_priv->basePort = tmp_phydev;
+                /* Record member port*/
+                phy_priv->memberPort[RTL8224_BASE_PORT_OFFSET] = tmp_phydev;
+                /* port offset */
+                port_offset = (phydev->mdio.addr - tmp_phydev->mdio.addr);
+                phy_priv->memberPort[port_offset] = phydev;
+                phy_priv->port_offset = port_offset;
+                /* updated base port's member port db */
+                temp_priv->memberPort[port_offset] = phydev;
+
+                return 0;
+            }
+        }
+    }
+    PR_ERR("\n[%s](PHY addr %d) FAILED!!!\n",__FUNCTION__,phydev->mdio.addr);
+    return -1;
+}
+
+int rtl8224_probe(struct phy_device *phydev)
+{
+    struct rtl8224_priv_info *priv = NULL;
+    int reg_data1 = 0, reg_data2 = 0, db_ret = 0, tmp_base = 1;
+    struct phy_device *tmp_phydev = NULL;
+    struct rtl8224_priv_info *tmp_priv;
+
+    RTL8224_INTERNAL_PORT_CHECK(phydev);
+
+    priv = kmalloc(sizeof(struct rtl8224_priv_info), GFP_KERNEL);
+    if (!priv)
+    {
+        return -ENOMEM;
+    }
+    memset(priv, 0, sizeof(struct rtl8224_priv_info));
+    phydev->priv = priv;
+
+    if (phydev->drv->phy_id == REALTEK_PHY_ID_RTL8224)
+    {
+        tmp_phydev = phy_8224_basePort_db_updated(phydev, &reg_data1, &reg_data2);
+        /* updated member port db */
+        if(tmp_phydev == NULL)
+        {
+             tmp_base = 0;
+             db_ret = phy_8224_member_db_updated(phydev);
+             if(db_ret)
+                goto match_error;
+        }
+    }
+    else
+    {
+        goto match_error;
+    }
+    tmp_priv = (struct rtl8224_priv_info *)phydev->priv;
+
+    phydev->priv = priv;
+    return 0;
+match_error:
+    PR_ERR("[%s] probe miss MATCH!!!\n",__FUNCTION__);
+    devm_kfree(&phydev->mdio.dev, priv);
+    return -ENXIO;
+}
+
+
+int rtl8224_get_features(struct phy_device *phydev)
+{
+    int ret;
+    RTL8224_INTERNAL_PORT_CHECK(phydev);
+
+    ret = genphy_c45_pma_read_abilities(phydev);
+    if (ret)
+        return ret;
+
+    linkmode_or(phydev->supported, phydev->supported, PHY_BASIC_FEATURES);
+
+    linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
+                       phydev->supported);
+
+    /* not support 10M modes */
+    linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
+                       phydev->supported);
+    linkmode_clear_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
+                       phydev->supported);
+
+    return 0;
+}
+
+
+int rtl8224_config_init(struct phy_device *phydev)
+{
+    struct rtl8224_priv_info *priv = (struct rtl8224_priv_info *)phydev->priv;
+    struct rtl8224_priv_info *tmp_priv = NULL;
+    int ret = 0, loop = 0;
+    int32   unit = 0;
+    rtk_port_t port;
+    RTL8224_INTERNAL_PORT_CHECK(phydev);
+
+    ret = _phy_8224_dbCompleted_check(phydev);
+    if(ret)
+        PR_ERR("\n PHY data base is NOT completed\n");
+
+    if(priv->is_basePort == 1)
+    {
+        PR_INFO("\n Base port (phy_addr %d), execute patch...\n",phydev->mdio.addr);
+
+        for (loop = 0; loop < RTL8224_PORT_NUM; loop++)
+        {
+            if ((port = _phy_8224_get_phydevice_by_offset(unit, phydev, loop)) == NULL)
+            {
+                PR_ERR("\n Offset(%d) PHY device cannot get\n",loop);
+                return -1;
+            }
+            tmp_priv = (struct rtl8224_priv_info *)port->priv;
+
+            phy_rtl8224_patch(unit, port, loop);
+            _phy_8224_mdi_reverse_set(port, RTL8224_MDI_PIN_SWAP);
+
+            if ((RTL8224_MDI_PAIR_SWAP) != 0)
+            {
+                _phy_8224_tx_polarity_swap_set(port, RTL8224_MDI_PAIR_SWAP);
+            }
+            _phy_8224_interrupt_init(unit, port);
+        }
+        PR_INFO("\n Base port (phy_addr %d), path completed!\n",phydev->mdio.addr);
+    }
+    else
+    {
+        PR_INFO("\n(phy_addr %d) is member port\n", phydev->mdio.addr);
+    }
+
+    return ret;
+}
+
+int
+rtl8224_cable_test_start(struct phy_device *phydev)
+{
+    int32   ret = RT_ERR_OK;
+    uint32  unit = 0;
+    uint32  phyData = 0, speed = 0, duplex = 0;
+    uint32  tryTime = 1000;
+    rtk_enable_t ena;
+    rtk_port_t port = phydev;
+    RTL8224_INTERNAL_PORT_CHECK(phydev);
+
+    if ((ret = _phy_8224_common_c45_enable_get(unit, port, &ena)) != RT_ERR_OK)
+        return ret;
+
+    if (ena == DISABLED)
+    {
+        return RT_ERR_OPER_DENIED;
+    }
+
+    /* Check the port is link up or not?
+     * Due to bit 2 is LL(latching low), need to read twice to get current status
+     */
+    if ((ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_PMAPMD, 0x1, &phyData)) != RT_ERR_OK)
+        return ret;
+    if ((ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_PMAPMD, 0x1, &phyData)) != RT_ERR_OK)
+        return ret;
+
+    _phy_8224_common_c45_speedDuplexStatusResReg_get(unit, port, &speed, &duplex);
+    if (phyData & BIT_2)
+    {
+        if (speed == PORT_SPEED_10M)
+        {
+            return RT_ERR_PORT_NOT_SUPPORTED;
+        }
+
+        return RT_ERR_OK;
+    }
+    else
+    {
+	    if ((ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_VEND2, 0xA400, &phyData)) != RT_ERR_OK)
+	        return ret;
+	    phyData |= (BIT_9); //[9]=1
+	    if ((ret = phy_common_general_reg_mmd_set(unit, port, PHY_MMD_VEND2, 0xA400, phyData)) != RT_ERR_OK)
+	        return ret;
+
+	    osal_time_mdelay(500);
+
+	    if ((ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_VEND2, 0xA422, &phyData)) != RT_ERR_OK)
+	        return ret;
+	    phyData &= (~BIT_15); //[15]=0
+	    phyData |= (BIT_1); //[1]=1
+	    if ((ret = phy_common_general_reg_mmd_set(unit, port, PHY_MMD_VEND2, 0xA422, phyData)) != RT_ERR_OK)
+	        return ret;
+
+	    phyData |= (BIT_4 | BIT_5 | BIT_6 | BIT_7); //[7:4]=0xf
+	    if ((ret = phy_common_general_reg_mmd_set(unit, port, PHY_MMD_VEND2, 0xA422, phyData)) != RT_ERR_OK)
+	        return ret;
+
+	    phyData |= (BIT_0); //[0]=0x1
+	    if ((ret = phy_common_general_reg_mmd_set(unit, port, PHY_MMD_VEND2, 0xA422, phyData)) != RT_ERR_OK)
+	        return ret;
+
+	    if ((ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_VEND2, 0xA422, &phyData)) != RT_ERR_OK)
+	        return ret;
+
+	    while((phyData & BIT_15) == 0)
+	    {
+	        osal_time_mdelay(10);
+	        if ((ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_VEND2, 0xA422, &phyData)) != RT_ERR_OK)
+	            return ret;
+	        tryTime--;
+	        if(tryTime == 0)
+	            return RT_ERR_NOT_FINISH;
+	    }
+    }
+    return ret;
+}
+
+int rtl8224_cable_test_get_status(struct phy_device *phydev, bool *finished)
+{
+    int32 ret = 0;
+    uint32 pair = 0, unit = 0, length_cm;
+    rtk_rtctResult_t result;
+    RTL8224_INTERNAL_PORT_CHECK(phydev);
+
+    *finished = false;
+    ret = _phy_8224_rtctResult_get(unit, phydev, &result);
+    if(ret == 0)
+        *finished = true;
+
+    for (pair = 0; pair < 4; pair++)
+    {
+        ethnl_cable_test_result(phydev, pair, _phy_8224_cable_test_report_trans(pair, &result));
+
+        if(_phy_8224_cable_test_length_get(pair, &result, &length_cm))
+            ethnl_cable_test_fault_length(phydev, pair, length_cm);
+
+    }
+    return 0;
+}
+
+int rtl8224_get_tunable(struct phy_device *phydev, struct ethtool_tunable *tuna, void *data)
+{
+    int32 ret = 0;
+    rtk_enable_t val = 0;
+    uint32 unit = 0;
+    RTL8224_INTERNAL_PORT_CHECK(phydev);
+
+    switch (tuna->id)
+    {
+        case ETHTOOL_PHY_EDPD:
+            RTK_PHYLIB_ERR_CHK(phy_8224_linkDownPowerSavingEnable_get(unit, phydev, &val));
+            *(u16 *)data = (val == DISABLED) ? ETHTOOL_PHY_EDPD_DISABLE : ETHTOOL_PHY_EDPD_DFLT_TX_MSECS;
+            return 0;
+
+        default:
+            return -EOPNOTSUPP;
+    }
+}
+
+int rtl8224_set_tunable(struct phy_device *phydev, struct ethtool_tunable *tuna, const void *data)
+{
+    int32 ret = 0;
+    rtk_enable_t val = DISABLED;
+    uint32 unit = 0;
+    RTL8224_INTERNAL_PORT_CHECK(phydev);
+
+    switch (tuna->id)
+    {
+        case ETHTOOL_PHY_EDPD:
+            switch (*(const u16 *)data)
+            {
+                case ETHTOOL_PHY_EDPD_DISABLE:
+                    val = DISABLED;
+                    break;
+                default:
+                    val = ENABLED;
+                    break;
+            }
+            RTK_PHYLIB_ERR_CHK(phy_8224_linkDownPowerSavingEnable_set(unit, phydev, val));
+            return 0;
+
+        default:
+            return -EOPNOTSUPP;
+    }
+}
+
+int rtl8224_config_intr(struct phy_device *phydev)
+{
+    int32 ret = 0;
+
+    RTL8224_INTERNAL_PORT_CHECK(phydev);
+
+    RTK_PHYLIB_ERR_CHK(_phy_8224_intr_enable(phydev, (phydev->interrupts == PHY_INTERRUPT_ENABLED)? 1 : 0));
+
+    return ret;
+}
+
+int rtl8224_ack_intr(struct phy_device *phydev)
+{
+    int32 ret = 0;
+    uint32 status = 0;
+
+    RTL8224_INTERNAL_PORT_CHECK(phydev);
+
+    RTK_PHYLIB_ERR_CHK(_phy_8224_intr_read_clear(phydev, &status));
+
+    return ret;
+}
+
+irqreturn_t rtl8224_handle_intr(struct phy_device *phydev)
+{
+    irqreturn_t ret;
+    uint32 status = 0;
+
+    RTL8224_INTERNAL_PORT_CHECK(phydev);
+
+    RTK_PHYLIB_ERR_CHK(_phy_8224_intr_read_clear(phydev, &status));
+    if (status & BIT_4)
+    {
+        PR_INFO("[%s,%d] RTK_PHY_INTR_LINK_CHANGE\n", __FUNCTION__, __LINE__);
+        phy_mac_interrupt(phydev);
+    }
+
+    return IRQ_HANDLED;
+}
+
diff --git a/sources/rtk-gp3000/src/hal/phy/rtk_phy_rtl8224.h b/sources/rtk-gp3000/src/hal/phy/rtk_phy_rtl8224.h
new file mode 100644
index 00000000..86d24444
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/rtk_phy_rtl8224.h
@@ -0,0 +1,13 @@
+
+
+extern int rtl8224_probe(struct phy_device *phydev);
+extern int rtl8224_get_features(struct phy_device *phydev);
+extern int rtl8224_config_init(struct phy_device *phydev);
+extern int rtl8224_cable_test_start(struct phy_device *phydev);
+extern int rtl8224_cable_test_get_status(struct phy_device *phydev, bool *finished);
+extern int rtl8224_get_tunable(struct phy_device *phydev, struct ethtool_tunable *tuna, void *data);
+extern int rtl8224_set_tunable(struct phy_device *phydev, struct ethtool_tunable *tuna, const void *data);
+extern int rtl8224_config_intr(struct phy_device *phydev);
+extern int rtl8224_ack_intr(struct phy_device *phydev);
+extern irqreturn_t rtl8224_handle_intr(struct phy_device *phydev);
+
diff --git a/sources/rtk-gp3000/src/hal/phy/rtk_phylib.c b/sources/rtk-gp3000/src/hal/phy/rtk_phylib.c
new file mode 100644
index 00000000..ca6b9a65
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/rtk_phylib.c
@@ -0,0 +1,117 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
+ */
+
+#include "rtk_phylib.h"
+#include <linux/phy.h>
+
+
+/* OSAL */
+
+void rtk_phylib_mdelay(uint32 msec)
+{
+#if defined(RTK_PHYDRV_IN_LINUX)
+    mdelay(msec);
+#else
+    osal_time_mdelay(msec);
+#endif
+}
+
+
+void rtk_phylib_udelay(uint32 usec)
+{
+#if defined(RTK_PHYDRV_IN_LINUX)
+    if (1000 <= usec)
+    {
+        mdelay(usec/1000);
+        usec = usec % 1000;
+    }
+    udelay(usec);
+#else
+    osal_time_udelay(usec);
+#endif
+}
+
+int32 rtk_phylib_time_usecs_get(uint32 *pUsec)
+{
+    struct timespec64 ts;
+
+    if(NULL == pUsec)
+        return RTK_PHYLIB_ERR_INPUT;
+
+    ktime_get_ts64(&ts);
+    *pUsec = ((ts.tv_sec * USEC_PER_SEC) + (ts.tv_nsec / NSEC_PER_USEC));
+    return 0;
+}
+
+/* Register Access APIs */
+int32 rtk_phylib_mmd_write(rtk_phydev *phydev, uint32 mmd, uint32 reg, uint8 msb, uint8 lsb, uint32 data)
+{
+    int32  ret = 0;
+    uint32 mask = 0;
+    mask = UINT32_BITS_MASK(msb,lsb);
+
+#if defined(RTK_PHYDRV_IN_LINUX)
+    ret = phy_modify_mmd(phydev, mmd, reg, mask, (data << lsb));
+#else
+    {
+        uint32 rData = 0, wData = 0;
+        if ((msb != 15) || (lsb != 0))
+        {
+            if ((ret = phy_common_general_reg_mmd_get(phydev->unit, phydev->port, page, reg, &rData)) != RT_ERR_OK)
+                return ret;
+        }
+        wData = REG32_FIELD_SET(rData, data, lsb, mask);
+        ret = phy_common_general_reg_mmd_set(phydev->unit, phydev->port, page, reg, wData);
+    }
+#endif
+
+    return ret;
+}
+
+int32 rtk_phylib_mmd_read(rtk_phydev *phydev, uint32 mmd, uint32 reg, uint8 msb, uint8 lsb, uint32 *pData)
+{
+    int32  ret = 0;
+    uint32 rData = 0;
+    uint32 mask = 0;
+    mask = UINT32_BITS_MASK(msb,lsb);
+
+#if defined(RTK_PHYDRV_IN_LINUX)
+    rData =  phy_read_mmd(phydev, mmd, reg);
+#else
+    {
+        ret = phy_common_general_reg_mmd_get(phydev->unit, phydev->port, page, reg, &rData);
+    }
+#endif
+
+    *pData = REG32_FIELD_GET(rData, lsb, mask);
+    return ret;
+}
+
+/* Function Driver */
+
+int32 rtk_phylib_c45_power_normal(rtk_phydev *phydev)
+{
+    int32  ret = 0;
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 1, 0, 11, 11, 0));
+
+    return 0;
+}
+
+int32 rtk_phylib_c45_power_low(rtk_phydev *phydev)
+{
+    int32  ret = 0;
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 1, 0, 11, 11, 1));
+
+    return 0;
+}
+
+int32 rtk_phylib_c45_pcs_loopback(rtk_phydev *phydev, uint32 enable)
+{
+    int32  ret = 0;
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 3, 0, 14, 14, (enable == 0) ? 0 : 1));
+
+    return 0;
+}
diff --git a/sources/rtk-gp3000/src/hal/phy/rtk_phylib.h b/sources/rtk-gp3000/src/hal/phy/rtk_phylib.h
new file mode 100644
index 00000000..8e1b7034
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/rtk_phylib.h
@@ -0,0 +1,389 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
+ */
+
+#ifndef __RTK_PHYLIB_H
+#define __RTK_PHYLIB_H
+
+#if defined(RTK_PHYDRV_IN_LINUX)
+  #include <linux/phy.h>
+  #include "type.h"
+  #include "rtk_phylib_def.h"
+#else
+  //#include SDK headers
+#endif
+
+#if defined(DEBUG)
+  #define MACSEC_DBG_PRINT 1
+#endif
+
+#if defined(RTK_PHYDRV_IN_LINUX)
+  #define PR_INFO(_fmt, _args...) pr_info(_fmt, ##_args)
+  #define PR_DBG(_fmt, _args...)  pr_debug(_fmt, ##_args)
+  #define PR_ERR(_fmt, _args...)  pr_err("ERROR: "_fmt, ##_args)
+
+  #define RTK_PHYLIB_ERR_FAILED             (-EPERM)
+  #define RTK_PHYLIB_ERR_INPUT              (-EINVAL)
+  #define RTK_PHYLIB_ERR_EXCEEDS_CAPACITY   (-ENOSPC)
+  #define RTK_PHYLIB_ERR_TIMEOUT            (-ETIME)
+  #define RTK_PHYLIB_ERR_ENTRY_NOTFOUND     (-ENODATA)
+  #define RTK_PHYLIB_ERR_OPER_DENIED        (-EACCES)
+#else
+  #define PR_INFO(_fmt, _args...) RT_LOG(LOG_INFO, (MOD_HAL|MOD_PHY), _fmt, ##_args)
+  #define PR_DBG(_fmt, _args...)  RT_LOG(LOG_DEBUG, (MOD_HAL|MOD_PHY), _fmt, ##_args)
+  #define PR_ERR(_fmt, _args...)  RT_LOG(LOG_MAJOR_ERR, (MOD_HAL|MOD_PHY), _fmt, ##_args)
+
+  #define RTK_PHYLIB_ERR_FAILED              (RT_ERR_FAILED)
+  #define RTK_PHYLIB_ERR_INPUT               (RT_ERR_INPUT)
+  #define RTK_PHYLIB_ERR_EXCEEDS_CAPACITY    (RT_ERR_EXCEEDS_CAPACITY)
+  #define RTK_PHYLIB_ERR_TIMEOUT             (RT_ERR_BUSYWAIT_TIMEOUT)
+  #define RTK_PHYLIB_ERR_ENTRY_NOTFOUND      (RT_ERR_ENTRY_NOTFOUND)
+  #define RTK_PHYLIB_ERR_OPER_DENIED         (RT_ERR_OPER_DENIED)
+#endif
+
+typedef enum rtk_phylib_phy_e
+{
+    RTK_PHYLIB_NONE,
+    RTK_PHYLIB_RTL8261N,
+    RTK_PHYLIB_RTL8264B,
+    RTK_PHYLIB_RTL8251L,
+    RTK_PHYLIB_RTL8254B,
+    RTK_PHYLIB_RTL8224,
+    RTK_PHYLIB_RTL8224N,
+    RTK_PHYLIB_END
+} rtk_phylib_phy_t;
+
+typedef enum rtk_port_duplex_e
+{
+    PORT_HALF_DUPLEX = 0,
+    PORT_FULL_DUPLEX,
+    PORT_DUPLEX_END
+} rtk_port_duplex_t;
+
+typedef enum rtk_port_speed_e
+{
+    PORT_SPEED_10M = 0,
+    PORT_SPEED_100M,
+    PORT_SPEED_500M,
+    PORT_SPEED_1000M,
+    PORT_SPEED_2_5G_LITE,
+    PORT_SPEED_2G,
+    PORT_SPEED_2_5G,
+    PORT_SPEED_5G_LITE,
+    PORT_SPEED_5G,
+    PORT_SPEED_10G_LITE,
+    PORT_SPEED_10G,
+    PORT_SPEED_25G,
+    PORT_SPEED_40G,
+    PORT_SPEED_50G,
+    PORT_SPEED_100G,
+    PORT_SPEED_END
+} rtk_port_speed_t;
+
+typedef enum rtk_port_lite_mode_e
+{
+    PORT_LITE_1G,
+    PORT_LITE_2P5G,
+    PORT_LITE_5G,
+    PORT_LITE_10G,
+    PORT_LITE_END
+} rtk_port_lite_mode_t;
+
+/* RTCT result Status of one channel */
+typedef struct rtk_rtctChannelStatus_s
+{
+    uint32      channelShort;
+    uint32      channelOpen;
+    uint32      channelLowMismatch;
+    uint32      channelHighMismatch;
+    uint32      channelCrossoverA;
+    uint32      channelCrossoverB;
+    uint32      channelCrossoverC;
+    uint32      channelCrossoverD;
+    uint32      channelLen;
+} rtk_rtctChannelStatus_t;
+
+/* result of RTCT test */
+typedef struct rtk_rtctResult_s
+{
+    rtk_port_speed_t    linkType;
+    union
+    {
+        struct fe_result_s
+        {
+            uint32      isRxShort;
+            uint32      isTxShort;
+            uint32      isRxOpen;
+            uint32      isTxOpen;
+            uint32      isRxMismatch;
+            uint32      isTxMismatch;
+            uint32      isRxLinedriver;
+            uint32      isTxLinedriver;
+            uint32      rxLen;
+            uint32      txLen;
+        } fe_result;
+
+        struct ge_result_s
+        {
+            uint32      channelAShort;
+            uint32      channelBShort;
+            uint32      channelCShort;
+            uint32      channelDShort;
+
+            uint32      channelAOpen;
+            uint32      channelBOpen;
+            uint32      channelCOpen;
+            uint32      channelDOpen;
+
+            uint32      channelAMismatch;
+            uint32      channelBMismatch;
+            uint32      channelCMismatch;
+            uint32      channelDMismatch;
+
+            uint32      channelALinedriver;
+            uint32      channelBLinedriver;
+            uint32      channelCLinedriver;
+            uint32      channelDLinedriver;
+
+            uint32      channelAHiImpedance;
+            uint32      channelBHiImpedance;
+            uint32      channelCHiImpedance;
+            uint32      channelDHiImpedance;
+
+            uint32      channelACross;
+            uint32      channelBCross;
+            uint32      channelCCross;
+            uint32      channelDCross;
+
+            uint32      channelAPartialCross;
+            uint32      channelBPartialCross;
+            uint32      channelCPartialCross;
+            uint32      channelDPartialCross;
+
+            /* when paire is busy, RTCT shall re-do by calling start API again. */
+            uint32      channelAPairBusy;
+            uint32      channelBPairBusy;
+            uint32      channelCPairBusy;
+            uint32      channelDPairBusy;
+
+            uint32      channelALen;
+            uint32      channelBLen;
+            uint32      channelCLen;
+            uint32      channelDLen;
+        } ge_result;
+
+        struct channels_result_s
+        {
+            rtk_rtctChannelStatus_t     a;
+            rtk_rtctChannelStatus_t     b;
+            rtk_rtctChannelStatus_t     c;
+            rtk_rtctChannelStatus_t     d;
+        } channels_result;
+    } un;
+} rtk_rtctResult_t;
+
+
+#if defined(RTK_PHYDRV_IN_LINUX)
+    typedef struct phy_device rtk_phydev;
+#else
+    struct rtk_phy_dev_s
+    {
+        uint32 unit;
+        rtk_port_t port;
+
+        struct rtk_phy_priv *priv;
+    };
+    typedef struct rtk_phy_dev_s rtk_phydev;
+#endif
+
+#define RTK_PHYLIB_ERR_CHK(op)\
+do {\
+    if ((ret = (op)) != 0)\
+        return ret;\
+} while(0)
+
+#define RTK_PHYLIB_VAL_TO_BYTE_ARRAY(_val, _valbytes, _array, _start, _bytes)\
+do{\
+    uint32 _i = 0;\
+    for (_i = 0; _i < _bytes; _i++)\
+        _array[(_bytes-1)-_i] = (_val >> (8* (_valbytes - _i - 1)));\
+}while(0)
+
+#define RTK_PHYLIB_BYTE_ARRAY_TO_VAL(_val, _array, _start, _bytes)\
+do{\
+    uint32 _i = 0;\
+    _val = 0;\
+    for (_i = 0; _i < _bytes; _i++)\
+        _val = (_val << 8) | _array[(_bytes-1)-_i];\
+}while(0)
+
+
+/* RTCT */
+#define RTK_PHYLIB_CABLE_STATUS_NORMAL              (0)
+#define RTK_PHYLIB_CABLE_STATUS_UNKNOWN             (1u << 0)
+#define RTK_PHYLIB_CABLE_STATUS_SHORT               (1u << 1)
+#define RTK_PHYLIB_CABLE_STATUS_OPEN                (1u << 2)
+#define RTK_PHYLIB_CABLE_STATUS_MISMATCH            (1u << 3)
+#define RTK_PHYLIB_CABLE_STATUS_CROSS               (1u << 4)
+#define RTK_PHYLIB_CABLE_STATUS_INTER_PAIR_SHORT    (1u << 5)
+
+typedef struct rtk_rtct_channel_result_s
+{
+    uint32 cable_status;
+    uint32 length_cm;
+} rtk_rtct_channel_result_t;
+
+/* MACsec */
+typedef struct rtk_macsec_sa_info_s
+{
+    uint8   ssci[4];
+} rtk_macsec_sa_info_t;
+
+#define MACSEC_SA_IS_USED(macsec_port_info_ptr, dir, sa_id)     (macsec_port_info_ptr->sa_used[dir][sa_id])
+#define MACSEC_SC_IS_USED(macsec_port_info_ptr, dir, sc_id)     (macsec_port_info_ptr->sc_used[dir][sc_id])
+
+#define MACSEC_SA_IS_CLEAR(macsec_port_info_ptr, dir, sa_id)    (!MACSEC_SA_IS_USED(macsec_port_info_ptr, dir, sa_id))
+#define MACSEC_SC_IS_CLEAR(macsec_port_info_ptr, dir, sc_id)    (!MACSEC_SC_IS_USED(macsec_port_info_ptr, dir, sc_id))
+
+#define MACSEC_SA_SET_USED(macsec_port_info_ptr, dir, sa_id)    do { macsec_port_info_ptr->sa_used[dir][sa_id] = 1; }while(0)
+#define MACSEC_SC_SET_USED(macsec_port_info_ptr, dir, sc_id)    do { macsec_port_info_ptr->sc_used[dir][sc_id] = 1; }while(0)
+
+#define MACSEC_SA_UNSET_USED(macsec_port_info_ptr, dir, sa_id)  do { macsec_port_info_ptr->sa_used[dir][sa_id] = 0; }while(0)
+#define MACSEC_SC_UNSET_USED(macsec_port_info_ptr, dir, sc_id)  do { macsec_port_info_ptr->sc_used[dir][sc_id] = 0; }while(0)
+
+#define MACSEC_SA_MAX(macsec_port_info_ptr)                 macsec_port_info_ptr->max_sa_num
+#define MACSEC_SC_MAX(macsec_port_info_ptr)                 macsec_port_info_ptr->max_sc_num
+#define MACSEC_SC_CS(macsec_port_info_ptr, dir, sc_id)      macsec_port_info_ptr->cipher_suite[dir][sc_id]
+#define MACSEC_SC_MATCH(macsec_port_info_ptr, dir, sc_id)   macsec_port_info_ptr->flow_match[dir][sc_id]
+#define MACSEC_SA_SSCI(macsec_port_info_ptr, sa_id)         macsec_port_info_ptr->sa_info[sa_id].ssci
+
+
+typedef struct rtk_macsec_port_stats_s
+{
+    uint64 InPktsUntagged;
+    uint64 InPktsNoTag;
+    uint64 InPktsBadTag;
+    uint64 InPktsUnknownSCI;
+    uint64 InPktsNoSCI;
+    uint64 OutPktsUntagged;
+}rtk_macsec_port_stats_t;
+
+typedef struct rtk_macsec_txsa_stats_s
+{
+    uint64 OutPktsTooLong;
+    uint64 OutOctetsProtectedEncrypted;
+    uint64 OutPktsProtectedEncrypted;
+}rtk_macsec_txsa_stats_t;
+
+typedef struct rtk_macsec_rxsa_stats_s
+{
+    uint64 InPktsUnusedSA;
+    uint64 InPktsNotUsingSA;
+    uint64 InPktsUnchecked;
+    uint64 InPktsDelayed;
+    uint64 InPktsLate;
+    uint64 InPktsOK;
+    uint64 InPktsInvalid;
+    uint64 InPktsNotValid;
+    uint64 InOctetsDecryptedValidated;
+}rtk_macsec_rxsa_stats_t;
+
+typedef struct rtk_macsec_port_info_s
+{
+    int32 (*macsec_reg_get)(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 reg, uint8 msb, uint8 lsb, uint32 *pData);
+    int32 (*macsec_reg_set)(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 reg, uint8 msb, uint8 lsb, uint32 data);
+
+    uint16 sa_gen_seq;
+    uint32 max_sa_num;
+    uint32 max_sc_num;
+    rtk_macsec_cipher_t cipher_suite[RTK_MACSEC_DIR_END][RTK_MAX_MACSEC_SC_PER_PORT];
+    uint32 flow_match[RTK_MACSEC_DIR_END][RTK_MAX_MACSEC_SC_PER_PORT];
+    uint8 sc_used[RTK_MACSEC_DIR_END][RTK_MAX_MACSEC_SC_PER_PORT];
+    uint8 sa_used[RTK_MACSEC_DIR_END][RTK_MAX_MACSEC_SA_PER_PORT];
+    rtk_macsec_sa_info_t sa_info[RTK_MAX_MACSEC_SA_PER_PORT];
+    uint64 sci[RTK_MACSEC_DIR_END][RTK_MAX_MACSEC_SC_PER_PORT];
+
+    rtk_macsec_port_stats_t port_stats;
+    rtk_macsec_txsa_stats_t *txsa_stats[RTK_MAX_MACSEC_SA_PER_PORT];
+    rtk_macsec_rxsa_stats_t *rxsa_stats[RTK_MAX_MACSEC_SA_PER_PORT];
+} rtk_macsec_port_info_t;
+
+struct rtk_phy_priv {
+    rtk_phylib_phy_t phytype;
+    uint8 isBasePort;
+    rt_phy_patch_db_t *patch;
+    rtk_macsec_port_info_t *macsec;
+};
+
+/* OSAL */
+void rtk_phylib_mdelay(uint32 msec);
+void rtk_phylib_udelay(uint32 usec);
+#define rtk_phylib_strlen   strlen
+#define rtk_phylib_strcmp   strcmp
+#define rtk_phylib_strcpy   strcpy
+#define rtk_phylib_strncpy  strncpy
+#define rtk_phylib_strcat   strcat
+#define rtk_phylib_strchr   strchr
+#define rtk_phylib_memset   memset
+#define rtk_phylib_memcpy   memcpy
+#define rtk_phylib_memcmp   memcmp
+#define rtk_phylib_strdup   strdup
+#define rtk_phylib_strncmp  strncmp
+#define rtk_phylib_strstr   strstr
+#define rtk_phylib_strtok   strtok
+#define rtk_phylib_strtok_r   strtok_r
+#define rtk_phylib_toupper  toupper
+
+int rtk_phylib_time_usecs_get(uint32 *pUsec);
+#ifndef WAIT_COMPLETE_VAR
+#define WAIT_COMPLETE_VAR() \
+    uint32    _t, _now, _t_wait=0, _timeout;  \
+    int32           _chkCnt=0;
+
+#define WAIT_COMPLETE(_timeout_us)     \
+    _timeout = _timeout_us;  \
+    for(rtk_phylib_time_usecs_get(&_t),rtk_phylib_time_usecs_get(&_now),_t_wait=0,_chkCnt=0 ; \
+        (_t_wait <= _timeout); \
+        rtk_phylib_time_usecs_get(&_now), _chkCnt++, _t_wait += ((_now >= _t) ? (_now - _t) : (0xFFFFFFFF - _t + _now)),_t = _now \
+       )
+
+#define WAIT_COMPLETE_IS_TIMEOUT()   (_t_wait > _timeout)
+#endif
+
+
+/* Register Access APIs */
+int32 rtk_phylib_mmd_write(rtk_phydev *phydev, uint32 mmd, uint32 reg, uint8 msb, uint8 lsb, uint32 data);
+int32 rtk_phylib_mmd_read(rtk_phydev *phydev, uint32 mmd, uint32 reg, uint8 msb, uint8 lsb, uint32 *pData);
+
+/* Function Driver */
+int32 rtk_phylib_c45_power_normal(rtk_phydev *phydev);
+int32 rtk_phylib_c45_power_low(rtk_phydev *phydev);
+int32 rtk_phylib_c45_pcs_loopback(rtk_phydev *phydev, uint32 enable);
+
+/* MACsec*/
+int32 rtk_phylib_macsec_init(rtk_phydev *phydev);
+int32 rtk_phylib_macsec_enable_get(rtk_phydev *phydev, uint32 *pEna);
+int32 rtk_phylib_macsec_enable_set(rtk_phydev *phydev, uint32 ena);
+
+int32 rtk_phylib_macsec_sc_create(rtk_phydev *phydev, rtk_macsec_dir_t dir, rtk_macsec_sc_t *pSc, uint32 *pSc_id, uint8 active);
+int32 rtk_phylib_macsec_sc_update(rtk_phydev *phydev, rtk_macsec_dir_t dir, rtk_macsec_sc_t *pSc, uint32 *pSc_id, uint8 active);
+int32 rtk_phylib_macsec_sc_del(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 sc_id);
+int32 rtk_phylib_macsec_sci_to_scid(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint64 sci, uint32 *sc_id);
+int32 rtk_phylib_macsec_sc_status_get(rtk_phydev *phydev, rtk_macsec_dir_t dir,uint32 sc_id, rtk_macsec_sc_status_t *pSc_status);
+int32 rtk_phylib_macsec_sc_get(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 sc_id, rtk_macsec_sc_t *pSc);
+
+int32 rtk_phylib_macsec_sa_activate(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 sc_id, rtk_macsec_an_t an);
+int32 rtk_phylib_macsec_rxsa_disable(rtk_phydev *phydev, uint32 rxsc_id, rtk_macsec_an_t an);
+int32 rtk_phylib_macsec_txsa_disable(rtk_phydev *phydev, uint32 txsc_id);
+int32 rtk_phylib_macsec_sa_create(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 sc_id, rtk_macsec_an_t an, rtk_macsec_sa_t *pSa);
+int32 rtk_phylib_macsec_sa_get(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 sc_id, rtk_macsec_an_t an, rtk_macsec_sa_t *pSa);
+int32 rtk_phylib_macsec_sa_del(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 sc_id, rtk_macsec_an_t an);
+
+int32 rtk_phylib_macsec_stat_port_get(rtk_phydev *phydev, rtk_macsec_stat_t stat, uint64 *pCnt);
+int32 rtk_phylib_macsec_stat_txsa_get(rtk_phydev *phydev, uint32 sc_id, rtk_macsec_an_t an, rtk_macsec_txsa_stat_t stat, uint64 *pCnt);
+int32 rtk_phylib_macsec_stat_rxsa_get(rtk_phydev *phydev, uint32 sc_id, rtk_macsec_an_t an, rtk_macsec_rxsa_stat_t stat, uint64 *pCnt);
+
+
+#endif /* __RTK_PHYLIB_H */
diff --git a/sources/rtk-gp3000/src/hal/phy/rtk_phylib_def.h b/sources/rtk-gp3000/src/hal/phy/rtk_phylib_def.h
new file mode 100644
index 00000000..5ca9cf6a
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/rtk_phylib_def.h
@@ -0,0 +1,421 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
+ */
+
+#ifndef __RTK_PHYLIB_DEF_H
+#define __RTK_PHYLIB_DEF_H
+
+#include "type.h"
+
+#define PHY_C22_MMD_PAGE            0x0A41
+#define PHY_C22_MMD_DEV_REG         13
+#define PHY_C22_MMD_ADD_REG         14
+
+/* MDIO Manageable Device(MDD) address*/
+#define PHY_MMD_PMAPMD              1
+#define PHY_MMD_PCS                 3
+#define PHY_MMD_AN                  7
+#define PHY_MMD_VEND1               30   /* Vendor specific 1 */
+#define PHY_MMD_VEND2               31   /* Vendor specific 2 */
+
+#define BIT_0        0x00000001U
+#define BIT_1        0x00000002U
+#define BIT_2        0x00000004U
+#define BIT_3        0x00000008U
+#define BIT_4        0x00000010U
+#define BIT_5        0x00000020U
+#define BIT_6        0x00000040U
+#define BIT_7        0x00000080U
+#define BIT_8        0x00000100U
+#define BIT_9        0x00000200U
+#define BIT_10       0x00000400U
+#define BIT_11       0x00000800U
+#define BIT_12       0x00001000U
+#define BIT_13       0x00002000U
+#define BIT_14       0x00004000U
+#define BIT_15       0x00008000U
+#define BIT_16       0x00010000U
+#define BIT_17       0x00020000U
+#define BIT_18       0x00040000U
+#define BIT_19       0x00080000U
+#define BIT_20       0x00100000U
+#define BIT_21       0x00200000U
+#define BIT_22       0x00400000U
+#define BIT_23       0x00800000U
+#define BIT_24       0x01000000U
+#define BIT_25       0x02000000U
+#define BIT_26       0x04000000U
+#define BIT_27       0x08000000U
+#define BIT_28       0x10000000U
+#define BIT_29       0x20000000U
+#define BIT_30       0x40000000U
+#define BIT_31       0x80000000U
+
+#define MASK_1_BITS     (BIT_1 - 1)
+#define MASK_2_BITS     (BIT_2 - 1)
+#define MASK_3_BITS     (BIT_3 - 1)
+#define MASK_4_BITS     (BIT_4 - 1)
+#define MASK_5_BITS     (BIT_5 - 1)
+#define MASK_6_BITS     (BIT_6 - 1)
+#define MASK_7_BITS     (BIT_7 - 1)
+#define MASK_8_BITS     (BIT_8 - 1)
+#define MASK_9_BITS     (BIT_9 - 1)
+#define MASK_10_BITS    (BIT_10 - 1)
+#define MASK_11_BITS    (BIT_11 - 1)
+#define MASK_12_BITS    (BIT_12 - 1)
+#define MASK_13_BITS    (BIT_13 - 1)
+#define MASK_14_BITS    (BIT_14 - 1)
+#define MASK_15_BITS    (BIT_15 - 1)
+#define MASK_16_BITS    (BIT_16 - 1)
+#define MASK_17_BITS    (BIT_17 - 1)
+#define MASK_18_BITS    (BIT_18 - 1)
+#define MASK_19_BITS    (BIT_19 - 1)
+#define MASK_20_BITS    (BIT_20 - 1)
+#define MASK_21_BITS    (BIT_21 - 1)
+#define MASK_22_BITS    (BIT_22 - 1)
+#define MASK_23_BITS    (BIT_23 - 1)
+#define MASK_24_BITS    (BIT_24 - 1)
+#define MASK_25_BITS    (BIT_25 - 1)
+#define MASK_26_BITS    (BIT_26 - 1)
+#define MASK_27_BITS    (BIT_27 - 1)
+#define MASK_28_BITS    (BIT_28 - 1)
+#define MASK_29_BITS    (BIT_29 - 1)
+#define MASK_30_BITS    (BIT_30 - 1)
+#define MASK_31_BITS    (BIT_31 - 1)
+
+#define REG32_FIELD_SET(_data, _val, _fOffset, _fMask)      ((_data & ~(_fMask)) | ((_val << (_fOffset)) & (_fMask)))
+#define REG32_FIELD_GET(_data, _fOffset, _fMask)            ((_data & (_fMask)) >> (_fOffset))
+#define UINT32_BITS_MASK(_mBit, _lBit)                      ((0xFFFFFFFF >> (31 - _mBit)) ^ ((1 << _lBit) - 1))
+
+typedef struct phy_device *  rtk_port_t;
+
+#if 1 /* ss\sdk\include\hal\phy\phydef.h */
+/* unified patch format */
+typedef enum rtk_phypatch_type_e
+{
+    PHY_PATCH_TYPE_NONE = 0,
+    PHY_PATCH_TYPE_TOP = 1,
+    PHY_PATCH_TYPE_SDS,
+    PHY_PATCH_TYPE_AFE,
+    PHY_PATCH_TYPE_UC,
+    PHY_PATCH_TYPE_UC2,
+    PHY_PATCH_TYPE_NCTL0,
+    PHY_PATCH_TYPE_NCTL1,
+    PHY_PATCH_TYPE_NCTL2,
+    PHY_PATCH_TYPE_ALGXG,
+    PHY_PATCH_TYPE_ALG1G,
+    PHY_PATCH_TYPE_NORMAL,
+    PHY_PATCH_TYPE_DATARAM,
+    PHY_PATCH_TYPE_RTCT,
+    PHY_PATCH_TYPE_END
+} rtk_phypatch_type_t;
+
+#define RTK_PATCH_TYPE_FLOW(_id)    (PHY_PATCH_TYPE_END + _id)
+#define RTK_PATCH_TYPE_FLOWID_MAX   PHY_PATCH_TYPE_END
+#define RTK_PATCH_SEQ_MAX     ( PHY_PATCH_TYPE_END + RTK_PATCH_TYPE_FLOWID_MAX -1)
+
+/* Interrupt */
+/* PHY Interrupt Status */
+#define RTK_PHY_INTR_NEXT_PAGE_RECV       (BIT_0)
+#define RTK_PHY_INTR_AN_COMPLETE          (BIT_1)
+#define RTK_PHY_INTR_LINK_CHANGE          (BIT_2)
+#define RTK_PHY_INTR_ALDPS_STATE_CHANGE   (BIT_3)
+#define RTK_PHY_INTR_RLFD                 (BIT_4)
+#define RTK_PHY_INTR_TM_LOW               (BIT_5)
+#define RTK_PHY_INTR_TM_HIGH              (BIT_6)
+#define RTK_PHY_INTR_FATAL_ERROR          (BIT_7)
+#define RTK_PHY_INTR_MACSEC               (BIT_8)
+#define RTK_PHY_INTR_PTP1588              (BIT_9)
+#define RTK_PHY_INTR_WOL                  (BIT_10)
+
+typedef struct rtk_hwpatch_s
+{
+    uint8    patch_op;
+    uint8    portmask;
+    uint16   pagemmd;
+    uint16   addr;
+    uint8    msb;
+    uint8    lsb;
+    uint16   data;
+    uint8    compare_op;
+    uint16   sram_p;
+    uint16   sram_rr;
+    uint16   sram_rw;
+    uint16   sram_a;
+} rtk_hwpatch_t;
+
+typedef struct rtk_hwpatch_data_s
+{
+    rtk_hwpatch_t *conf;
+    uint32        size;
+} rtk_hwpatch_data_t;
+
+typedef struct rtk_hwpatch_seq_s
+{
+    uint8 patch_type;
+    union
+    {
+        rtk_hwpatch_data_t data;
+        uint8 flow_id;
+    } patch;
+} rtk_hwpatch_seq_t;
+
+typedef struct rt_phy_patch_db_s
+{
+    /* patch operation */
+    int32   (*fPatch_op)(uint32 unit, rtk_port_t port, uint8 portOffset, rtk_hwpatch_t *pPatch_data, uint8 patch_mode);
+    int32   (*fPatch_flow)(uint32 unit, rtk_port_t port, uint8 portOffset, uint8 patch_flow, uint8 patch_mode);
+
+    /* patch data */
+    rtk_hwpatch_seq_t seq_table[RTK_PATCH_SEQ_MAX];
+    rtk_hwpatch_seq_t cmp_table[RTK_PATCH_SEQ_MAX];
+
+} rt_phy_patch_db_t;
+#endif
+
+#define RTK_HWPATCH_OP_UNKNOWN                  0
+#define RTK_HWPATCH_OP_SDS                      1
+#define RTK_HWPATCH_OP_PHY                      2
+#define RTK_HWPATCH_OP_PHYW                     3
+#define RTK_HWPATCH_OP_ALGO                     4
+#define RTK_HWPATCH_OP_TOP                      5
+#define RTK_HWPATCH_OP_MMD                      6
+#define RTK_HWPATCH_OP_DATARAM                  7
+
+typedef struct rtk_phy_hwpatch_s
+{
+    uint8    patch_op;
+    uint8    portmask;
+    uint16   pagemmd;
+    uint16   addr;
+    uint8    msb;
+    uint8    lsb;
+    uint16   data;
+} rtk_phy_hwpatch_t;
+
+
+/* cable type for cable test */
+typedef enum {
+	RTK_RTCT_CABLE_COMMON,
+	RTK_RTCT_CABLE_CAT5E,
+	RTK_RTCT_CABLE_CAT6A,
+} rtk_rtct_cable_type_t;
+
+/* MACSec */
+#ifndef RTK_MAX_MACSEC_SA_PER_PORT
+  #define RTK_MAX_MACSEC_SA_PER_PORT                  64                              /* max number of Secure Association by a port*/
+  #define RTK_MAX_MACSEC_SC_PER_PORT                  RTK_MAX_MACSEC_SA_PER_PORT/4    /* max number of Secure Channel by a port (4 AN per SC) */
+#endif
+
+#define RTK_MACSEC_MAX_KEY_LEN        32
+
+typedef enum rtk_macsec_reg_e
+{
+    RTK_MACSEC_DIR_EGRESS = 0,
+    RTK_MACSEC_DIR_INGRESS,
+    RTK_MACSEC_DIR_END,
+} rtk_macsec_dir_t;
+
+typedef enum rtk_macsec_an_e
+{
+    RTK_MACSEC_AN0 = 0,
+    RTK_MACSEC_AN1,
+    RTK_MACSEC_AN2,
+    RTK_MACSEC_AN3,
+    RTK_MACSEC_AN_MAX,
+} rtk_macsec_an_t ;
+
+typedef enum rtk_macsec_flow_e
+{
+    RTK_MACSEC_FLOW_BYPASS = 0,
+    RTK_MACSEC_FLOW_DROP,
+    RTK_MACSEC_FLOW_INGRESS,
+    RTK_MACSEC_FLOW_EGRESS,
+} rtk_macsec_flow_type_t;
+
+typedef enum rtk_macsec_validate_e
+{
+    RTK_MACSEC_VALIDATE_STRICT = 0,
+    RTK_MACSEC_VALIDATE_CHECK,
+    RTK_MACSEC_VALIDATE_DISABLE,
+} rtk_macsec_validate_t;
+
+typedef enum rtk_macsec_cipher_e
+{
+    RTK_MACSEC_CIPHER_GCM_ASE_128 = 0,
+    RTK_MACSEC_CIPHER_GCM_ASE_256,
+    RTK_MACSEC_CIPHER_GCM_ASE_XPN_128,
+    RTK_MACSEC_CIPHER_GCM_ASE_XPN_256,
+    RTK_MACSEC_CIPHER_MAX,
+} rtk_macsec_cipher_t;
+
+typedef enum rtk_macsec_stat_e
+{
+    RTK_MACSEC_STAT_InPktsUntagged = 0,
+    RTK_MACSEC_STAT_InPktsNoTag,
+    RTK_MACSEC_STAT_InPktsBadTag,
+    RTK_MACSEC_STAT_InPktsUnknownSCI,
+    RTK_MACSEC_STAT_InPktsNoSCI,
+    RTK_MACSEC_STAT_OutPktsUntagged,
+    RTK_MACSEC_STAT_MAX,
+} rtk_macsec_stat_t;
+
+typedef enum rtk_macsec_txsa_stat_e
+{
+    RTK_MACSEC_TXSA_STAT_OutPktsTooLong = 0,
+    RTK_MACSEC_TXSA_STAT_OutOctetsProtectedEncrypted,
+    RTK_MACSEC_TXSA_STAT_OutPktsProtectedEncrypted,
+    RTK_MACSEC_TXSA_STAT_MAX,
+} rtk_macsec_txsa_stat_t;
+
+typedef enum rtk_macsec_rxsa_stat_e
+{
+    RTK_MACSEC_RXSA_STAT_InPktsUnusedSA = 0,
+    RTK_MACSEC_RXSA_STAT_InPktsNotUsingSA,
+    RTK_MACSEC_RXSA_STAT_InPktsUnchecked,
+    RTK_MACSEC_RXSA_STAT_InPktsDelayed,
+    RTK_MACSEC_RXSA_STAT_InPktsLate,
+    RTK_MACSEC_RXSA_STAT_InPktsOK,
+    RTK_MACSEC_RXSA_STAT_InPktsInvalid,
+    RTK_MACSEC_RXSA_STAT_InPktsNotValid,
+    RTK_MACSEC_RXSA_STAT_InOctetsDecryptedValidated,
+    RTK_MACSEC_RXSA_STAT_MAX,
+} rtk_macsec_rxsa_stat_t;
+
+
+typedef enum rtk_macsec_match_tx_e
+{
+    RTK_MACSEC_MATCH_NON_CTRL = 0, /* match all non-control and untagged packets */
+    RTK_MACSEC_MATCH_MAC_DA, /* match all non-control and untagged packets with specific MAC DA */
+} rtk_macsec_match_tx_t;
+
+typedef struct rtk_macsec_txsc_s
+{
+    /* 8-byte SCI([0:5] = MAC address, [6:7] = port index) for this secure channel  */
+    uint8      sci[8];
+
+    /* cipher suite for this SC */
+    rtk_macsec_cipher_t    cipher_suite;
+
+    /* packet flow type to match this SC */
+    rtk_macsec_match_tx_t  flow_match;
+    rtk_mac_t  mac_da; /* the target address for RTK_MACSEC_MATCH_MAC_DA */
+
+    uint8 protect_frame;  /* 1 = enable frame protection */
+    uint8 include_sci;    /* 1 = include explicit SCI in packet */
+    uint8 use_es;         /* 1 = set ES (End Station) bit in TCI field */
+    uint8 use_scb;        /* 1 = set SCB (Single Copy Broadcast) bit in TCI field */
+    uint8 conf_protect;   /* 1 = enable confidentiality protection, */
+}rtk_macsec_txsc_t;
+
+typedef enum rtk_macsec_match_rx_e
+{
+    RTK_MACSEC_MATCH_SCI = 0,
+    RTK_MACSEC_MATCH_MAC_SA,  //for pkt without SCI field/TCI.SC=0,
+} rtk_macsec_match_rx_t;
+
+typedef struct rtk_macsec_rxsc_s
+{
+    /* 8-byte SCI([0:5] = MAC address, [6:7] = port index) for this secure channel  */
+    uint8      sci[8];
+
+    /* cipher suite for this SC */
+    rtk_macsec_cipher_t   cipher_suite;
+
+    /* packet flow type to match this SC */
+    rtk_macsec_match_rx_t flow_match;
+    rtk_mac_t  mac_sa; /* the target address for RTK_MACSEC_MATCH_MAC_SA */
+
+    /* frame validation level */
+    rtk_macsec_validate_t validate_frames;
+
+    /* replay protection */
+    uint8  replay_protect;  /* 1 = enable replay protection */
+    uint32 replay_window;   /* the window size for replay protection, range for PN: 0 ~ 2^32 - 1, for XPN: 0 ~ 2^30 */
+
+}rtk_macsec_rxsc_t;
+
+typedef union rtk_macsec_sc_u
+{
+    rtk_macsec_txsc_t tx;
+    rtk_macsec_rxsc_t rx;
+}
+rtk_macsec_sc_t;
+
+typedef struct rtk_macsec_txsc_status_s
+{
+    uint32 hw_flow_index;
+    uint32 hw_sa_index;
+    uint8  sa_inUse;
+    uint32 hw_flow_data;
+    uint8  hw_sc_flow_status;
+    rtk_macsec_an_t running_an;
+}
+rtk_macsec_txsc_status_t;
+
+typedef struct rtk_macsec_rxsc_status_s
+{
+    uint32 hw_flow_base;
+    uint32 hw_sa_index[RTK_MACSEC_AN_MAX];
+    uint8  sa_inUse[RTK_MACSEC_AN_MAX];
+    uint32 hw_flow_data[RTK_MACSEC_AN_MAX];
+    uint8  hw_sc_flow_status[RTK_MACSEC_AN_MAX];
+}
+rtk_macsec_rxsc_status_t;
+
+typedef union rtk_macsec_sc_status_u
+{
+    rtk_macsec_txsc_status_t tx;
+    rtk_macsec_rxsc_status_t rx;
+}
+rtk_macsec_sc_status_t;
+
+typedef struct rtk_macsec_sa_s
+{
+    uint8 key[RTK_MACSEC_MAX_KEY_LEN];  // MACsec Key.
+    uint32 key_bytes; // Size of the MACsec key in bytes (16 for AES128, 32 for AES256).
+
+    uint32 pn;      // PN (32-bit) or lower 32-bit of XPN (64-bit)
+    uint32 pn_h;    // higher 32-bit of XPN (64-bit)
+    uint8 salt[12]; // 12-byte salt (for XPN).
+    uint8 ssci[4];  // 4-byte SSCI value (for XPN).
+} rtk_macsec_sa_t;
+
+#define RTK_MACSEC_INTR_EGRESS_PN_THRESHOLD          0x00000001
+#define RTK_MACSEC_INTR_EGRESS_PN_ROLLOVER           0x00000002
+
+typedef struct rtk_macsec_intr_status_s
+{
+    /* a bitmap of RTK_MACSEC_INTR_*  to present occured event */
+    uint32 status;
+
+    /* When read 1b, the corresponding MACsec egress SA is about to expire due to
+       the packet number crossing the rtk_macsec_port_cfg_t.pn_intr_threshold or xpn_intr_threshold*/
+    uint8  egress_pn_thr_an_bmap[RTK_MAX_MACSEC_SC_PER_PORT]; //bitmap of AN3~0.
+
+    /* When read 1b, the corresponding MACsec egress SA has expired due to
+       the packet number reaching the maximum allowed value. */
+    uint8  egress_pn_exp_an_bmap[RTK_MAX_MACSEC_SC_PER_PORT]; //bitmap of AN3~0.
+}
+rtk_macsec_intr_status_t;
+
+
+typedef enum rtk_wol_opt_e
+{
+    RTK_WOL_OPT_LINK   = (0x1U << 0),
+    RTK_WOL_OPT_MAGIC  = (0x1U << 1),
+    RTK_WOL_OPT_UCAST  = (0x1U << 2),
+    RTK_WOL_OPT_MCAST  = (0x1U << 3),
+    RTK_WOL_OPT_BCAST  = (0x1U << 4),
+} rtk_wol_opt_t;
+
+/* value for RTK_PHY_CTRL_MDI_POLARITY_SWAP */
+#define RTK_PHY_CTRL_MDI_POLARITY_SWAP_CH_A    0b0001
+#define RTK_PHY_CTRL_MDI_POLARITY_SWAP_CH_B    0b0010
+#define RTK_PHY_CTRL_MDI_POLARITY_SWAP_CH_C    0b0100
+#define RTK_PHY_CTRL_MDI_POLARITY_SWAP_CH_D    0b1000
+
+
+#endif /* __RTK_PHYLIB_DEF_H */
diff --git a/sources/rtk-gp3000/src/hal/phy/rtk_phylib_macsec.c b/sources/rtk-gp3000/src/hal/phy/rtk_phylib_macsec.c
new file mode 100644
index 00000000..ea24defe
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/rtk_phylib_macsec.c
@@ -0,0 +1,2448 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
+ */
+
+#if defined(RTK_PHYDRV_IN_LINUX)
+  #include <crypto/aes.h>
+  #include "rtk_phylib.h"
+  #include "rtk_phylib_macsec.h"
+  #include "rtk_phylib_rtl826xb.h"
+#else
+  //#include SDK headers
+  #include <hal/phy/macsec/phy_macsec.h>
+  #include <hal/common/halctrl.h>
+  #include <osal/time.h>
+  #include <osal/memory.h>
+  #include <hal/phy/macsec/aes.h>
+  #include <hal/phy/phy_probe.h>
+  #include <hal/phy/macsec/aes.h>
+#endif
+
+
+#define MACSEC_REG_GET(phydev, dir, reg, pData) \
+do\
+{\
+    struct rtk_phy_priv *_priv = phydev->priv;\
+    RTK_PHYLIB_ERR_CHK(_priv->macsec->macsec_reg_get(phydev, dir, reg, 31, 0, pData));\
+} while (0)
+
+#define MACSEC_REG_SET(phydev, dir, reg, data) \
+do\
+{\
+    struct rtk_phy_priv *_priv = phydev->priv;\
+    RTK_PHYLIB_ERR_CHK(_priv->macsec->macsec_reg_set(phydev, dir, reg, 31, 0, data));\
+} while (0)
+
+#define MACSEC_REG_ARRAY_GET(phydev, dir, reg, pArray, cnt) \
+do\
+{\
+    if((ret = __rtk_phylib_macsec_reg_array_get(phydev, dir, reg, pArray, cnt)) != 0)\
+    {\
+        return ret;\
+    }\
+} while(0)
+
+#define MACSEC_REG_ARRAY_SET(phydev, dir, reg, pArray, cnt) \
+do\
+{\
+    if((ret = __rtk_phylib_macsec_reg_array_set(phydev, dir, reg, pArray, cnt)) != 0)\
+    {\
+        return ret;\
+    }\
+} while(0)
+
+static void __rtk_macsec_aes_encrypt(const uint8 * const In_p, uint8 * const Out_p,
+        const uint8 * const Key_p, const unsigned int KeyByteCount)
+{
+    struct crypto_aes_ctx ctx;
+    int ret = 0;
+	ret = aes_expandkey(&ctx, Key_p, KeyByteCount);
+	if (ret)
+    {
+        PR_ERR("aes_expandkey failed!");
+		return;
+    }
+    aes_encrypt(&ctx, Out_p, In_p);
+}
+
+static int32 __rtk_phylib_macsec_reg_array_get(rtk_phydev *phydev, rtk_macsec_dir_t dir,
+                         const uint32 reg, uint32* pArray, const uint32 cnt)
+{
+    int32  ret = 0;
+    uint32 data = 0, i = 0;
+    uint32 offset = reg;
+
+    for (i = 0; i < cnt; i++)
+    {
+        MACSEC_REG_GET(phydev, dir, offset, &data);
+        pArray[i] = data;
+        offset += MACSEC_REG_OFFS;
+    }
+    return ret;
+}
+
+static int32 __rtk_phylib_macsec_reg_array_set(rtk_phydev *phydev, rtk_macsec_dir_t dir,
+                         const uint32 reg, uint32* pArray, const uint32 cnt)
+{
+    int32  ret = 0;
+    uint32 data = 0, i = 0;
+    uint32 offset = reg;
+
+    for (i = 0; i < cnt; i++)
+    {
+        data = pArray[i];
+        MACSEC_REG_SET(phydev, dir, offset, data);
+        offset += MACSEC_REG_OFFS;
+    }
+    return ret;
+}
+
+static int32 __rtk_phylib_macsec_hw_flow_action_write(
+        rtk_phydev *phydev,
+        rtk_macsec_dir_t dir, uint32 flow_index,
+        const uint32 SAIndex,
+        const uint8 FlowType,
+        const uint8 DestPort,
+        const uint8 fDropNonReserved,
+        const uint8 fFlowCryptAuth,
+        const uint8 DropAction,
+        const uint8 fProtect,
+        const uint8 fSAInUse,
+        const uint8 fIncludeSCI,
+        const uint8 ValidateFrames,
+        const uint8 TagBypassSize,
+        const uint8 fSaIndexUpdate,
+        const uint8 ConfOffset,
+        const uint8 fConfProtect)
+{
+    int32 ret = 0;
+    uint32 data = 0;
+
+    if(fDropNonReserved)
+        data |= BIT_4;
+    else
+        data &= ~BIT_4;
+
+    if(fFlowCryptAuth)
+        data |= BIT_5;
+    else
+        data &= ~BIT_5;
+
+    if(fProtect)
+        data |= BIT_16;
+    else
+        data &= ~BIT_16;
+
+    if(fSAInUse)
+        data |= BIT_17;
+    else
+        data &= ~BIT_17;
+
+    if(fIncludeSCI)
+        data |= BIT_18;
+    else
+        data &= ~BIT_18;
+
+    if(fSaIndexUpdate)
+        data |= BIT_23;
+    else
+        data &= ~BIT_23;
+
+    if(fConfProtect)
+        data |= BIT_31;
+    else
+        data &= ~BIT_31;
+
+    data |= (uint32)((((uint32)ConfOffset)     & MASK_7_BITS) << 24);
+    data |= (uint32)((((uint32)TagBypassSize)  & MASK_2_BITS) << 21);
+    data |= (uint32)((((uint32)ValidateFrames) & MASK_2_BITS) << 19);
+    data |= (uint32)((((uint32)SAIndex)        & MASK_8_BITS) << 8);
+    data |= (uint32)((((uint32)DropAction)     & MASK_2_BITS) << 6);
+    data |= (uint32)((((uint32)DestPort)       & MASK_2_BITS) << 2);
+    data |= (uint32)((((uint32)FlowType)       & MASK_2_BITS));
+
+    MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_FLOW_CTRL(flow_index), data);
+
+    PR_DBG("FLOW[%u] = 0x%08X\n", flow_index, data);
+
+    return ret;
+}
+
+static void __rtk_phylib_macsec_copy_key_to_raw(uint32 *pRaw, uint32 offset, uint8 *pKey, uint32 key_bytes)
+{
+    uint32_t *dst = pRaw + offset;
+    const uint8_t *src = pKey;
+    unsigned int i,j;
+    uint32_t w;
+    if (pRaw == NULL)
+        return;
+    for(i=0; i<(key_bytes+3)/4; i++)
+    {
+        w=0;
+        for(j=0; j<4; j++)
+            w=(w>>8)|(*src++ << 24);
+        *dst++ = w;
+    }
+}
+
+static void __rtk_phylib_macsec_copy_raw_to_key(uint32 *pRaw, uint32 offset ,uint8 *pKey, uint32 raw_words)
+{
+    uint32_t *src = pRaw + offset;
+    uint8_t *dst = pKey;
+    unsigned int i;
+    if (pRaw == NULL)
+        return;
+
+    for (i = 0; i < raw_words; i++)
+    {
+        *dst++ = (uint8)((src[i] & 0xff));
+        *dst++ = (uint8)((src[i] & 0xff00) >> 8) ;
+        *dst++ = (uint8)((src[i] & 0xff0000) >> 16) ;
+        *dst++ = (uint8)((src[i] & 0xff000000) >> 24) ;
+    }
+}
+
+static void __rtk_phylib_macsec_hw_sa_offset_parse(phy_macsec_sa_params_t *pSa, phy_macsec_sa_offset_t *pOffs)
+{
+    unsigned int long_key;
+    rtk_phylib_memset(pOffs, 0, sizeof(phy_macsec_sa_offset_t));
+
+    pOffs->key_offs = 2;
+    if (pSa->key_bytes == 16)
+    {
+        long_key = 0;
+    }
+    else
+    {
+        long_key = 4;
+    }
+    pOffs->hkey_offs = long_key + 6;
+    pOffs->seq_offs = long_key + 10;
+    if (pSa->direction == RTK_MACSEC_DIR_EGRESS)
+    {
+        if ((pSa->flags & RTK_PHY_MACSEC_SA_FLAG_XPN) != 0)
+        {
+            pOffs->ctx_salt_offs = long_key + 13;
+            pOffs->iv_offs = long_key + 16;
+            if (long_key)
+                pOffs->upd_ctrl_offs = 16;
+            else
+                pOffs->upd_ctrl_offs = 19;
+        }
+        else
+        {
+            pOffs->iv_offs = long_key + 11;
+            pOffs->upd_ctrl_offs = long_key + 15;
+        }
+    }
+    else
+    {
+        if ((pSa->flags & RTK_PHY_MACSEC_SA_FLAG_XPN) != 0)
+        {
+            pOffs->mask_offs = long_key + 12;
+            pOffs->ctx_salt_offs = long_key + 13;
+            pOffs->upd_ctrl_offs = 0;
+        }
+        else
+        {
+            pOffs->mask_offs = long_key + 11;
+            pOffs->iv_offs = long_key + 12;
+            pOffs->upd_ctrl_offs = 0;
+        }
+    }
+}
+
+static uint32 __rtk_phylib_macsec_hw_context_id_gen(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 sa_index)
+{
+    struct rtk_phy_priv *priv = phydev->priv;
+    rtk_macsec_port_info_t *macsec_db = priv->macsec;
+
+    uint32 context_id = 0;
+    context_id = 0x10000 * (macsec_db->sa_gen_seq & (0xFFFF)) + 0x1000 * (dir)+ sa_index;
+    macsec_db->sa_gen_seq++;
+    return context_id;
+}
+
+static int32 __rtk_phylib_macsec_hw_sa_parse(rtk_phydev *phydev, uint32 sa_index, uint32 *pSa_raw, phy_macsec_sa_params_t *pSa)
+{
+    struct rtk_phy_priv *priv = phydev->priv;
+    rtk_macsec_port_info_t *macsec_db = priv->macsec;
+
+    int32 ret = 0;
+    uint32 next_offs = 0, words = 0;
+    uint8 tmp8 = 0;
+    if (pSa == NULL || pSa_raw == NULL)
+        return RTK_PHYLIB_ERR_INPUT;
+
+    rtk_phylib_memset(pSa, 0, sizeof(phy_macsec_sa_params_t));
+
+    if (pSa_raw[0] & BIT_29)
+    {
+        pSa->flags |= RTK_PHY_MACSEC_SA_FLAG_XPN;
+    }
+
+    if ((pSa_raw[0] & MASK_4_BITS) == 0b0110)
+    {
+        pSa->direction = RTK_MACSEC_DIR_EGRESS;
+
+        pSa->an = (uint8)((pSa_raw[0] >> 26) & 0x3);
+    }
+    else
+    {
+        pSa->direction = RTK_MACSEC_DIR_INGRESS;
+    }
+
+    if (((pSa_raw[0] >> 17) & MASK_3_BITS) == 0b101)
+    {
+        pSa->key_bytes = 16;
+    }
+    else
+    {
+        pSa->key_bytes = 32;
+    }
+    next_offs = 2;
+
+    pSa->context_id = pSa_raw[1];
+
+    /* key */
+    words = (pSa->key_bytes * 8) / 32;
+    __rtk_phylib_macsec_copy_raw_to_key(pSa_raw, next_offs, pSa->key, words);
+    next_offs += words + 4;
+
+    /* seq */
+    pSa->seq = pSa_raw[next_offs];
+    words = 1;
+
+    if (pSa->flags & RTK_PHY_MACSEC_SA_FLAG_XPN)
+    {
+        pSa->seq_h = pSa_raw[next_offs+1];
+        words = 2;
+    }
+    next_offs += words;
+
+    /* replay_window(ingress) */
+    if (pSa->direction == RTK_MACSEC_DIR_EGRESS)
+    {
+        words = (pSa->flags & RTK_PHY_MACSEC_SA_FLAG_XPN) ? 1 : 0;
+    }
+    else
+    {
+        pSa->replay_window = pSa_raw[next_offs];
+        words = 1;
+    }
+    next_offs += words;
+
+    /* CtxSalt */
+    if (pSa->flags & RTK_PHY_MACSEC_SA_FLAG_XPN)
+    {
+        words = 3;
+
+        pSa->ssci[0] = macsec_db->sa_info[sa_index].ssci[0];
+        pSa->ssci[1] = macsec_db->sa_info[sa_index].ssci[1];
+        pSa->ssci[2] = macsec_db->sa_info[sa_index].ssci[2];
+        pSa->ssci[3] = macsec_db->sa_info[sa_index].ssci[3];
+
+        tmp8 = (uint8)(pSa_raw[next_offs] & 0xFF);
+        pSa->salt[0] = (tmp8 ^ (pSa->ssci[0]));
+        tmp8 = (uint8)((pSa_raw[next_offs] & 0xFF00) >> 8 );
+        pSa->salt[1] = (tmp8 ^ (pSa->ssci[1]));
+        tmp8 = (uint8)((pSa_raw[next_offs] & 0xFF0000) >> 16 );
+        pSa->salt[2] = (tmp8 ^ (pSa->ssci[2]));
+        tmp8 = (uint8)((pSa_raw[next_offs] & 0xFF000000) >> 24 );
+        pSa->salt[3] = (tmp8 ^ (pSa->ssci[3]));
+
+        __rtk_phylib_macsec_copy_raw_to_key(pSa_raw, next_offs + 1, &pSa->salt[4], 2);
+
+    }
+    else
+    {
+        words = 0;
+    }
+    next_offs += words;
+
+    /* IV(SCI) */
+    if (pSa->flags & RTK_PHY_MACSEC_SA_FLAG_XPN)
+    {
+        if (pSa->direction == RTK_MACSEC_DIR_EGRESS)
+        {
+            words = 3;
+        }
+        else
+        {
+            words = 0;
+        }
+    }
+    else
+    {
+        words = 4;
+    }
+
+    if (words != 0)
+    {
+        __rtk_phylib_macsec_copy_raw_to_key(pSa_raw, next_offs, pSa->sci, 2);
+    }
+    next_offs += words;
+
+    /* Update Control */
+    if (pSa->direction == RTK_MACSEC_DIR_EGRESS)
+    {
+
+        pSa->flow_index = (uint32)((pSa_raw[next_offs] >> 16) & MASK_15_BITS);
+        pSa->next_sa_index = (uint32)(pSa_raw[next_offs] & MASK_14_BITS);
+        pSa->update_en = (pSa_raw[next_offs] & BIT_31) ? 1 : 0;
+        pSa->next_sa_valid = (pSa_raw[next_offs] & BIT_15) ? 1 : 0;
+        pSa->sa_expired_irq = (pSa_raw[next_offs] & BIT_14) ? 1 : 0;
+    }
+
+    return ret;
+}
+
+static int32 __rtk_phylib_macsec_hw_sa_build(rtk_phydev *phydev, uint32 sa_index, phy_macsec_sa_params_t *pSa, uint32 *pSa_raw)
+{
+    struct rtk_phy_priv *priv = phydev->priv;
+    rtk_macsec_port_info_t *macsec_db = priv->macsec;
+
+    int32 ret = 0;
+    phy_macsec_sa_offset_t offs;
+
+    uint8 hkey[16] = { 0 };
+    uint32 tmp = 0;
+    uint32_t seq = 0; // sequence number.
+    uint32_t seq_h = 0; // High part of sequence number (64-bit sequence numbers)
+    uint32 gen_id = 0;
+
+    if (pSa == NULL || pSa_raw == NULL)
+        return RTK_PHYLIB_ERR_INPUT;
+    if (pSa->an > 3)
+        return RTK_PHYLIB_ERR_INPUT;
+
+    if ((pSa->direction != RTK_MACSEC_DIR_INGRESS) &&
+        (pSa->direction != RTK_MACSEC_DIR_EGRESS))
+    {
+        PR_ERR("unknown direction:%d", pSa->direction);
+        return RTK_PHYLIB_ERR_INPUT;
+    }
+
+    if (pSa->context_id == 0)
+    {
+        gen_id = __rtk_phylib_macsec_hw_context_id_gen(phydev, pSa->direction, sa_index);
+    }
+    else
+    {
+        gen_id = pSa->context_id;
+    }
+
+    // Compute offsets for various fields.
+    __rtk_phylib_macsec_hw_sa_offset_parse(pSa, &offs);
+
+    // Fill the entire SA record with zeros.
+    rtk_phylib_memset(pSa_raw, 0, PHY_MACSEC_MAX_SA_SIZE * sizeof(uint32_t));
+
+    if (pSa->direction == RTK_MACSEC_DIR_EGRESS)
+    {
+        if((pSa->flags & RTK_PHY_MACSEC_SA_FLAG_XPN) != 0)
+        {
+            pSa_raw[0] = MACSEC_SAB_CW0_MACSEC_EG64;
+        }
+        else
+        {
+            pSa_raw[0] = MACSEC_SAB_CW0_MACSEC_EG32;
+        }
+        seq = pSa->seq;
+        seq_h = pSa->seq_h;
+        pSa_raw[0] |= (pSa->an & 0x3) << 26;
+    }
+    else //RTK_MACSEC_DIR_INGRESS
+    {
+        if((pSa->flags & RTK_PHY_MACSEC_SA_FLAG_XPN) != 0)
+        {
+            pSa_raw[0] = MACSEC_SAB_CW0_MACSEC_IG64;
+        }
+        else
+        {
+            pSa_raw[0] = MACSEC_SAB_CW0_MACSEC_IG32;
+        }
+        seq = (pSa->seq == 0 && pSa->seq_h == 0) ? 1 : pSa->seq;
+        seq_h = pSa->seq_h;
+    }
+
+    switch (pSa->key_bytes)
+    {
+        case 16:
+            pSa_raw[0] |= MACSEC_SAB_CW0_AES128;
+            break;
+        case 32:
+            pSa_raw[0] |= MACSEC_SAB_CW0_AES256;
+            break;
+        default:
+            PR_ERR("unsupported AES key size:%d", pSa->key_bytes);
+            return RTK_PHYLIB_ERR_INPUT;
+    }
+
+    // Fill in ID
+    pSa_raw[1] = gen_id;
+
+    // Fill Key and HKey
+    __rtk_phylib_macsec_copy_key_to_raw(pSa_raw, offs.key_offs, pSa->key, pSa->key_bytes);
+    /* generate hkey from key, encrypt a single all-zero block */
+    __rtk_macsec_aes_encrypt((uint8_t *)(pSa_raw + offs.hkey_offs),  hkey, pSa->key, pSa->key_bytes);
+    __rtk_phylib_macsec_copy_key_to_raw(pSa_raw, offs.hkey_offs, hkey, 16);
+
+    // Fill in sequence number/seqmask.
+    pSa_raw[offs.seq_offs] = seq;
+    if ((pSa->flags & RTK_PHY_MACSEC_SA_FLAG_XPN) != 0)
+        pSa_raw[offs.seq_offs + 1] = seq_h;
+
+    if (pSa->direction == RTK_MACSEC_DIR_INGRESS)
+        pSa_raw[offs.mask_offs] = pSa->replay_window;
+
+    // Fill in CtxSalt field.
+    if (offs.ctx_salt_offs > 0)
+    {
+        //__rtk_phylib_macsec_copy_key_to_raw(&phy_macsec_info[unit]->ssci[port], 0, pSa->ssci, 8);
+        macsec_db->sa_info[sa_index].ssci[0] = pSa->ssci[0];
+        macsec_db->sa_info[sa_index].ssci[1] = pSa->ssci[1];
+        macsec_db->sa_info[sa_index].ssci[2] = pSa->ssci[2];
+        macsec_db->sa_info[sa_index].ssci[3] = pSa->ssci[3];
+
+        //[0] = most significant 32-bits Salt XOR-ed with SSCI
+        tmp =  (pSa->salt[0] ^ pSa->ssci[0]) |
+              ((pSa->salt[1] ^ pSa->ssci[1]) << 8)  |
+              ((pSa->salt[2] ^ pSa->ssci[2]) << 16) |
+              ((pSa->salt[3] ^ pSa->ssci[3]) << 24);
+        pSa_raw[offs.ctx_salt_offs] = tmp;
+        //[1:2] = lower 64-bits Salt
+        __rtk_phylib_macsec_copy_key_to_raw(pSa_raw, offs.ctx_salt_offs + 1, pSa->salt + 4, 8);
+    }
+
+    // Fill in IV(SCI) fields.
+    if (offs.iv_offs > 0)
+    {
+        __rtk_phylib_macsec_copy_key_to_raw(pSa_raw, offs.iv_offs, pSa->sci, 8);
+    }
+
+    // Fill in update control fields.
+    if(offs.upd_ctrl_offs > 0)
+    {
+        tmp = (pSa->next_sa_index & MASK_14_BITS) |
+            ((pSa->flow_index & MASK_15_BITS) << 16);
+
+        if (pSa->update_en)
+            tmp |= BIT_31;
+        if (pSa->next_sa_valid)
+            tmp |= BIT_15;
+        if (pSa->sa_expired_irq)
+            tmp |= BIT_14;
+
+        pSa_raw[offs.upd_ctrl_offs] = tmp;
+    }
+
+    return ret;
+}
+
+int32 __rtk_phylib_macsec_hw_sa_del(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 sa_index)
+{
+    int32 ret = 0;
+    uint32 sa_raw[PHY_MACSEC_MAX_SA_SIZE] = {0};
+
+    MACSEC_REG_ARRAY_SET(phydev, dir, MACSEC_REG_XFORM_REC_OFFS(sa_index, dir, 0), sa_raw, MACSEC_XFORM_REC_SIZE(dir));
+
+    return ret;
+}
+
+static int32 __rtk_phylib_macsec_hw_sa_set(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 sa_index, phy_macsec_sa_params_t *pSa)
+{
+    int32 ret = 0;
+    uint32 sa_raw[PHY_MACSEC_MAX_SA_SIZE] = {0};
+
+    if (pSa == NULL)
+        return RTK_PHYLIB_ERR_INPUT;
+
+    if (pSa->direction == RTK_MACSEC_DIR_EGRESS && dir == RTK_MACSEC_DIR_INGRESS)
+    {
+        PR_ERR("direction mismatch!(set egress entry on ingress)");
+        return RTK_PHYLIB_ERR_INPUT;
+    }
+    if (pSa->direction == RTK_MACSEC_DIR_INGRESS && dir == RTK_MACSEC_DIR_EGRESS)
+    {
+        PR_ERR("direction mismatch!(set ingress entry on egress)");
+        return RTK_PHYLIB_ERR_INPUT;
+    }
+
+    if ((ret = __rtk_phylib_macsec_hw_sa_build(phydev, sa_index, pSa, sa_raw)) != 0)
+        return ret;
+
+    MACSEC_REG_ARRAY_SET(phydev, dir, MACSEC_REG_XFORM_REC_OFFS(sa_index, dir, 0), sa_raw, MACSEC_XFORM_REC_SIZE(dir));
+
+    #ifdef MACSEC_DBG_PRINT
+    {
+        uint32 __i = 0;
+        PR_DBG("flow_index: %u\n", pSa->flow_index);
+        PR_DBG("next_sa_index: %u\n", pSa->next_sa_index);
+        PR_DBG("update_en: %u, next_sa_valid: %u, sa_expired_irq:%u\n", pSa->update_en, pSa->next_sa_valid,  pSa->sa_expired_irq);
+
+        PR_DBG("SA offset = 0x%04X\n", MACSEC_REG_XFORM_REC_OFFS(sa_index, dir, 0));
+        for (__i = 0; __i < MACSEC_XFORM_REC_SIZE(dir); __i++)
+        {
+            PR_DBG("SA[%02u] = 0x%08X\n", __i, sa_raw[__i]);
+        }
+    }
+    #endif
+
+    return ret;
+}
+
+static int32 __rtk_phylib_macsec_hw_sa_get(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 sa_index, phy_macsec_sa_params_t *pSa)
+{
+    int32 ret = 0;
+    uint32 sa_raw[PHY_MACSEC_MAX_SA_SIZE] = {0};
+
+    if (pSa == NULL)
+        return RTK_PHYLIB_ERR_INPUT;
+
+    MACSEC_REG_ARRAY_GET(phydev, dir, MACSEC_REG_XFORM_REC_OFFS(sa_index, dir, 0), sa_raw, MACSEC_XFORM_REC_SIZE(dir));
+
+    __rtk_phylib_macsec_hw_sa_parse(phydev, sa_index, sa_raw, pSa);
+
+    return ret;
+}
+
+static int32 __rtk_phylib_macsec_hw_flow_action_rule_set(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 flow_index, phy_macsec_flow_action_t *pAct)
+{
+    struct rtk_phy_priv *priv = phydev->priv;
+    rtk_macsec_port_info_t *macsec_db = priv->macsec;
+
+    int32  ret = 0;
+    uint32 sa_index = pAct->sa_index;
+    uint8  flow_type = 0;
+    uint8  dest_port = 0;
+    uint8  drop_non_reserved = 0; //do not drop
+    uint8  flow_crypt_auth = 0;
+    uint8  drop_action = 0; // CRC
+    uint8  protect = 0;
+    uint8  sa_in_use = 0;
+    uint8  include_sci = 0;
+    uint8  validate_frames = 0;
+    uint8  tag_bypass_size = 0;
+    uint8  sa_index_update = 0;
+    uint8  conf_offset = 0;
+    uint8  conf_protect = 0;
+
+    if (flow_index >= MACSEC_SA_MAX(macsec_db))
+    {
+        PR_ERR("flow_index out of range!");
+        return RTK_PHYLIB_ERR_INPUT;
+    }
+    if (pAct->flow_type == RTK_MACSEC_FLOW_EGRESS && dir == RTK_MACSEC_DIR_INGRESS)
+    {
+        PR_ERR("flow_type mismatch!(set egress entry on ingress)");
+        return RTK_PHYLIB_ERR_INPUT;
+    }
+    if (pAct->flow_type == RTK_MACSEC_FLOW_INGRESS && dir == RTK_MACSEC_DIR_EGRESS)
+    {
+        PR_ERR("flow_type mismatch!(set ingress entry on egress)");
+        return RTK_PHYLIB_ERR_INPUT;
+    }
+
+    dest_port = pAct->dest_port;
+    switch (pAct->flow_type)
+    {
+        case RTK_MACSEC_FLOW_EGRESS:
+            flow_type = 0b11;
+            dest_port = RTK_MACSEC_PORT_COMMON;
+            flow_crypt_auth = 0b0;
+            protect = pAct->params.egress.protect_frame;
+            sa_in_use = pAct->params.egress.sa_in_use;
+            include_sci = pAct->params.egress.include_sci;
+            validate_frames = pAct->params.egress.use_es | ( pAct->params.egress.use_scb << 1);
+            tag_bypass_size = pAct->params.egress.tag_bypass_size;
+            conf_offset = pAct->params.egress.confidentiality_offset;
+            conf_protect = pAct->params.egress.conf_protect;
+            break;
+
+        case RTK_MACSEC_FLOW_INGRESS:
+            flow_type = 0b10;
+            dest_port = RTK_MACSEC_PORT_CONTROLLED;
+            flow_crypt_auth = 0b0;
+            protect = pAct->params.ingress.replay_protect;
+            sa_in_use = pAct->params.ingress.sa_in_use;
+
+            switch (pAct->params.ingress.validate_frames)
+            {
+               case RTK_MACSEC_VALIDATE_DISABLE:
+                   validate_frames = 0b00;
+                   break;
+               case RTK_MACSEC_VALIDATE_CHECK:
+                   validate_frames = 0b01;
+                   break;
+               case RTK_MACSEC_VALIDATE_STRICT:
+                   validate_frames = 0b10;
+                   break;
+               default:
+                   PR_ERR("unknown type of validate_frames!");
+                   return RTK_PHYLIB_ERR_INPUT;
+            }
+            conf_offset = pAct->params.ingress.confidentiality_offset;
+            break;
+
+        case RTK_MACSEC_FLOW_BYPASS:
+            flow_type = 0b00;
+            flow_crypt_auth = 0b0;
+            //sa_in_use = 1;
+            sa_in_use = pAct->params.bypass_drop.sa_in_use;
+            break;
+
+        case RTK_MACSEC_FLOW_DROP:
+            flow_type = 0b01;
+            flow_crypt_auth = 0b0;
+            //sa_in_use = 1;
+            sa_in_use = pAct->params.bypass_drop.sa_in_use;
+            break;
+
+        default:
+            return RTK_PHYLIB_ERR_INPUT;
+    }
+
+    ret = __rtk_phylib_macsec_hw_flow_action_write(
+        phydev,
+        dir, flow_index,
+        sa_index,
+        flow_type,
+        dest_port,
+        drop_non_reserved,
+        flow_crypt_auth,
+        drop_action,
+        protect,
+        sa_in_use,
+        include_sci,
+        validate_frames,
+        tag_bypass_size,
+        sa_index_update,
+        conf_offset,
+        conf_protect);
+
+    return ret;
+}
+
+static int32 __rtk_phylib_macsec_hw_flow_action_rule_get(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 flow_index, phy_macsec_flow_action_t *pAct)
+{
+    int32 ret = 0;
+    uint32 reg = 0, reg_data = 0;
+    uint8 flow_type = 0;
+
+    if(pAct == NULL)
+        return RTK_PHYLIB_ERR_INPUT;
+
+    rtk_phylib_memset(pAct, 0, sizeof(phy_macsec_flow_action_t));
+
+    reg = MACSEC_REG_SAM_FLOW_CTRL(flow_index);
+    MACSEC_REG_GET(phydev, dir, reg, &reg_data);
+
+    pAct->dest_port = (reg_data >> 2) & MASK_2_BITS;
+
+    pAct->sa_index  = (reg_data >> 8) & MASK_8_BITS;
+
+    flow_type = reg_data & MASK_2_BITS;
+    switch (flow_type)
+    {
+        case 0b11:
+            pAct->flow_type = RTK_MACSEC_FLOW_EGRESS;
+            pAct->params.egress.protect_frame          = (reg_data >> 16) & MASK_1_BITS;
+            pAct->params.egress.sa_in_use              = (reg_data >> 17) & MASK_1_BITS;
+            pAct->params.egress.include_sci            = (reg_data >> 18) & MASK_1_BITS;
+            pAct->params.egress.use_es                 = (reg_data >> 19) & MASK_1_BITS;
+            pAct->params.egress.use_scb                = (reg_data >> 20) & MASK_1_BITS;
+            pAct->params.egress.tag_bypass_size        = (reg_data >> 21) & MASK_2_BITS;
+            pAct->params.egress.sa_index_update_by_hw  = (reg_data >> 23) & MASK_2_BITS;
+            pAct->params.egress.confidentiality_offset = (reg_data >> 24) & MASK_7_BITS;
+            pAct->params.egress.conf_protect           = (reg_data >> 31) & MASK_1_BITS;
+            break;
+        case 0b10:
+            pAct->flow_type = RTK_MACSEC_FLOW_INGRESS;
+            pAct->params.ingress.replay_protect         = (reg_data >> 16) & MASK_1_BITS;
+            switch ((reg_data >> 19) & MASK_2_BITS)
+            {
+                case 0b00:
+                    pAct->params.ingress.validate_frames = RTK_MACSEC_VALIDATE_DISABLE;
+                    break;
+                case 0b01:
+                    pAct->params.ingress.validate_frames = RTK_MACSEC_VALIDATE_CHECK;
+                    break;
+                case 0b10:
+                    pAct->params.ingress.validate_frames = RTK_MACSEC_VALIDATE_STRICT;
+                    break;
+                default:
+                    return RTK_PHYLIB_ERR_FAILED;
+            }
+
+            pAct->params.ingress.confidentiality_offset = (reg_data >> 24) & MASK_7_BITS;
+            break;
+        case 0b01:
+        case 0b00:
+        default:
+            pAct->flow_type = (flow_type == 0b01) ? RTK_MACSEC_FLOW_DROP : RTK_MACSEC_FLOW_BYPASS;
+            pAct->params.bypass_drop.sa_in_use = (reg_data >> 17) & MASK_1_BITS;
+            break;
+    }
+
+    return ret;
+}
+
+static int32 __rtk_phylib_macsec_hw_flow_action_rule_del(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 flow_index)
+{
+    int32 ret = 0;
+
+    ret = __rtk_phylib_macsec_hw_flow_action_write(
+        phydev,
+        dir, flow_index,
+        0,
+        0, 0, 0, 0, 0, 0,
+        0, //SA not in use
+        0, 0, 0, 0, 0, 0);
+    return ret;
+}
+
+
+static int32 __rtk_phylib_macsec_hw_flow_match_rule_set(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 flow_index, phy_macsec_flow_match_t *pMatch)
+{
+    struct rtk_phy_priv *priv = phydev->priv;
+    rtk_macsec_port_info_t *macsec_db = priv->macsec;
+
+    int32  ret = 0;
+    uint32 reg_data = 0;
+    uint32 srcPort = 0;
+    uint16 tmp = 0;
+
+    if (pMatch == NULL)
+        return RTK_PHYLIB_ERR_INPUT;
+
+    if (flow_index >= MACSEC_SA_MAX(macsec_db))
+    {
+        PR_ERR("flow_index out of range!");
+        return RTK_PHYLIB_ERR_INPUT;
+    }
+
+    {
+        reg_data = 0;
+        reg_data |= (uint32)((((uint32)pMatch->mac_sa[3]) & MASK_8_BITS) << 24);
+        reg_data |= (uint32)((((uint32)pMatch->mac_sa[2]) & MASK_8_BITS) << 16);
+        reg_data |= (uint32)((((uint32)pMatch->mac_sa[1]) & MASK_8_BITS) << 8);
+        reg_data |= (uint32)((((uint32)pMatch->mac_sa[0]) & MASK_8_BITS));
+        MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_MAC_SA_MATCH_LO(flow_index), reg_data);
+
+        reg_data = 0;
+        tmp = ((pMatch->etherType & 0xFF) << 8) | (pMatch->etherType >> 8);
+        reg_data |= (uint32)((((uint32)tmp)  & MASK_16_BITS) << 16);
+
+        reg_data |= (uint32)((((uint32)pMatch->mac_sa[5]) & MASK_8_BITS) << 8);
+        reg_data |= (uint32)((((uint32)pMatch->mac_sa[4]) & MASK_8_BITS));
+        MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_MAC_SA_MATCH_HI(flow_index), reg_data);
+    }
+
+    {
+        reg_data = 0;
+        reg_data |= (uint32)((((uint32)pMatch->mac_da[3]) & MASK_8_BITS) << 24);
+        reg_data |= (uint32)((((uint32)pMatch->mac_da[2]) & MASK_8_BITS) << 16);
+        reg_data |= (uint32)((((uint32)pMatch->mac_da[1]) & MASK_8_BITS) << 8);
+        reg_data |= (uint32)((((uint32)pMatch->mac_da[0]) & MASK_8_BITS));
+        MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_MAC_DA_MATCH_LO(flow_index), reg_data);
+
+        reg_data = 0;
+        reg_data |= (uint32)((((uint32)pMatch->vlan_id)   & MASK_12_BITS) << 16);
+        reg_data |= (uint32)((((uint32)pMatch->mac_da[5]) & MASK_8_BITS) << 8);
+        reg_data |= (uint32)((((uint32)pMatch->mac_da[4]) & MASK_8_BITS));
+        MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_MAC_DA_MATCH_HI(flow_index), reg_data);
+    }
+
+    {
+        srcPort = pMatch->sourcePort;
+
+        reg_data = 0;
+        reg_data |= (pMatch->fVLANValid) ? (BIT_0) : 0;
+        reg_data |= (pMatch->fQinQFound) ? (BIT_1) : 0;
+        reg_data |= (pMatch->fSTagValid) ? (BIT_2) : 0;
+        reg_data |= (pMatch->fQTagFound) ? (BIT_3) : 0;
+
+        reg_data |= (pMatch->fControlPacket) ? (BIT_7)  : 0;
+        reg_data |= (pMatch->fUntagged) ?      (BIT_8)  : 0;
+        reg_data |= (pMatch->fTagged) ?        (BIT_9)  : 0;
+        reg_data |= (pMatch->fBadTag) ?        (BIT_10) : 0;
+        reg_data |= (pMatch->fKayTag) ?        (BIT_11) : 0;
+
+        reg_data |= (uint32)((((uint32)pMatch->macsec_TCI_AN)    & MASK_8_BITS) << 24);
+        reg_data |= (uint32)((((uint32)pMatch->matchPriority)    & MASK_4_BITS) << 16);
+        reg_data |= (uint32)((((uint32)srcPort)                & MASK_2_BITS) << 12);
+        reg_data |= (uint32)((((uint32)pMatch->vlanUserPriority) & MASK_3_BITS) << 4);
+        MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_MISC_MATCH(flow_index), reg_data);
+    }
+
+    {
+        #ifdef MACSEC_DBG_PRINT
+        {
+            PR_DBG("[%s]SCI = 0x%02X%02X%02X%02X%02X%02X%02X%02X\n", __FUNCTION__,
+                pMatch->sci[0], pMatch->sci[1], pMatch->sci[2], pMatch->sci[3],
+                pMatch->sci[4], pMatch->sci[5], pMatch->sci[6], pMatch->sci[7]);
+        }
+        #endif
+        reg_data = 0;
+        reg_data |= (uint32)(((uint32)(pMatch->sci[3]) & MASK_8_BITS) << 24);
+        reg_data |= (uint32)(((uint32)(pMatch->sci[2]) & MASK_8_BITS) << 16);
+        reg_data |= (uint32)(((uint32)(pMatch->sci[1]) & MASK_8_BITS) << 8);
+        reg_data |= (uint32)(((uint32)(pMatch->sci[0]) & MASK_8_BITS));
+        MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_SCI_MATCH_LO(flow_index), reg_data);
+        #ifdef MACSEC_DBG_PRINT
+        {
+            PR_DBG("[%s]SCI_LO = 0x%08X\n", __FUNCTION__, reg_data);
+            MACSEC_REG_GET(phydev, dir, MACSEC_REG_SAM_SCI_MATCH_LO(flow_index), &reg_data);
+            PR_DBG("CHECK read[0x%04X] = 0x%08X\n", MACSEC_REG_SAM_SCI_MATCH_LO(flow_index), reg_data);
+        }
+        #endif
+
+        reg_data = 0;
+        reg_data |= (uint32)(((uint32)(pMatch->sci[7]) & MASK_8_BITS) << 24);
+        reg_data |= (uint32)(((uint32)(pMatch->sci[6]) & MASK_8_BITS) << 16);
+        reg_data |= (uint32)(((uint32)(pMatch->sci[5]) & MASK_8_BITS) << 8);
+        reg_data |= (uint32)(((uint32)(pMatch->sci[4]) & MASK_8_BITS));
+        MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_SCI_MATCH_HI(flow_index), reg_data);
+        #ifdef MACSEC_DBG_PRINT
+        {
+            PR_DBG("[%s]SCI_HI = 0x%08X\n", __FUNCTION__, reg_data);
+            MACSEC_REG_GET(phydev, dir, MACSEC_REG_SAM_SCI_MATCH_HI(flow_index), &reg_data);
+            PR_DBG("CHECK read[0x%04X] = 0x%08X\n", MACSEC_REG_SAM_SCI_MATCH_HI(flow_index), reg_data);
+        }
+        #endif
+    }
+
+    {
+        reg_data = 0;
+        reg_data |= pMatch->matchMask;
+        MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_MASK(flow_index), reg_data);
+    }
+
+    {
+        reg_data = 0;
+        reg_data |= (uint32)((((uint32)pMatch->flow_index) & MASK_8_BITS) << 16);
+        reg_data |= (uint32)((((uint32)pMatch->vlanUpInner) & MASK_3_BITS) << 12);
+        reg_data |= (uint32)((((uint32)pMatch->vlanIdInner) & MASK_12_BITS));
+        MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_EXT_MATCH(flow_index), reg_data);
+    }
+    return ret;
+}
+
+static int32 __rtk_phylib_macsec_hw_flow_match_rule_get(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 flow_index, phy_macsec_flow_match_t *pMatch)
+{
+    int32 ret = 0;
+    uint32 reg = 0, reg_data = 0;
+    uint16 tmp = 0;
+
+    if (pMatch == NULL)
+        return RTK_PHYLIB_ERR_INPUT;
+
+    rtk_phylib_memset(pMatch, 0, sizeof(phy_macsec_flow_match_t));
+
+    reg = MACSEC_REG_SAM_MAC_SA_MATCH_LO(flow_index);
+    MACSEC_REG_GET(phydev, dir, reg, &reg_data);
+    PR_DBG("read[0x%04X] = 0x%08X\n", reg, reg_data);
+    pMatch->mac_sa[3] = (uint8)((reg_data >> 24) & MASK_8_BITS);
+    pMatch->mac_sa[2] = (uint8)((reg_data >> 16) & MASK_8_BITS);
+    pMatch->mac_sa[1] = (uint8)((reg_data >> 8)  & MASK_8_BITS);
+    pMatch->mac_sa[0] = (uint8)((reg_data)       & MASK_8_BITS);
+
+    reg = MACSEC_REG_SAM_MAC_SA_MATCH_HI(flow_index);
+    MACSEC_REG_GET(phydev, dir, reg, &reg_data);
+    PR_DBG("read[0x%04X] = 0x%08X\n", reg, reg_data);
+    tmp = (uint16)((reg_data >> 16) & MASK_16_BITS);
+    pMatch->etherType = ((tmp & 0xFF) << 8) | ((tmp >> 8) & 0xFF);
+    pMatch->mac_sa[5] = (uint8)((reg_data >> 8)  & MASK_8_BITS);
+    pMatch->mac_sa[4] = (uint8)((reg_data)       & MASK_8_BITS);
+
+    reg = MACSEC_REG_SAM_MAC_DA_MATCH_LO(flow_index);
+    MACSEC_REG_GET(phydev, dir, reg, &reg_data);
+    PR_DBG("read[0x%04X] = 0x%08X\n", reg, reg_data);
+    pMatch->mac_da[3] = (uint8)((reg_data >> 24) & MASK_8_BITS);
+    pMatch->mac_da[2] = (uint8)((reg_data >> 16) & MASK_8_BITS);
+    pMatch->mac_da[1] = (uint8)((reg_data >> 8)  & MASK_8_BITS);
+    pMatch->mac_da[0] = (uint8)((reg_data)       & MASK_8_BITS);
+
+    reg = MACSEC_REG_SAM_MAC_DA_MATCH_HI(flow_index);
+    MACSEC_REG_GET(phydev, dir, reg, &reg_data);
+    PR_DBG("read[0x%04X] = 0x%08X\n", reg, reg_data);
+    pMatch->vlan_id   = (uint16)((reg_data >> 16) & MASK_12_BITS);
+    pMatch->mac_da[5] = (uint8)((reg_data >> 8)   & MASK_8_BITS);
+    pMatch->mac_da[4] = (uint8)((reg_data)        & MASK_8_BITS);
+
+    reg = MACSEC_REG_SAM_MISC_MATCH(flow_index);
+    MACSEC_REG_GET(phydev, dir, reg, &reg_data);
+    PR_DBG("read[0x%04X] = 0x%08X\n", reg, reg_data);
+    pMatch->fVLANValid = (reg_data & BIT_0) ? 1 : 0;
+    pMatch->fQinQFound = (reg_data & BIT_1) ? 1 : 0;
+    pMatch->fSTagValid = (reg_data & BIT_2) ? 1 : 0;
+    pMatch->fQTagFound = (reg_data & BIT_3) ? 1 : 0;
+
+    pMatch->fControlPacket = (reg_data & BIT_7) ? 1 : 0;
+    pMatch->fUntagged      = (reg_data & BIT_8) ? 1 : 0;
+    pMatch->fTagged        = (reg_data & BIT_9) ? 1 : 0;
+    pMatch->fBadTag        = (reg_data & BIT_10) ? 1 : 0;
+    pMatch->fKayTag        = (reg_data & BIT_11) ? 1 : 0;
+
+    pMatch->macsec_TCI_AN = (uint8)((reg_data >> 24) & MASK_8_BITS);
+    pMatch->matchPriority = (uint8)((reg_data >> 16) & MASK_4_BITS);
+    pMatch->sourcePort =    (uint8)((reg_data >> 12) & MASK_2_BITS);
+
+    pMatch->vlanUserPriority = (uint8)((reg_data >> 4) & MASK_3_BITS);
+
+    reg = MACSEC_REG_SAM_SCI_MATCH_LO(flow_index);
+    MACSEC_REG_GET(phydev, dir, reg, &reg_data);
+    PR_DBG("read[0x%04X] = 0x%08X\n", reg, reg_data);
+    pMatch->sci[3] = (uint8)((reg_data >> 24) & MASK_8_BITS);
+    pMatch->sci[2] = (uint8)((reg_data >> 16) & MASK_8_BITS);
+    pMatch->sci[1] = (uint8)((reg_data >> 8)  & MASK_8_BITS);
+    pMatch->sci[0] = (uint8)((reg_data)       & MASK_8_BITS);
+
+    reg = MACSEC_REG_SAM_SCI_MATCH_HI(flow_index);
+    MACSEC_REG_GET(phydev, dir, reg, &reg_data);
+    PR_DBG("read[0x%04X] = 0x%08X\n", reg, reg_data);
+    pMatch->sci[7] = (uint8)((reg_data >> 24) & MASK_8_BITS);
+    pMatch->sci[6] = (uint8)((reg_data >> 16) & MASK_8_BITS);
+    pMatch->sci[5] = (uint8)((reg_data >> 8)  & MASK_8_BITS);
+    pMatch->sci[4] = (uint8)((reg_data)       & MASK_8_BITS);
+
+    reg = MACSEC_REG_SAM_MASK(flow_index);
+    MACSEC_REG_GET(phydev, dir, reg, &reg_data);
+    PR_DBG("read[0x%04X] = 0x%08X\n", reg, reg_data);
+    pMatch->matchMask = reg_data;
+
+    reg = MACSEC_REG_SAM_EXT_MATCH(flow_index);
+    MACSEC_REG_GET(phydev, dir, reg, &reg_data);
+    PR_DBG("read[0x%04X] = 0x%08X\n", reg, reg_data);
+    pMatch->flow_index  = (uint32) ((reg_data >> 16) & MASK_8_BITS);
+    pMatch->vlanUpInner = (uint8)  ((reg_data >> 12) & MASK_3_BITS);
+    pMatch->vlanIdInner = (uint16) ((reg_data) & MASK_12_BITS);
+
+    return ret;
+}
+
+static int32 __rtk_phylib_macsec_hw_flow_match_rule_del(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 flow_index)
+{
+    int32  ret = 0;
+    uint32 reg_data = 0;
+
+    MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_MAC_SA_MATCH_LO(flow_index), reg_data);
+    MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_MAC_SA_MATCH_HI(flow_index), reg_data);
+    MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_MAC_DA_MATCH_LO(flow_index), reg_data);
+    MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_MAC_DA_MATCH_HI(flow_index), reg_data);
+    MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_MISC_MATCH(flow_index), reg_data);
+    MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_SCI_MATCH_LO(flow_index), reg_data);
+    MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_SCI_MATCH_HI(flow_index), reg_data);
+    MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_MASK(flow_index), reg_data);
+    MACSEC_REG_SET(phydev, dir, MACSEC_REG_SAM_EXT_MATCH(flow_index), reg_data);
+
+    return ret;
+}
+
+static int32 __rtk_phylib_macsec_hw_flow_enable_get(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 flow_index, uint32 *pEnable)
+{
+    int32  ret = 0;
+    uint32 reg_data;
+
+    MACSEC_REG_GET(phydev, dir, MACSEC_REG_SAM_ENTRY_ENABLE(flow_index/32), &reg_data);
+    *pEnable = (reg_data & (BIT_0 << (flow_index % 32))) ? ENABLED : DISABLED;
+
+    return ret;
+}
+
+static int32 __rtk_phylib_macsec_hw_flow_enable_set(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 flow_index, uint32 enable)
+{
+    int32        ret = 0;
+    uint32       reg_data = 0;
+    uint32       cur_ena = 0;
+    WAIT_COMPLETE_VAR();
+
+    if ((ret = __rtk_phylib_macsec_hw_flow_enable_get(phydev, dir, flow_index, &cur_ena)) != 0)
+    {
+        return ret;
+    }
+
+    if (enable != cur_ena)
+    {
+        MACSEC_REG_SET(phydev, dir, (enable == ENABLED)?
+                   MACSEC_REG_SAM_ENTRY_SET(flow_index/32) : MACSEC_REG_SAM_ENTRY_CLEAR(flow_index/32),
+                   BIT_0 << (flow_index % 32));
+
+        if (enable == 0)
+        {
+            WAIT_COMPLETE(10000000)
+            {
+                MACSEC_REG_GET(phydev, dir, MACSEC_REG_SAM_IN_FLIGHT, &reg_data);
+                if ((reg_data & 0x3F) == 0)
+                    break;
+            }
+            if (WAIT_COMPLETE_IS_TIMEOUT())
+            {
+                ret = RTK_PHYLIB_ERR_TIMEOUT;
+                PR_ERR("flow delete timeout, val=0x%x", (reg_data & 0x3F));
+                return ret;
+            }
+        }
+
+    }
+
+    return ret;
+}
+
+int32 rtk_phylib_macsec_init(rtk_phydev *phydev)
+{
+    int32  ret = 0;
+    uint32 data = 0;
+    struct rtk_phy_priv *priv = phydev->priv;
+
+    switch (priv->phytype)
+    {
+        case RTK_PHYLIB_RTL8261N:
+        case RTK_PHYLIB_RTL8264B:
+        case RTK_PHYLIB_RTL8251L:
+        case RTK_PHYLIB_RTL8254B:
+            priv->macsec->macsec_reg_get = rtk_phylib_826xb_macsec_read;
+            priv->macsec->macsec_reg_set = rtk_phylib_826xb_macsec_write;
+            break;
+        default:
+            return RTK_PHYLIB_ERR_FAILED;
+    }
+
+    //read HW version
+    MACSEC_REG_GET(phydev, RTK_MACSEC_DIR_EGRESS, 0xFFFC, &data);
+    if ((data & MASK_8_BITS) != 160)
+        PR_ERR("[%s] HW ver: 0x%X, mismatch!\n", __FUNCTION__, (data & MASK_8_BITS));
+    else
+        PR_INFO("[%s] HW ver: 0x%X\n", __FUNCTION__, (data & MASK_8_BITS));
+
+    MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_EGRESS,  MACSEC_REG_COUNT_CTRL,     0x00000001);
+    MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_EGRESS,  MACSEC_REG_COUNT_CTRL,     0x0000000c);
+    MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_EGRESS,  MACSEC_REG_COUNT_SECFAIL1, 0x80fe0000);
+    MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_EGRESS,  MACSEC_REG_MISC_CONTROL,   0x02000046);
+    MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_EGRESS,  MACSEC_REG_CTX_CTRL,       0xe5880618);
+    MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_EGRESS,  MACSEC_REG_CTX_UPD_CTRL,   0x00000003);
+
+    MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_INGRESS, MACSEC_REG_COUNT_CTRL,     0x00000001);
+    MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_INGRESS, MACSEC_REG_COUNT_CTRL,     0x0000000c);
+    MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_INGRESS, MACSEC_REG_COUNT_SECFAIL1, 0x80fe0000);
+    MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_INGRESS, MACSEC_REG_MISC_CONTROL,   0x01001046);
+    MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_INGRESS, MACSEC_REG_CTX_CTRL,       0xe5880614);
+    MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_INGRESS, MACSEC_REG_CTX_UPD_CTRL,   0x00000003);
+    MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_INGRESS, MACSEC_REG_SAM_CP_TAG,     0xe0fac688);
+    MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_INGRESS, MACSEC_REG_IG_CC_CONTROL,  0x0000C000);
+    MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_INGRESS, MACSEC_REG_SAM_NM_PARAMS,  0xe588003f);
+
+    /* default Egress non-match pkt action:
+       bypass: NCP - KaY tag; CP - Untagged
+       drop: others
+       */
+    MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_EGRESS,  MACSEC_REG_SAM_NM_FLOW_NCP, 0x00010101);
+    MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_EGRESS,  MACSEC_REG_SAM_NM_FLOW_CP,  0x01010100);
+    /* default Ingress non-match pkt action:
+       bypass: NCP - KaY tag,Tagged; CP - Untagged
+       drop: others
+       */
+    MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_INGRESS, MACSEC_REG_SAM_NM_FLOW_NCP, 0x08090809);
+    MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_INGRESS, MACSEC_REG_SAM_NM_FLOW_CP,  0x09090908);
+
+    MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_EGRESS,  0xF810, 0x000003ff);
+    MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_EGRESS,  0xF808, 0x00000300);
+
+    MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_EGRESS, 0x780C, 0x8e880000);
+    MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_EGRESS, 0x78FC,  0x80200);
+    MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_INGRESS, 0x780C, 0x8e880000);
+    MACSEC_REG_SET(phydev, RTK_MACSEC_DIR_INGRESS, 0x78FC,  0x80200);
+
+    return 0;
+}
+
+int32 rtk_phylib_macsec_enable_get(rtk_phydev *phydev, uint32 *pEna)
+{
+    int32  ret = 0;
+    struct rtk_phy_priv *priv = phydev->priv;
+    uint32 val = 0;
+    switch (priv->phytype)
+    {
+        case RTK_PHYLIB_RTL8261N:
+        case RTK_PHYLIB_RTL8264B:
+        case RTK_PHYLIB_RTL8251L:
+        case RTK_PHYLIB_RTL8254B:
+            RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_macsec_bypass_get(phydev, &val));
+            *pEna = (val == 0) ? 1 : 0;
+            break;
+        default:
+            return RTK_PHYLIB_ERR_FAILED;
+    }
+    return ret;
+}
+int32 rtk_phylib_macsec_enable_set(rtk_phydev *phydev, uint32 ena)
+{
+    int32  ret = 0;
+    struct rtk_phy_priv *priv = phydev->priv;
+
+    switch (priv->phytype)
+    {
+        case RTK_PHYLIB_RTL8261N:
+        case RTK_PHYLIB_RTL8264B:
+        case RTK_PHYLIB_RTL8251L:
+        case RTK_PHYLIB_RTL8254B:
+            ret = rtk_phylib_826xb_macsec_bypass_set(phydev, (ena == 0) ? 1 : 0);
+            break;
+        default:
+            ret = RTK_PHYLIB_ERR_FAILED;
+    }
+    PR_DBG("[%s]ena=%u ret=%d\n", __FUNCTION__, ena, ret);
+    return ret;
+}
+
+int32 rtk_phylib_macsec_sc_create(rtk_phydev *phydev, rtk_macsec_dir_t dir,
+    rtk_macsec_sc_t *pSc, uint32 *pSc_id, uint8 active)
+{
+    struct rtk_phy_priv *priv = phydev->priv;
+    rtk_macsec_port_info_t *macsec_db = priv->macsec;
+
+    int32  ret = 0;
+    uint8 an = 0, tci_an = 0;
+    uint32 i = 0, sc_id = 0xFFFFFFFF;
+    uint32 sa_id = 0;
+    uint32 flow_base = 0;
+    rtk_macsec_cipher_t cs = RTK_MACSEC_CIPHER_GCM_ASE_128;
+    phy_macsec_flow_action_t flow;
+    phy_macsec_flow_match_t match;
+    phy_macsec_sa_params_t hwsa;
+
+    if (pSc == NULL || pSc_id == NULL)
+        return RTK_PHYLIB_ERR_INPUT;
+
+    for (i = 0; i < MACSEC_SC_MAX(macsec_db); i++)
+    {
+        if(MACSEC_SC_IS_CLEAR(macsec_db, dir, i))
+        {
+            sc_id = i;
+            break;
+        }
+    }
+    if ( sc_id == 0xFFFFFFFF )
+    {
+        PR_ERR("no empty SC entry!");
+        return RTK_PHYLIB_ERR_EXCEEDS_CAPACITY;
+    }
+
+    flow_base = PHY_MACSEC_HW_FLOW_ID(sc_id);
+
+    rtk_phylib_memset(&flow, 0, sizeof(phy_macsec_flow_action_t));
+    rtk_phylib_memset(&match, 0, sizeof(phy_macsec_flow_match_t));
+    rtk_phylib_memset(&hwsa, 0, sizeof(phy_macsec_sa_params_t));
+
+    cs = (dir == RTK_MACSEC_DIR_EGRESS) ? (pSc->tx.cipher_suite) : (pSc->rx.cipher_suite);
+    switch (cs)
+    {
+        case RTK_MACSEC_CIPHER_GCM_ASE_128:
+            hwsa.flags = 0;
+            hwsa.key_bytes = 16;
+            if(dir == RTK_MACSEC_DIR_INGRESS && pSc->rx.replay_window > 0xFFFFFFFF)
+            {
+                PR_ERR("PN replay_window %u out of range 0~%u", pSc->rx.replay_window, (0xFFFFFFFF));
+                return RTK_PHYLIB_ERR_INPUT;
+            }
+            break;
+        case RTK_MACSEC_CIPHER_GCM_ASE_256:
+            hwsa.flags = 0;
+            hwsa.key_bytes = 32;
+            if(dir == RTK_MACSEC_DIR_INGRESS && pSc->rx.replay_window > 0xFFFFFFFF)
+            {
+                PR_ERR("PN replay_window %u out of range 0~%u", pSc->rx.replay_window, (0xFFFFFFFF));
+                return RTK_PHYLIB_ERR_INPUT;
+            }
+            break;
+        case RTK_MACSEC_CIPHER_GCM_ASE_XPN_128:
+            hwsa.flags = RTK_PHY_MACSEC_SA_FLAG_XPN;
+            hwsa.key_bytes = 16;
+            if(dir == RTK_MACSEC_DIR_INGRESS && pSc->rx.replay_window > 0x40000000)
+            {
+                PR_ERR("XPN replay_window %u out of range 0~%u", pSc->rx.replay_window, (0x40000000));
+                return RTK_PHYLIB_ERR_INPUT;
+            }
+            break;
+        case RTK_MACSEC_CIPHER_GCM_ASE_XPN_256:
+            hwsa.flags = RTK_PHY_MACSEC_SA_FLAG_XPN;
+            hwsa.key_bytes = 32;
+            if(dir == RTK_MACSEC_DIR_INGRESS && pSc->rx.replay_window > 0x40000000)
+            {
+                PR_ERR("XPN replay_window %u out of range 0~%u", pSc->rx.replay_window, (0x40000000));
+                return RTK_PHYLIB_ERR_INPUT;
+            }
+            break;
+        default:
+            return RTK_PHYLIB_ERR_INPUT;
+    }
+
+    if (dir == RTK_MACSEC_DIR_EGRESS)
+    {
+        PR_DBG("[%s]SCI = 0x%02X%02X%02X%02X%02X%02X%02X%02X\n", __FUNCTION__,
+                 pSc->tx.sci[0], pSc->tx.sci[1], pSc->tx.sci[2], pSc->tx.sci[3],
+                 pSc->tx.sci[4], pSc->tx.sci[5], pSc->tx.sci[6], pSc->tx.sci[7]);
+        PR_DBG("[%s]pf %u/is %u/es %u/scb %u/cp %u\n", __FUNCTION__,
+                 pSc->tx.protect_frame, pSc->tx.include_sci, pSc->tx.use_es,  pSc->tx.use_scb, pSc->tx.conf_protect);
+
+        /* match rule */
+        match.fUntagged = 1;
+        match.fControlPacket = 0;
+        switch (pSc->tx.flow_match)
+        {
+            case RTK_MACSEC_MATCH_NON_CTRL:
+                match.matchMask = MACSEC_SA_MATCH_MASK_CTRL_PKT;
+                break;
+
+            case RTK_MACSEC_MATCH_MAC_DA:
+                rtk_phylib_memcpy(match.mac_da, pSc->tx.mac_da.octet, 6 * sizeof(uint8));
+                match.matchMask = (MACSEC_SA_MATCH_MASK_MAC_DA_FULL
+                    | MACSEC_SA_MATCH_MASK_CTRL_PKT);
+                break;
+
+            default:
+                return RTK_PHYLIB_ERR_INPUT;
+        }
+        match.flow_index = flow_base;
+        RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_match_rule_set(phydev, dir, flow_base, &match));
+        MACSEC_SC_MATCH(macsec_db, dir, sc_id) = pSc->tx.flow_match;
+
+        /* flow ctrl */
+        flow.flow_type = RTK_MACSEC_FLOW_EGRESS;
+        flow.dest_port = RTK_MACSEC_PORT_COMMON;
+        flow.sa_index = PHY_MACSEC_HW_SA_ID(sc_id, 0);
+        flow.params.egress.protect_frame = pSc->tx.protect_frame;
+        flow.params.egress.sa_in_use = 0;
+        flow.params.egress.include_sci = pSc->tx.include_sci;
+        flow.params.egress.use_es = pSc->tx.use_es;
+        flow.params.egress.use_scb = pSc->tx.use_scb;
+        flow.params.egress.confidentiality_offset = 0;
+        flow.params.egress.conf_protect = pSc->tx.conf_protect;
+
+        RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_set(phydev, dir, flow_base, &flow));
+
+        /* TC */
+        hwsa.direction = dir;
+        hwsa.flow_index = flow_base;
+        hwsa.sa_expired_irq = 1;
+        hwsa.update_en = 1;
+        hwsa.next_sa_valid = 0;
+        rtk_phylib_memcpy(hwsa.sci, pSc->tx.sci, 8 * sizeof(uint8));
+        for (an = 0; an < 4; an++)
+        {
+            hwsa.an = an;
+            hwsa.next_sa_index = PHY_MACSEC_HW_SA_ID(sc_id, ((an + 1) % 4));
+            RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_set(phydev, dir, PHY_MACSEC_HW_SA_ID(sc_id, an), &hwsa));
+        }
+    }
+    else /* RTK_MACSEC_DIR_INGRESS */
+    {
+        PR_DBG("[%s]SCI = 0x%02X%02X%02X%02X%02X%02X%02X%02X\n", __FUNCTION__,
+                 pSc->rx.sci[0], pSc->rx.sci[1], pSc->rx.sci[2], pSc->rx.sci[3],
+                 pSc->rx.sci[4], pSc->rx.sci[5], pSc->rx.sci[6], pSc->rx.sci[7]);
+        PR_DBG("[%s]rp %u/rw %u\n", __FUNCTION__,
+                 pSc->rx.replay_protect, pSc->rx.replay_window);
+        /* match rule */
+        match.fTagged = 1;
+        match.fControlPacket = 0;
+        rtk_phylib_memcpy(match.sci, pSc->rx.sci, 8 * sizeof(uint8));
+        switch (pSc->rx.flow_match)
+        {
+            case RTK_MACSEC_MATCH_SCI:
+                tci_an = 0x20;
+                match.matchMask = (MACSEC_SA_MATCH_MASK_MACSEC_SCI
+                    | MACSEC_SA_MATCH_MASK_MACSEC_TCI_AN_SC
+                    | MACSEC_SA_MATCH_MASK_CTRL_PKT);
+                break;
+
+            case RTK_MACSEC_MATCH_MAC_SA:
+                tci_an = 0x0;
+                rtk_phylib_memcpy(match.mac_sa, pSc->rx.mac_sa.octet, 6 * sizeof(uint8));
+                match.matchMask = (MACSEC_SA_MATCH_MASK_MAC_SA_FULL
+                    | MACSEC_SA_MATCH_MASK_MACSEC_TCI_AN_SC
+                    | MACSEC_SA_MATCH_MASK_CTRL_PKT);
+                break;
+
+            default:
+                return RTK_PHYLIB_ERR_INPUT;
+        }
+        for (an = 0; an < 4; an++)
+        {
+            match.macsec_TCI_AN = an | tci_an;
+            match.flow_index = flow_base + an;
+            RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_match_rule_set(phydev, dir, (flow_base + an), &match));
+        }
+        MACSEC_SC_MATCH(macsec_db, dir, sc_id) = pSc->rx.flow_match;
+
+        /* flow ctrl */
+        flow.flow_type = RTK_MACSEC_FLOW_INGRESS;
+        flow.dest_port = RTK_MACSEC_PORT_CONTROLLED;
+
+        flow.params.ingress.replay_protect = pSc->rx.replay_protect;
+        flow.params.ingress.sa_in_use = 0;
+        flow.params.ingress.validate_frames = pSc->rx.validate_frames;
+        flow.params.ingress.confidentiality_offset = 0;
+
+        for (an = 0; an < 4; an++)
+        {
+            flow.sa_index = PHY_MACSEC_HW_SA_ID(sc_id, an);
+            RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_set(phydev, dir, (flow_base + an), &flow));
+        }
+
+        /* TC */
+        hwsa.direction = dir;
+        hwsa.replay_window = pSc->rx.replay_window;
+        rtk_phylib_memcpy(hwsa.sci, pSc->rx.sci, 8 * sizeof(uint8));
+        for (an = 0; an < 4; an++)
+        {
+            RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_set(phydev, dir, PHY_MACSEC_HW_SA_ID(sc_id, an), &hwsa));
+        }
+    }
+
+    RTK_PHYLIB_BYTE_ARRAY_TO_VAL(macsec_db->sci[dir][sc_id], hwsa.sci, 0, 8);
+
+    MACSEC_SC_CS(macsec_db, dir, sc_id) = cs;
+    MACSEC_SC_SET_USED(macsec_db, dir, sc_id);
+    PR_DBG("[%s]%s SC:%u \n", __FUNCTION__, (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX", sc_id);
+
+    if (dir == RTK_MACSEC_DIR_EGRESS)
+    {
+        RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_enable_set(phydev, dir, flow_base, active));
+    }
+    else /* RTK_MACSEC_DIR_INGRESS */
+    {
+        for (an = 0; an < 4; an++)
+        {
+            sa_id = PHY_MACSEC_HW_SA_ID(sc_id, an);
+            if(MACSEC_SA_IS_USED(macsec_db, dir, sa_id))
+            {
+                RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_enable_set(phydev, dir, flow_base + an, active));
+            }
+        }
+    }
+
+    *pSc_id = sc_id;
+    return ret;
+}
+
+int32 rtk_phylib_macsec_sc_update(rtk_phydev *phydev, rtk_macsec_dir_t dir,
+    rtk_macsec_sc_t *pSc, uint32 *pSc_id, uint8 active)
+{
+    struct rtk_phy_priv *priv = phydev->priv;
+    rtk_macsec_port_info_t *macsec_db = priv->macsec;
+
+    int32  ret = 0;
+    uint8 an = 0, tci_an = 0;
+    uint32 sc_id = 0xFFFFFFFF;
+    uint32 flow_base = 0;
+    rtk_macsec_cipher_t cs = RTK_MACSEC_CIPHER_GCM_ASE_128;
+    phy_macsec_flow_action_t flow[4];
+    phy_macsec_flow_match_t match[4];
+    phy_macsec_sa_params_t hwsa[4];
+    uint64 sci_val = 0;
+    rtk_macsec_sc_status_t sc_status;
+    uint32 hwsa_flags = 0, hwsa_key_bytes = 0;
+
+    rtk_phylib_memset(&flow, 0, sizeof(flow));
+    rtk_phylib_memset(&match, 0, sizeof(match));
+    rtk_phylib_memset(&hwsa, 0, sizeof(hwsa));
+
+    if (pSc == NULL || pSc_id == NULL)
+        return RTK_PHYLIB_ERR_INPUT;
+
+    if (RTK_MACSEC_DIR_INGRESS == dir)
+        RTK_PHYLIB_BYTE_ARRAY_TO_VAL(sci_val, pSc->rx.sci, 0, 8);
+    else
+        RTK_PHYLIB_BYTE_ARRAY_TO_VAL(sci_val, pSc->tx.sci, 0, 8);
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sci_to_scid(phydev, dir, sci_val, &sc_id));
+    PR_DBG("[%s]update %s SC %u\n", __FUNCTION__, (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX", sc_id);
+    flow_base = PHY_MACSEC_HW_FLOW_ID(sc_id);
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sc_status_get(phydev, dir, sc_id, &sc_status));
+    if (dir == RTK_MACSEC_DIR_EGRESS)
+    {
+        if (sc_status.tx.hw_sc_flow_status == 1) /* Disable active flow before update */
+        {
+            RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_enable_set(phydev, dir, flow_base, DISABLED));
+        }
+
+        RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_get(phydev, dir, flow_base, &flow[0]));
+        RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_match_rule_get(phydev, dir, flow_base, &match[0]));
+        for (an = 0; an < 4; an++)
+        {
+            RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_get(phydev, dir, PHY_MACSEC_HW_SA_ID(sc_id, an), &hwsa[an]));
+        }
+    }
+    else /* RTK_MACSEC_DIR_INGRESS */
+    {
+        for (an = 0; an < 4; an++)
+        {
+            if (sc_status.rx.hw_sc_flow_status[an] == 1) /* Disable active flow before update */
+            {
+                RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_enable_set(phydev, dir, flow_base + an, DISABLED));
+            }
+
+            RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_get(phydev, dir, flow_base + an, &flow[0]));
+            RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_match_rule_get(phydev, dir, flow_base + an, &match[0]));
+            RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_get(phydev, dir, PHY_MACSEC_HW_SA_ID(sc_id, an), &hwsa[an]));
+        }
+    }
+
+    cs = (dir == RTK_MACSEC_DIR_EGRESS) ? (pSc->tx.cipher_suite) : (pSc->rx.cipher_suite);
+    switch (cs)
+    {
+        case RTK_MACSEC_CIPHER_GCM_ASE_128:
+            hwsa_flags = 0;
+            hwsa_key_bytes = 16;
+            if(dir == RTK_MACSEC_DIR_INGRESS && pSc->rx.replay_window > 0xFFFFFFFF)
+            {
+                PR_ERR("PN replay_window %u out of range 0~%u", pSc->rx.replay_window, (0xFFFFFFFF));
+                return RTK_PHYLIB_ERR_INPUT;
+            }
+            break;
+        case RTK_MACSEC_CIPHER_GCM_ASE_256:
+            hwsa_flags = 0;
+            hwsa_key_bytes = 32;
+            if(dir == RTK_MACSEC_DIR_INGRESS && pSc->rx.replay_window > 0xFFFFFFFF)
+            {
+                PR_ERR("PN replay_window %u out of range 0~%u", pSc->rx.replay_window, (0xFFFFFFFF));
+                return RTK_PHYLIB_ERR_INPUT;
+            }
+            break;
+        case RTK_MACSEC_CIPHER_GCM_ASE_XPN_128:
+            hwsa_flags = RTK_PHY_MACSEC_SA_FLAG_XPN;
+            hwsa_key_bytes = 16;
+            if(dir == RTK_MACSEC_DIR_INGRESS && pSc->rx.replay_window > 0x40000000)
+            {
+                PR_ERR("XPN replay_window %u out of range 0~%u", pSc->rx.replay_window, (0x40000000));
+                return RTK_PHYLIB_ERR_INPUT;
+            }
+            break;
+        case RTK_MACSEC_CIPHER_GCM_ASE_XPN_256:
+            hwsa_flags = RTK_PHY_MACSEC_SA_FLAG_XPN;
+            hwsa_key_bytes = 32;
+            if(dir == RTK_MACSEC_DIR_INGRESS && pSc->rx.replay_window > 0x40000000)
+            {
+                PR_ERR("XPN replay_window %u out of range 0~%u", pSc->rx.replay_window, (0x40000000));
+                return RTK_PHYLIB_ERR_INPUT;
+            }
+            break;
+        default:
+            return RTK_PHYLIB_ERR_INPUT;
+    }
+
+    if (dir == RTK_MACSEC_DIR_EGRESS)
+    {
+        PR_DBG("[%s]SCI = 0x%02X%02X%02X%02X%02X%02X%02X%02X\n", __FUNCTION__,
+                 pSc->tx.sci[0], pSc->tx.sci[1], pSc->tx.sci[2], pSc->tx.sci[3],
+                 pSc->tx.sci[4], pSc->tx.sci[5], pSc->tx.sci[6], pSc->tx.sci[7]);
+        PR_DBG("[%s]pf %u/is %u/es %u/scb %u/cp %u\n", __FUNCTION__,
+                 pSc->tx.protect_frame, pSc->tx.include_sci, pSc->tx.use_es,  pSc->tx.use_scb, pSc->tx.conf_protect);
+
+        /* match rule */
+        switch (pSc->tx.flow_match)
+        {
+            case RTK_MACSEC_MATCH_NON_CTRL:
+                match[0].matchMask = MACSEC_SA_MATCH_MASK_CTRL_PKT;
+                break;
+
+            case RTK_MACSEC_MATCH_MAC_DA:
+                rtk_phylib_memcpy(match[0].mac_da, pSc->tx.mac_da.octet, 6 * sizeof(uint8));
+                match[0].matchMask = (MACSEC_SA_MATCH_MASK_MAC_DA_FULL
+                    | MACSEC_SA_MATCH_MASK_CTRL_PKT);
+                break;
+
+            default:
+                return RTK_PHYLIB_ERR_INPUT;
+        }
+        match[0].flow_index = flow_base;
+        RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_match_rule_set(phydev, dir, flow_base, &match[0]));
+        MACSEC_SC_MATCH(macsec_db, dir, sc_id) = pSc->tx.flow_match;
+
+        /* flow ctrl */
+        flow[0].params.egress.protect_frame = pSc->tx.protect_frame;
+        flow[0].params.egress.include_sci = pSc->tx.include_sci;
+        flow[0].params.egress.use_es = pSc->tx.use_es;
+        flow[0].params.egress.use_scb = pSc->tx.use_scb;
+        flow[0].params.egress.conf_protect = pSc->tx.conf_protect;
+
+        RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_set(phydev, dir, flow_base, &flow[0]));
+
+        /* TC */
+        for (an = 0; an < 4; an++)
+        {
+            rtk_phylib_memcpy(hwsa[an].sci, pSc->tx.sci, 8 * sizeof(uint8));
+            hwsa[an].flags = hwsa_flags;
+            hwsa[an].key_bytes = hwsa_key_bytes;
+            RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_set(phydev, dir, PHY_MACSEC_HW_SA_ID(sc_id, an), &hwsa[an]));
+
+        }
+    }
+    else /* RTK_MACSEC_DIR_INGRESS */
+    {
+        PR_DBG("[%s]SCI = 0x%02X%02X%02X%02X%02X%02X%02X%02X\n", __FUNCTION__,
+                 pSc->rx.sci[0], pSc->rx.sci[1], pSc->rx.sci[2], pSc->rx.sci[3],
+                 pSc->rx.sci[4], pSc->rx.sci[5], pSc->rx.sci[6], pSc->rx.sci[7]);
+        PR_DBG("[%s]rp %u/rw %u\n", __FUNCTION__,
+                 pSc->rx.replay_protect, pSc->rx.replay_window);
+        MACSEC_SC_MATCH(macsec_db, dir, sc_id) = pSc->rx.flow_match;
+        for (an = 0; an < 4; an++)
+        {
+            /* match rule */
+            rtk_phylib_memcpy(match[an].sci, pSc->rx.sci, 8 * sizeof(uint8));
+            switch (pSc->rx.flow_match)
+            {
+                case RTK_MACSEC_MATCH_SCI:
+                    tci_an = 0x20;
+                    match[an].matchMask = (MACSEC_SA_MATCH_MASK_MACSEC_SCI
+                        | MACSEC_SA_MATCH_MASK_MACSEC_TCI_AN_SC
+                        | MACSEC_SA_MATCH_MASK_CTRL_PKT);
+                    break;
+
+                case RTK_MACSEC_MATCH_MAC_SA:
+                    tci_an = 0x0;
+                    rtk_phylib_memcpy(match[an].mac_sa, pSc->rx.mac_sa.octet, 6 * sizeof(uint8));
+                    match[an].matchMask = (MACSEC_SA_MATCH_MASK_MAC_SA_FULL
+                        | MACSEC_SA_MATCH_MASK_MACSEC_TCI_AN_SC
+                        | MACSEC_SA_MATCH_MASK_CTRL_PKT);
+                    break;
+
+                default:
+                    return RTK_PHYLIB_ERR_INPUT;
+            }
+            match[an].macsec_TCI_AN = an | tci_an;
+            match[an].flow_index = flow_base + an;
+            RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_match_rule_set(phydev, dir, (flow_base + an), &match[an]));
+
+
+            /* flow ctrl */
+            flow[an].params.ingress.replay_protect = pSc->rx.replay_protect;
+            flow[an].params.ingress.validate_frames = pSc->rx.validate_frames;
+            flow[an].sa_index = PHY_MACSEC_HW_SA_ID(sc_id, an);
+            RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_set(phydev, dir, (flow_base + an), &flow[an]));
+
+            /* TC */
+            hwsa[an].replay_window = pSc->rx.replay_window;
+            rtk_phylib_memcpy(hwsa[an].sci, pSc->rx.sci, 8 * sizeof(uint8));
+
+            hwsa[an].flags = hwsa_flags;
+            hwsa[an].key_bytes =hwsa_key_bytes;
+
+            RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_set(phydev, dir, PHY_MACSEC_HW_SA_ID(sc_id, an), &hwsa[an]));
+        }
+    }
+    RTK_PHYLIB_BYTE_ARRAY_TO_VAL(macsec_db->sci[dir][sc_id], hwsa[0].sci, 0, 8);
+
+    MACSEC_SC_CS(macsec_db, dir, sc_id) = cs;
+    MACSEC_SC_SET_USED(macsec_db, dir, sc_id);
+    PR_DBG("[%s]%s SC:%u \n", __FUNCTION__,  (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX", sc_id);
+
+    /* Recover active flow after update */
+    if (dir == RTK_MACSEC_DIR_EGRESS)
+    {
+        if (sc_status.tx.hw_sc_flow_status == 1)
+        {
+            RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_enable_set(phydev, dir, flow_base, ENABLED));
+        }
+    }
+    else /* RTK_MACSEC_DIR_INGRESS */
+    {
+        for (an = 0; an < 4; an++)
+        {
+            if (sc_status.rx.hw_sc_flow_status[an] == 1)
+            {
+                RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_enable_set(phydev, dir, flow_base + an, ENABLED));
+            }
+        }
+    }
+
+    *pSc_id = sc_id;
+    return ret;
+}
+
+int32 rtk_phylib_macsec_sc_get(rtk_phydev *phydev, rtk_macsec_dir_t dir,
+    uint32 sc_id, rtk_macsec_sc_t *pSc)
+{
+    struct rtk_phy_priv *priv = phydev->priv;
+    rtk_macsec_port_info_t *macsec_db = priv->macsec;
+
+    int32 ret = 0;
+    uint32 flow_base = 0, sa_base = 0;
+    phy_macsec_flow_action_t flow;
+    phy_macsec_flow_match_t match;
+    phy_macsec_sa_params_t hwsa;
+
+    if (pSc == NULL)
+        return RTK_PHYLIB_ERR_INPUT;
+    if (sc_id >= MACSEC_SC_MAX(macsec_db))
+        return RTK_PHYLIB_ERR_INPUT;
+
+    if (MACSEC_SC_IS_CLEAR(macsec_db, dir, sc_id))
+    {
+        PR_ERR("%s SC %u is not existed!",(RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX",sc_id);
+        return RTK_PHYLIB_ERR_ENTRY_NOTFOUND;
+    }
+    rtk_phylib_memset(pSc, 0, sizeof(rtk_macsec_sc_t));
+
+    flow_base = PHY_MACSEC_HW_FLOW_ID(sc_id);
+    sa_base = PHY_MACSEC_HW_SA_ID(sc_id, 0);
+
+    RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_get(phydev, dir, flow_base, &flow));
+    RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_get(phydev, dir, sa_base, &hwsa));
+
+    if (dir == RTK_MACSEC_DIR_EGRESS)
+    {
+        pSc->tx.cipher_suite = MACSEC_SC_CS(macsec_db, dir, sc_id);
+        pSc->tx.flow_match = MACSEC_SC_MATCH(macsec_db, dir, sc_id);
+        if (RTK_MACSEC_MATCH_MAC_DA == pSc->tx.flow_match)
+        {
+            RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_match_rule_get(phydev, dir, flow_base, &match));
+            rtk_phylib_memcpy(pSc->tx.mac_da.octet, match.mac_da, 6 * sizeof(uint8));
+        }
+
+        pSc->tx.protect_frame = flow.params.egress.protect_frame;
+        pSc->tx.include_sci = flow.params.egress.include_sci;
+        pSc->tx.use_es = flow.params.egress.use_es;
+        pSc->tx.use_scb = flow.params.egress.use_scb;
+        pSc->tx.conf_protect = flow.params.egress.conf_protect;
+
+        rtk_phylib_memcpy(pSc->tx.sci, hwsa.sci, 8 * sizeof(uint8));
+    }
+    else /* RTK_MACSEC_DIR_INGRESS */
+    {
+        pSc->rx.cipher_suite = MACSEC_SC_CS(macsec_db, dir, sc_id);
+        pSc->rx.flow_match = MACSEC_SC_MATCH(macsec_db, dir, sc_id);
+        RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_match_rule_get(phydev, dir, flow_base, &match));
+        if (RTK_MACSEC_MATCH_MAC_SA == pSc->rx.flow_match)
+        {
+            rtk_phylib_memcpy(pSc->rx.mac_sa.octet, match.mac_sa, 6 * sizeof(uint8));
+        }
+        rtk_phylib_memcpy(pSc->rx.sci, match.sci, 8 * sizeof(uint8));
+
+        pSc->rx.replay_protect = flow.params.ingress.replay_protect;
+        pSc->rx.validate_frames = flow.params.ingress.validate_frames;
+
+        pSc->rx.replay_window = hwsa.replay_window;
+    }
+    return ret;
+}
+
+int32 rtk_phylib_macsec_sc_del(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 sc_id)
+{
+    struct rtk_phy_priv *priv = phydev->priv;
+    rtk_macsec_port_info_t *macsec_db = priv->macsec;
+
+    int32 ret = 0;
+    uint8 an = 0;
+    uint32 flow_base = 0, flow_id = 0;
+
+    PR_DBG("[%s]%s SC:%u\n", __FUNCTION__, (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX", sc_id);
+
+    if (sc_id >= MACSEC_SC_MAX(macsec_db))
+        return RTK_PHYLIB_ERR_INPUT;
+
+    if (MACSEC_SC_IS_CLEAR(macsec_db, dir, sc_id))
+        return 0;
+
+    flow_base = PHY_MACSEC_HW_FLOW_ID(sc_id);
+
+    if (dir == RTK_MACSEC_DIR_EGRESS)
+    {
+        flow_id = flow_base;
+
+        RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_enable_set(phydev, dir, flow_id, 0));
+        RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_match_rule_del(phydev, dir, flow_id));
+        RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_del(phydev, dir, flow_id));
+
+        for (an = 0; an < 4; an++)
+        {
+            RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_del(phydev, dir, PHY_MACSEC_HW_SA_ID(sc_id, an)));
+            MACSEC_SA_UNSET_USED(macsec_db, dir, PHY_MACSEC_HW_SA_ID(sc_id, an));
+        }
+    }
+    else /* RTK_MACSEC_DIR_INGRESS */
+    {
+        for (an = 0; an < 4; an++)
+        {
+            flow_id = flow_base + an;
+            RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_enable_set(phydev, dir, flow_id, 0));
+            RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_match_rule_del(phydev, dir, flow_id));
+            RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_del(phydev, dir, flow_id));
+            RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_del(phydev, dir, PHY_MACSEC_HW_SA_ID(sc_id, an)));
+            MACSEC_SA_UNSET_USED(macsec_db, dir, PHY_MACSEC_HW_SA_ID(sc_id, an));
+        }
+    }
+
+    macsec_db->sci[dir][sc_id] = 0;
+    MACSEC_SC_UNSET_USED(macsec_db, dir, sc_id);
+    return ret;
+}
+
+int32 rtk_phylib_macsec_sc_status_get(rtk_phydev *phydev, rtk_macsec_dir_t dir,
+    uint32 sc_id, rtk_macsec_sc_status_t *pSc_status)
+{
+    struct rtk_phy_priv *priv = phydev->priv;
+    rtk_macsec_port_info_t *macsec_db = priv->macsec;
+
+    int32 ret = 0;
+    phy_macsec_flow_action_t flow;
+    uint32 flow_base = 0, flow_id = 0;
+    uint32 flow_reg = 0, flow_data = 0;
+    rtk_enable_t ena = DISABLED;
+    rtk_macsec_an_t an;
+
+    if (pSc_status == NULL)
+        return RTK_PHYLIB_ERR_INPUT;
+    if (sc_id >= MACSEC_SC_MAX(macsec_db))
+        return RTK_PHYLIB_ERR_INPUT;
+    if (MACSEC_SC_IS_CLEAR(macsec_db, dir, sc_id))
+    {
+        PR_ERR("%s SC %u is not existed!", (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX",sc_id);
+        return RTK_PHYLIB_ERR_ENTRY_NOTFOUND;
+    }
+    rtk_phylib_memset(pSc_status, 0, sizeof(rtk_macsec_sc_status_t));
+
+    flow_base = PHY_MACSEC_HW_FLOW_ID(sc_id);
+    RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_get(phydev, dir, flow_base, &flow));
+
+    if (dir == RTK_MACSEC_DIR_EGRESS)
+    {
+        RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_get(phydev, dir, flow_base, &flow));
+        RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_enable_get(phydev, dir, flow_base, &ena));
+        pSc_status->tx.hw_flow_index = flow_base;
+        pSc_status->tx.hw_sa_index = flow.sa_index;
+        pSc_status->tx.sa_inUse = flow.params.egress.sa_in_use;
+        pSc_status->tx.hw_sc_flow_status = (ena == ENABLED) ? 1 : 0;
+        pSc_status->tx.running_an = PHY_MACSEC_HW_SA_TO_AN(flow.sa_index);
+
+        flow_reg = MACSEC_REG_SAM_FLOW_CTRL(flow_base);
+        MACSEC_REG_GET(phydev, dir, flow_reg, &flow_data);
+        pSc_status->tx.hw_flow_data = flow_data;
+    }
+    else /* RTK_MACSEC_DIR_INGRESS */
+    {
+        pSc_status->rx.hw_flow_base = flow_base;
+        for (an = RTK_MACSEC_AN0; an < RTK_MACSEC_AN_MAX; an++)
+        {
+            flow_id = flow_base + an;
+            RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_get(phydev, dir, flow_id, &flow));
+            RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_enable_get(phydev, dir, flow_id, &ena));
+            pSc_status->rx.hw_sa_index[an] = flow.sa_index;
+            pSc_status->rx.sa_inUse[an] = flow.params.ingress.sa_in_use;
+            pSc_status->rx.hw_sc_flow_status[an] = (ena == ENABLED) ? 1 : 0;
+
+            flow_reg = MACSEC_REG_SAM_FLOW_CTRL(flow_id);
+            MACSEC_REG_GET(phydev, dir, flow_reg, &flow_data);
+            pSc_status->rx.hw_flow_data[an] = flow_data;
+        }
+    }
+
+    return ret;
+}
+
+int32 rtk_phylib_macsec_sa_activate(rtk_phydev *phydev, rtk_macsec_dir_t dir,
+    uint32 sc_id, rtk_macsec_an_t an)
+{
+    struct rtk_phy_priv *priv = phydev->priv;
+    rtk_macsec_port_info_t *macsec_db = priv->macsec;
+
+    int32 ret = 0;
+    uint32 sa_id = PHY_MACSEC_HW_SA_ID(sc_id, an);
+    uint32 flow_id = 0;
+    phy_macsec_flow_action_t flow;
+
+    if (sc_id >= MACSEC_SC_MAX(macsec_db))
+        return RTK_PHYLIB_ERR_INPUT;
+    if (sa_id >= MACSEC_SA_MAX(macsec_db))
+        return RTK_PHYLIB_ERR_INPUT;
+    if (MACSEC_SC_IS_CLEAR(macsec_db, dir, sc_id))
+    {
+        PR_ERR("[%s]%s SC %u is not existed!", __FUNCTION__,
+                (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX",sc_id);
+        return RTK_PHYLIB_ERR_ENTRY_NOTFOUND;
+    }
+    if (MACSEC_SA_IS_CLEAR(macsec_db, dir, sa_id))
+    {
+        PR_ERR("[%s]%s SA(SC %u, AN %u) is not existed!", __FUNCTION__,
+                (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX", sc_id, an);
+        return RTK_PHYLIB_ERR_ENTRY_NOTFOUND;
+    }
+
+    PR_DBG("[%s]%s SC:%u AN:%u\n", __FUNCTION__, (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX", sc_id, an);
+    if (dir == RTK_MACSEC_DIR_EGRESS)
+    {
+        flow_id = PHY_MACSEC_HW_FLOW_ID(sc_id);
+        RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_get(phydev, dir, flow_id, &flow));
+        flow.sa_index = sa_id;
+        flow.params.egress.sa_in_use = 1;
+    }
+    else /* RTK_MACSEC_DIR_INGRESS */
+    {
+        flow_id = PHY_MACSEC_HW_FLOW_ID(sc_id) + an;
+        RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_get(phydev, dir, flow_id, &flow));
+        flow.sa_index = sa_id;
+        flow.params.ingress.sa_in_use = 1;
+    }
+
+    RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_set(phydev, dir, flow_id, &flow));
+    RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_enable_set(phydev, dir, flow_id, ENABLED));
+    return ret;
+}
+
+int32 rtk_phylib_macsec_rxsa_disable(rtk_phydev *phydev, uint32 rxsc_id,
+    rtk_macsec_an_t an)
+{
+    struct rtk_phy_priv *priv = phydev->priv;
+    rtk_macsec_port_info_t *macsec_db = priv->macsec;
+
+    int32 ret = 0;
+    rtk_macsec_dir_t dir = RTK_MACSEC_DIR_INGRESS;
+    uint32 sa_id = PHY_MACSEC_HW_SA_ID(rxsc_id, an);
+    uint32 flow_id = PHY_MACSEC_HW_FLOW_ID(rxsc_id) + an;
+    phy_macsec_flow_action_t flow;
+
+    PR_DBG("[%s]SC %u AN %u\n", __FUNCTION__, rxsc_id, an);
+
+    if (rxsc_id >= MACSEC_SC_MAX(macsec_db))
+        return RTK_PHYLIB_ERR_INPUT;
+    if (sa_id >= MACSEC_SA_MAX(macsec_db))
+        return RTK_PHYLIB_ERR_INPUT;
+    if (MACSEC_SC_IS_CLEAR(macsec_db, dir, rxsc_id))
+    {
+        PR_ERR("%s SC %u is not existed!",
+                (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX" ,rxsc_id);
+        return RTK_PHYLIB_ERR_ENTRY_NOTFOUND;
+    }
+    if (MACSEC_SA_IS_CLEAR(macsec_db, dir, sa_id))
+    {
+        PR_ERR("[%s]%s SA(SC %u, AN %u) is not existed!", __FUNCTION__,
+                (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX", rxsc_id, an);
+        return RTK_PHYLIB_ERR_ENTRY_NOTFOUND;
+    }
+
+    RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_get(phydev, dir, flow_id, &flow));
+    flow.params.ingress.sa_in_use = 0;
+    RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_set(phydev, dir, flow_id, &flow));
+
+    return ret;
+}
+
+int32
+rtk_phylib_macsec_txsa_disable(rtk_phydev *phydev, uint32 txsc_id)
+{
+    struct rtk_phy_priv *priv = phydev->priv;
+    rtk_macsec_port_info_t *macsec_db = priv->macsec;
+
+    int32 ret = 0;
+    rtk_macsec_dir_t dir = RTK_MACSEC_DIR_EGRESS;
+    uint32 flow_id = PHY_MACSEC_HW_FLOW_ID(txsc_id);
+    phy_macsec_flow_action_t flow;
+
+    PR_DBG("[%s]SC %u\n", __FUNCTION__, txsc_id);
+
+    if (txsc_id >= MACSEC_SC_MAX(macsec_db))
+        return RTK_PHYLIB_ERR_INPUT;
+
+    if (MACSEC_SC_IS_CLEAR(macsec_db, dir, txsc_id))
+    {
+        PR_ERR("%s SC %u is not existed!",
+                (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX",txsc_id);
+        return RTK_PHYLIB_ERR_ENTRY_NOTFOUND;
+    }
+
+    RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_get(phydev, dir, flow_id, &flow));
+    flow.params.egress.sa_in_use = 0;
+    RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_action_rule_set(phydev, dir, flow_id, &flow));
+
+    return ret;
+}
+
+int32 rtk_phylib_macsec_sa_create(rtk_phydev *phydev, rtk_macsec_dir_t dir,
+    uint32 sc_id, rtk_macsec_an_t an, rtk_macsec_sa_t *pSa)
+{
+    struct rtk_phy_priv *priv = phydev->priv;
+    rtk_macsec_port_info_t *macsec_db = priv->macsec;
+
+    int32 ret = 0;
+    phy_macsec_sa_params_t hwsa;
+    rtk_macsec_cipher_t cs;
+    rtk_macsec_sc_status_t sc_status;
+    uint32 sa_id = PHY_MACSEC_HW_SA_ID(sc_id, an);
+    uint32 post_sa_id = PHY_MACSEC_HW_SA_ID(sc_id, ((an + 3) % 4));
+    uint8 flow_state_recover = 0;
+    uint32 flow_id = PHY_MACSEC_HW_FLOW_ID(sc_id) + an;
+
+    PR_DBG("[%s]%s SC:%u AN:%u\n", __FUNCTION__, (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX", sc_id, an);
+
+    if (pSa == NULL)
+        return RTK_PHYLIB_ERR_INPUT;
+    if (sc_id >= MACSEC_SC_MAX(macsec_db))
+        return RTK_PHYLIB_ERR_INPUT;
+    if (sa_id >= MACSEC_SA_MAX(macsec_db))
+        return RTK_PHYLIB_ERR_INPUT;
+
+    if (MACSEC_SC_IS_CLEAR(macsec_db, dir, sc_id))
+    {
+        PR_ERR("%s SC %u is not existed!",
+                (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX", sc_id);
+        return RTK_PHYLIB_ERR_ENTRY_NOTFOUND;
+    }
+
+    cs = MACSEC_SC_CS(macsec_db, dir, sc_id);
+    PR_DBG("[%s]CS: %u, key_bytes: %u\n", __FUNCTION__, cs, pSa->key_bytes);
+    switch (cs)
+    {
+        case RTK_MACSEC_CIPHER_GCM_ASE_128:
+        case RTK_MACSEC_CIPHER_GCM_ASE_XPN_128:
+            if (pSa->key_bytes != 16)
+            {
+                PR_ERR("Bad key_bytes:%u for AES-128.", pSa->key_bytes);
+                return RTK_PHYLIB_ERR_INPUT;
+            }
+            break;
+
+        case RTK_MACSEC_CIPHER_GCM_ASE_XPN_256:
+        case RTK_MACSEC_CIPHER_GCM_ASE_256:
+            if (pSa->key_bytes != 32)
+            {
+                PR_ERR("Bad key_bytes:%u for AES-256.", pSa->key_bytes);
+                return RTK_PHYLIB_ERR_INPUT;
+            }
+            break;
+        default:
+            return RTK_PHYLIB_ERR_FAILED;
+    }
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sc_status_get(phydev, dir, sc_id, &sc_status));
+    if (dir == RTK_MACSEC_DIR_EGRESS)
+    {
+        /* disable flow for running AN */
+        if ((sc_status.tx.hw_sc_flow_status == 1) && (sc_status.tx.running_an == an))
+        {
+            RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_enable_set(phydev, dir, flow_id, DISABLED));
+            flow_state_recover = 1;
+        }
+
+    }
+    else /* RTK_MACSEC_DIR_INGRESS */
+    {
+        if (sc_status.rx.hw_sc_flow_status[an] == 1)
+        {
+            RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_rxsa_disable(phydev, sc_id, an));
+            flow_state_recover = 1;
+        }
+    }
+
+    RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_get(phydev, dir, sa_id, &hwsa));
+    switch (cs)
+    {
+        case RTK_MACSEC_CIPHER_GCM_ASE_128:
+        case RTK_MACSEC_CIPHER_GCM_ASE_256:
+            hwsa.key_bytes = pSa->key_bytes;
+            hwsa.seq = pSa->pn;
+            hwsa.seq_h = 0;
+            rtk_phylib_memset(hwsa.salt, 0x0, sizeof(uint8) * 12);
+            rtk_phylib_memset(hwsa.ssci, 0x0, sizeof(uint8) * 4);
+            break;
+
+        case RTK_MACSEC_CIPHER_GCM_ASE_XPN_128:
+        case RTK_MACSEC_CIPHER_GCM_ASE_XPN_256:
+            hwsa.flags = RTK_PHY_MACSEC_SA_FLAG_XPN;
+            hwsa.key_bytes = pSa->key_bytes;
+            hwsa.seq = pSa->pn;
+            hwsa.seq_h = pSa->pn_h;
+            rtk_phylib_memcpy(hwsa.salt, pSa->salt, sizeof(uint8) * 12);
+            rtk_phylib_memcpy(hwsa.ssci, pSa->ssci, sizeof(uint8) * 4);
+            break;
+        default:
+            return RTK_PHYLIB_ERR_FAILED;
+    }
+
+    rtk_phylib_memcpy(hwsa.key, pSa->key, sizeof(uint8) * hwsa.key_bytes);
+    RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_set(phydev, dir, sa_id, &hwsa));
+
+    if ((dir == RTK_MACSEC_DIR_EGRESS) && MACSEC_SA_IS_USED(macsec_db, dir, post_sa_id))
+    {
+        RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_get(phydev, dir, post_sa_id, &hwsa));
+        hwsa.next_sa_valid = 1;
+        RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_set(phydev, dir, post_sa_id, &hwsa));
+    }
+
+    if (flow_state_recover == 1)
+    {
+        RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_flow_enable_set(phydev, dir, flow_id, ENABLED));
+    }
+
+    MACSEC_SA_SET_USED(macsec_db, dir, sa_id);
+    return ret;
+}
+
+int32 rtk_phylib_macsec_sa_get(rtk_phydev *phydev, rtk_macsec_dir_t dir,
+    uint32 sc_id, rtk_macsec_an_t an, rtk_macsec_sa_t *pSa)
+{
+    struct rtk_phy_priv *priv = phydev->priv;
+    rtk_macsec_port_info_t *macsec_db = priv->macsec;
+
+    int32 ret = 0;
+    uint32 sa_id = PHY_MACSEC_HW_SA_ID(sc_id, an);
+    phy_macsec_sa_params_t hwsa;
+
+    if (pSa == NULL)
+        return RTK_PHYLIB_ERR_INPUT;
+    if (sc_id >= MACSEC_SC_MAX(macsec_db))
+        return RTK_PHYLIB_ERR_INPUT;
+    if (sa_id >= MACSEC_SA_MAX(macsec_db))
+        return RTK_PHYLIB_ERR_INPUT;
+    if (MACSEC_SC_IS_CLEAR(macsec_db, dir, sc_id))
+    {
+        PR_ERR("%s SC %u is not existed!", (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX",sc_id);
+        return RTK_PHYLIB_ERR_ENTRY_NOTFOUND;
+    }
+    if (MACSEC_SC_IS_CLEAR(macsec_db, dir, sc_id))
+    {
+        PR_ERR("[%s]%s SA(SC %u, AN %u) is not existed!", __FUNCTION__,
+                (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX", sc_id, an);
+        return RTK_PHYLIB_ERR_ENTRY_NOTFOUND;
+    }
+
+    rtk_phylib_memset(pSa, 0x0, sizeof(rtk_macsec_sa_t));
+    RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_get(phydev, dir, sa_id, &hwsa));
+
+    pSa->key_bytes = hwsa.key_bytes;
+    rtk_phylib_memcpy(pSa->key, hwsa.key, sizeof(uint8) * hwsa.key_bytes);
+    if (hwsa.flags & RTK_PHY_MACSEC_SA_FLAG_XPN)
+    {
+        pSa->pn = hwsa.seq;
+        pSa->pn_h = hwsa.seq_h;
+        rtk_phylib_memcpy(pSa->salt, hwsa.salt, sizeof(uint8) * 12);
+        rtk_phylib_memcpy(pSa->ssci, hwsa.ssci, sizeof(uint8) * 4);
+    }
+    else /* PN */
+    {
+        pSa->pn = hwsa.seq;
+    }
+
+    return ret;
+}
+
+int32 rtk_phylib_macsec_sa_del(rtk_phydev *phydev, rtk_macsec_dir_t dir,
+    uint32 sc_id, rtk_macsec_an_t an)
+{
+    struct rtk_phy_priv *priv = phydev->priv;
+    rtk_macsec_port_info_t *macsec_db = priv->macsec;
+
+    int32 ret = 0;
+    uint32 sa_id = PHY_MACSEC_HW_SA_ID(sc_id, an);
+    phy_macsec_sa_params_t hwsa;
+    rtk_macsec_sc_status_t sc_status;
+
+    PR_DBG("[%s]%s SC:%u AN:%u\n", __FUNCTION__, (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX", sc_id, an);
+
+    if (sc_id >= MACSEC_SC_MAX(macsec_db))
+        return RTK_PHYLIB_ERR_INPUT;
+    if (sa_id >= MACSEC_SA_MAX(macsec_db))
+        return RTK_PHYLIB_ERR_INPUT;
+    if (MACSEC_SC_IS_CLEAR(macsec_db, dir, sc_id))
+    {
+        PR_ERR("%s SC %u is not existed!",
+                (RTK_MACSEC_DIR_EGRESS == dir) ? "TX" : "RX",sc_id);
+        return RTK_PHYLIB_ERR_ENTRY_NOTFOUND;
+    }
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_sc_status_get(phydev, dir, sc_id, &sc_status));
+    if (dir == RTK_MACSEC_DIR_EGRESS)
+    {
+        /* disable flow for running AN */
+        if ((sc_status.tx.hw_sc_flow_status == 1) && (sc_status.tx.running_an == an))
+        {
+            RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_txsa_disable(phydev, sc_id));
+        }
+    }
+    else /* RTK_MACSEC_DIR_INGRESS */
+    {
+        if (sc_status.rx.hw_sc_flow_status[an] == 1)
+        {
+            RTK_PHYLIB_ERR_CHK(rtk_phylib_macsec_rxsa_disable(phydev, sc_id, an));
+        }
+    }
+
+    RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_get(phydev, dir, sa_id, &hwsa));
+    rtk_phylib_memset(hwsa.key, 0, sizeof(uint8) * RTK_MACSEC_MAX_KEY_LEN);
+    rtk_phylib_memset(hwsa.salt, 0x0, sizeof(uint8) * 12);
+    rtk_phylib_memset(hwsa.ssci, 0x0, sizeof(uint8) * 4);
+    hwsa.seq = 0;
+    hwsa.seq_h = 0;
+    RTK_PHYLIB_ERR_CHK(__rtk_phylib_macsec_hw_sa_set(phydev, dir, sa_id, &hwsa));
+
+    MACSEC_SA_UNSET_USED(macsec_db, dir, sa_id);
+    return ret;
+}
+
+int32 rtk_phylib_macsec_stat_port_get(rtk_phydev *phydev, rtk_macsec_stat_t stat,
+    uint64 *pCnt)
+{
+    struct rtk_phy_priv *priv = phydev->priv;
+    rtk_macsec_port_info_t *macsec_db = priv->macsec;
+    int32 ret = 0;
+    uint64 cnt_h = 0, cnt_l = 0;
+    uint32 data= 0;
+
+    if (pCnt == NULL)
+        return RTK_PHYLIB_ERR_INPUT;
+
+    switch (stat)
+    {
+        case RTK_MACSEC_STAT_InPktsUntagged:
+            MACSEC_REG_GET(phydev, RTK_MACSEC_DIR_INGRESS, 0xC418, &data);
+            cnt_l = (uint64)data;
+            MACSEC_REG_GET(phydev, RTK_MACSEC_DIR_INGRESS, 0xC41C, &data);
+            cnt_h = (uint64)data;
+            macsec_db->port_stats.InPktsUntagged += ((cnt_h << 32) | cnt_l);
+            *pCnt = macsec_db->port_stats.InPktsUntagged;
+            break;
+        case RTK_MACSEC_STAT_InPktsNoTag:
+            MACSEC_REG_GET(phydev, RTK_MACSEC_DIR_INGRESS, 0xC410, &data);
+            cnt_l = (uint64)data;
+            MACSEC_REG_GET(phydev, RTK_MACSEC_DIR_INGRESS, 0xC414, &data);
+            cnt_h = (uint64)data;
+            macsec_db->port_stats.InPktsNoTag += ((cnt_h << 32) | cnt_l);
+            *pCnt = macsec_db->port_stats.InPktsNoTag;
+            break;
+        case RTK_MACSEC_STAT_InPktsBadTag:
+            MACSEC_REG_GET(phydev, RTK_MACSEC_DIR_INGRESS, 0xC428, &data);
+            cnt_l = (uint64)data;
+            MACSEC_REG_GET(phydev, RTK_MACSEC_DIR_INGRESS, 0xC42C, &data);
+            cnt_h = (uint64)data;
+            macsec_db->port_stats.InPktsBadTag += ((cnt_h << 32) | cnt_l);
+            *pCnt = macsec_db->port_stats.InPktsBadTag;
+            break;
+        case RTK_MACSEC_STAT_InPktsUnknownSCI:
+            MACSEC_REG_GET(phydev, RTK_MACSEC_DIR_INGRESS, 0xC440, &data);
+            cnt_l = (uint64)data;
+            MACSEC_REG_GET(phydev, RTK_MACSEC_DIR_INGRESS, 0xC444, &data);
+            cnt_h = (uint64)data;
+            macsec_db->port_stats.InPktsUnknownSCI += ((cnt_h << 32) | cnt_l);
+            *pCnt = macsec_db->port_stats.InPktsUnknownSCI;
+            break;
+        case RTK_MACSEC_STAT_InPktsNoSCI:
+            MACSEC_REG_GET(phydev, RTK_MACSEC_DIR_INGRESS, 0xC438, &data);
+            cnt_l = (uint64)data;
+            MACSEC_REG_GET(phydev, RTK_MACSEC_DIR_INGRESS, 0xC43C, &data);
+            cnt_h = (uint64)data;
+            macsec_db->port_stats.InPktsNoSCI += ((cnt_h << 32) | cnt_l);
+            *pCnt = macsec_db->port_stats.InPktsNoSCI;
+            break;
+        case RTK_MACSEC_STAT_OutPktsUntagged:
+            MACSEC_REG_GET(phydev, RTK_MACSEC_DIR_EGRESS, 0xC418, &data);
+            cnt_l = (uint64)data;
+            MACSEC_REG_GET(phydev, RTK_MACSEC_DIR_EGRESS, 0xC41C, &data);
+            cnt_h = (uint64)data;
+            macsec_db->port_stats.OutPktsUntagged += ((cnt_h << 32) | cnt_l);
+            *pCnt = macsec_db->port_stats.OutPktsUntagged;
+            break;
+        default:
+            return RTK_PHYLIB_ERR_INPUT;
+    }
+    return ret;
+}
+
+int32 rtk_phylib_macsec_stat_txsa_get(rtk_phydev *phydev, uint32 sc_id,
+    rtk_macsec_an_t an, rtk_macsec_txsa_stat_t stat, uint64 *pCnt)
+{
+    struct rtk_phy_priv *priv = phydev->priv;
+    rtk_macsec_port_info_t *macsec_db = priv->macsec;
+
+    int32 ret = 0;
+    uint64 cnt_h = 0, cnt_l = 0;
+    uint32 data= 0, base = 0;
+    uint32 sa_id = PHY_MACSEC_HW_SA_ID(sc_id, an);
+    rtk_macsec_dir_t dir = RTK_MACSEC_DIR_EGRESS;
+
+    if (pCnt == NULL)
+        return RTK_PHYLIB_ERR_INPUT;
+    if (sc_id >= MACSEC_SC_MAX(macsec_db))
+        return RTK_PHYLIB_ERR_INPUT;
+    if (sa_id >= MACSEC_SA_MAX(macsec_db))
+        return RTK_PHYLIB_ERR_INPUT;
+    if (MACSEC_SC_IS_CLEAR(macsec_db, dir, sc_id))
+    {
+        return RTK_PHYLIB_ERR_ENTRY_NOTFOUND;
+    }
+    if (MACSEC_SA_IS_CLEAR(macsec_db, dir, sa_id))
+    {
+        return RTK_PHYLIB_ERR_ENTRY_NOTFOUND;
+    }
+
+    base = (sa_id * 0x80);
+    switch (stat)
+    {
+        case RTK_MACSEC_TXSA_STAT_OutPktsTooLong:
+            MACSEC_REG_GET(phydev, dir, (base + 0x8018), &data);
+            cnt_l = (uint64)data;
+            MACSEC_REG_GET(phydev, dir, (base + 0x801C), &data);
+            cnt_h = (uint64)data;
+            macsec_db->txsa_stats[sa_id]->OutPktsTooLong += ((cnt_h << 32) | cnt_l);
+            *pCnt = macsec_db->txsa_stats[sa_id]->OutPktsTooLong;
+            break;
+        case RTK_MACSEC_TXSA_STAT_OutOctetsProtectedEncrypted:
+            MACSEC_REG_GET(phydev, dir, (base + 0x8000), &data);
+            cnt_l = (uint64)data;
+            MACSEC_REG_GET(phydev, dir, (base + 0x8004), &data);
+            cnt_h = (uint64)data;
+            macsec_db->txsa_stats[sa_id]->OutOctetsProtectedEncrypted += ((cnt_h << 32) | cnt_l);
+            *pCnt = macsec_db->txsa_stats[sa_id]->OutOctetsProtectedEncrypted;
+            break;
+        case RTK_MACSEC_TXSA_STAT_OutPktsProtectedEncrypted:
+            MACSEC_REG_GET(phydev, dir, (base + 0x8010), &data);
+            cnt_l = (uint64)data;
+            MACSEC_REG_GET(phydev, dir, (base + 0x8014), &data);
+            cnt_h = (uint64)data;
+            macsec_db->txsa_stats[sa_id]->OutPktsProtectedEncrypted += ((cnt_h << 32) | cnt_l);
+            *pCnt = macsec_db->txsa_stats[sa_id]->OutPktsProtectedEncrypted;
+            break;
+
+        default:
+            return RTK_PHYLIB_ERR_INPUT;
+    }
+    return ret;
+}
+
+int32 rtk_phylib_macsec_stat_rxsa_get(rtk_phydev *phydev, uint32 sc_id,
+    rtk_macsec_an_t an, rtk_macsec_rxsa_stat_t stat, uint64 *pCnt)
+{
+    struct rtk_phy_priv *priv = phydev->priv;
+    rtk_macsec_port_info_t *macsec_db = priv->macsec;
+
+    int32 ret = 0;
+    uint64 cnt_h = 0, cnt_l = 0;
+    uint32 data= 0, base = 0;
+    uint32 sa_id = PHY_MACSEC_HW_SA_ID(sc_id, an);
+    rtk_macsec_dir_t dir = RTK_MACSEC_DIR_INGRESS;
+
+    if (pCnt == NULL)
+        return RTK_PHYLIB_ERR_INPUT;
+    if (sc_id >= MACSEC_SC_MAX(macsec_db))
+        return RTK_PHYLIB_ERR_INPUT;
+    if (sa_id >= MACSEC_SA_MAX(macsec_db))
+        return RTK_PHYLIB_ERR_INPUT;
+    if (MACSEC_SC_IS_CLEAR(macsec_db, dir, sc_id))
+    {
+        return RTK_PHYLIB_ERR_ENTRY_NOTFOUND;
+    }
+    if (MACSEC_SA_IS_CLEAR(macsec_db, dir, sa_id))
+    {
+        return RTK_PHYLIB_ERR_ENTRY_NOTFOUND;
+    }
+
+    base = (sa_id * 0x80);
+    switch (stat)
+    {
+        case RTK_MACSEC_RXSA_STAT_InPktsUnusedSA:
+            MACSEC_REG_GET(phydev, dir, (base + 0x8048), &data);
+            cnt_l = (uint64)data;
+            MACSEC_REG_GET(phydev, dir, (base + 0x804C), &data);
+            cnt_h = (uint64)data;
+            macsec_db->rxsa_stats[sa_id]->InPktsUnusedSA += ((cnt_h << 32) | cnt_l);
+            *pCnt = macsec_db->rxsa_stats[sa_id]->InPktsUnusedSA;
+            break;
+        case RTK_MACSEC_RXSA_STAT_InPktsNotUsingSA:
+            MACSEC_REG_GET(phydev, dir, (base + 0x8040), &data);
+            cnt_l = (uint64)data;
+            MACSEC_REG_GET(phydev, dir, (base + 0x8044), &data);
+            cnt_h = (uint64)data;
+            macsec_db->rxsa_stats[sa_id]->InPktsNotUsingSA += ((cnt_h << 32) | cnt_l);
+            *pCnt = macsec_db->rxsa_stats[sa_id]->InPktsNotUsingSA;
+            break;
+        case RTK_MACSEC_RXSA_STAT_InPktsUnchecked:
+            MACSEC_REG_GET(phydev, dir, (base + 0x8010), &data);
+            cnt_l = (uint64)data;
+            MACSEC_REG_GET(phydev, dir, (base + 0x8014), &data);
+            cnt_h = (uint64)data;
+            macsec_db->rxsa_stats[sa_id]->InPktsUnchecked += ((cnt_h << 32) | cnt_l);
+            *pCnt = macsec_db->rxsa_stats[sa_id]->InPktsUnchecked;
+            break;
+        case RTK_MACSEC_RXSA_STAT_InPktsDelayed:
+            MACSEC_REG_GET(phydev, dir, (base + 0x8018), &data);
+            cnt_l = (uint64)data;
+            MACSEC_REG_GET(phydev, dir, (base + 0x801C), &data);
+            cnt_h = (uint64)data;
+            macsec_db->rxsa_stats[sa_id]->InPktsDelayed += ((cnt_h << 32) | cnt_l);
+            *pCnt = macsec_db->rxsa_stats[sa_id]->InPktsDelayed;
+            break;
+        case RTK_MACSEC_RXSA_STAT_InPktsLate:
+            MACSEC_REG_GET(phydev, dir, (base + 0x8020), &data);
+            cnt_l = (uint64)data;
+            MACSEC_REG_GET(phydev, dir, (base + 0x8024), &data);
+            cnt_h = (uint64)data;
+            macsec_db->rxsa_stats[sa_id]->InPktsLate += ((cnt_h << 32) | cnt_l);
+            *pCnt = macsec_db->rxsa_stats[sa_id]->InPktsLate;
+            break;
+        case RTK_MACSEC_RXSA_STAT_InPktsOK:
+            MACSEC_REG_GET(phydev, dir, (base + 0x8028), &data);
+            cnt_l = (uint64)data;
+            MACSEC_REG_GET(phydev, dir, (base + 0x802C), &data);
+            cnt_h = (uint64)data;
+            macsec_db->rxsa_stats[sa_id]->InPktsOK += ((cnt_h << 32) | cnt_l);
+            *pCnt = macsec_db->rxsa_stats[sa_id]->InPktsOK;
+            break;
+        case RTK_MACSEC_RXSA_STAT_InPktsInvalid:
+            MACSEC_REG_GET(phydev, dir, (base + 0x8030), &data);
+            cnt_l = (uint64)data;
+            MACSEC_REG_GET(phydev, dir, (base + 0x8034), &data);
+            cnt_h = (uint64)data;
+            macsec_db->rxsa_stats[sa_id]->InPktsInvalid += ((cnt_h << 32) | cnt_l);
+            *pCnt = macsec_db->rxsa_stats[sa_id]->InPktsInvalid;
+            break;
+        case RTK_MACSEC_RXSA_STAT_InPktsNotValid:
+            MACSEC_REG_GET(phydev, dir, (base + 0x8038), &data);
+            cnt_l = (uint64)data;
+            MACSEC_REG_GET(phydev, dir, (base + 0x803C), &data);
+            cnt_h = (uint64)data;
+            macsec_db->rxsa_stats[sa_id]->InPktsNotValid += ((cnt_h << 32) | cnt_l);
+            *pCnt = macsec_db->rxsa_stats[sa_id]->InPktsNotValid;
+            break;
+        case RTK_MACSEC_RXSA_STAT_InOctetsDecryptedValidated:
+            MACSEC_REG_GET(phydev, dir, (base + 0x8000), &data);
+            cnt_l = (uint64)data;
+            MACSEC_REG_GET(phydev, dir, (base + 0x8004), &data);
+            cnt_h = (uint64)data;
+            macsec_db->rxsa_stats[sa_id]->InOctetsDecryptedValidated += ((cnt_h << 32) | cnt_l);
+            *pCnt = macsec_db->rxsa_stats[sa_id]->InOctetsDecryptedValidated;
+            break;
+        default:
+            return RTK_PHYLIB_ERR_INPUT;
+    }
+    return ret;
+}
+
+/* ------------------------------------------------------------------------------------------------------------------------------- */
+/* id mapping */
+int32 rtk_phylib_macsec_sci_to_scid(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint64 sci, uint32 *sc_id)
+{
+    struct rtk_phy_priv *priv = phydev->priv;
+    rtk_macsec_port_info_t *macsec_db = priv->macsec;
+
+    int32 ret = RTK_PHYLIB_ERR_ENTRY_NOTFOUND;
+    uint32 i = 0;
+    uint64 sci_val = 0;
+
+    PR_DBG("[%s]sci: 0x%016llX\n", __FUNCTION__, sci);
+    for (i = 0; i < MACSEC_SC_MAX(macsec_db); i++)
+    {
+        if(MACSEC_SC_IS_USED(macsec_db, dir, i))
+        {
+            sci_val = macsec_db->sci[dir][i];
+            PR_DBG("[%s]find sci: 0x%016llX, sc id: %u, 0x%016llX\n", __FUNCTION__, sci, i, sci_val);
+            if (sci_val == sci)
+            {
+                *sc_id = i;
+                return 0;
+            }
+        }
+    }
+    return ret;
+}
+
diff --git a/sources/rtk-gp3000/src/hal/phy/rtk_phylib_macsec.h b/sources/rtk-gp3000/src/hal/phy/rtk_phylib_macsec.h
new file mode 100644
index 00000000..103c695a
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/rtk_phylib_macsec.h
@@ -0,0 +1,329 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
+ */
+
+#ifndef __RTK_PHYLIB_MACSEC_H
+#define __RTK_PHYLIB_MACSEC_H
+
+#if defined(RTK_PHYDRV_IN_LINUX)
+  #include "type.h"
+  #include "rtk_phylib_def.h"
+#endif
+
+#define PHY_MACSEC_DEV_EGRESS   0
+#define PHY_MACSEC_DEV_INGRESS  1
+
+#define MACSEC_REG_OFFS               4
+
+#define PHY_MACSEC_HW_SA_ID(sc_id, an)       (sc_id * 4 + an)
+#define PHY_MACSEC_HW_FLOW_ID(sc_id)         (sc_id * 4)
+#define PHY_MACSEC_HW_SA_TO_AN(sa_id)        (sa_id % 4)
+
+#define PHY_MACSEC_MAX_SA_EN_SIZE     24 //32-bit words
+#define PHY_MACSEC_MAX_SA_IN_SIZE     20
+#define PHY_MACSEC_MAX_SA_SIZE        PHY_MACSEC_MAX_SA_EN_SIZE
+
+#define MACSEC_XFORM_REC_BASE         (0x0000)
+#define MACSEC_XFORM_REC_SIZE(dir)   ((RTK_MACSEC_DIR_EGRESS == dir) ? PHY_MACSEC_MAX_SA_EN_SIZE : PHY_MACSEC_MAX_SA_IN_SIZE )
+
+#define MACSEC_REG_XFORM_REC(n, dir)        (MACSEC_XFORM_REC_BASE + MACSEC_XFORM_REC_SIZE(dir) * \
+                                             MACSEC_REG_OFFS * (n % 128))
+#define MACSEC_REG_XFORM_REC_OFFS(n, dir, off) (MACSEC_REG_XFORM_REC(n, dir) + off * MACSEC_REG_OFFS)
+
+
+#define MACSEC_REG_SAM_MAC_SA_MATCH_LO(n) (0x4000 + 16 * MACSEC_REG_OFFS * (n % 128))
+#define MACSEC_REG_SAM_MAC_SA_MATCH_HI(n) (0x4004 + 16 * MACSEC_REG_OFFS * (n % 128))
+#define MACSEC_REG_SAM_MAC_DA_MATCH_LO(n) (0x4008 + 16 * MACSEC_REG_OFFS * (n % 128))
+#define MACSEC_REG_SAM_MAC_DA_MATCH_HI(n) (0x400C + 16 * MACSEC_REG_OFFS * (n % 128))
+
+#define MACSEC_REG_SAM_MISC_MATCH(n)      (0x4010 + 16 * MACSEC_REG_OFFS * (n % 128))
+#define MACSEC_REG_SAM_SCI_MATCH_LO(n)    (0x4014 + 16 * MACSEC_REG_OFFS * (n % 128))
+#define MACSEC_REG_SAM_SCI_MATCH_HI(n)    (0x4018 + 16 * MACSEC_REG_OFFS * (n % 128))
+#define MACSEC_REG_SAM_MASK(n)            (0x401C + 16 * MACSEC_REG_OFFS * (n % 128))
+#define MACSEC_REG_SAM_EXT_MATCH(n)       (0x4020 + 16 * MACSEC_REG_OFFS * (n % 128))
+
+#define MACSEC_REG_SAM_ENTRY_ENABLE(n)    (0x6000 + (n * MACSEC_REG_OFFS))
+#define MACSEC_REG_SAM_ENTRY_TOGGLE(n)    (0x6040 + (n * MACSEC_REG_OFFS))
+#define MACSEC_REG_SAM_ENTRY_SET(n)       (0x6080 + (n * MACSEC_REG_OFFS))
+#define MACSEC_REG_SAM_ENTRY_CLEAR(n)     (0x60C0 + (n * MACSEC_REG_OFFS))
+#define MACSEC_REG_SAM_ENTRY_ENABLE_CTRL  (0x6100)
+#define MACSEC_REG_SAM_IN_FLIGHT          (0x6104)
+
+#define MACSEC_REG_SAM_FLOW_CTRL(n)   (0x7000 + MACSEC_REG_OFFS * (n % 128))
+
+
+#define MACSEC_REG_SAM_IN_FLIGHT      (0x6104)
+#define MACSEC_REG_COUNT_CTRL         (0xC810)
+#define MACSEC_REG_IG_CC_CONTROL      (0xE840)
+#define MACSEC_REG_COUNT_SECFAIL1     (0xF124)
+#define MACSEC_REG_CTX_CTRL           (0xF408)
+#define MACSEC_REG_CTX_UPD_CTRL       (0xF430)
+#define MACSEC_REG_SAM_CP_TAG         (0x7900)
+#define MACSEC_REG_SAM_NM_PARAMS      (0x7940)
+#define MACSEC_REG_SAM_NM_FLOW_NCP        (0x7944)
+#define MACSEC_REG_SAM_NM_FLOW_CP         (0x7948)
+
+#define MACSEC_REG_MISC_CONTROL       (0x797C)
+
+// Mask last byte received of MAC source address
+#define MACSEC_SA_MATCH_MASK_MAC_SA_0         BIT_0
+#define MACSEC_SA_MATCH_MASK_MAC_SA_1         BIT_1
+#define MACSEC_SA_MATCH_MASK_MAC_SA_2         BIT_2
+#define MACSEC_SA_MATCH_MASK_MAC_SA_3         BIT_3
+#define MACSEC_SA_MATCH_MASK_MAC_SA_4         BIT_4
+// Mask first byte received of MAC source address
+#define MACSEC_SA_MATCH_MASK_MAC_SA_5         BIT_5
+
+#define MACSEC_SA_MATCH_MASK_MAC_SA_FULL      (BIT_0 | BIT_1 | BIT_2 | BIT_3 | BIT_4 | BIT_5)
+
+// Mask last byte received of MAC destination address
+#define MACSEC_SA_MATCH_MASK_MAC_DA_0         BIT_6
+#define MACSEC_SA_MATCH_MASK_MAC_DA_1         BIT_7
+#define MACSEC_SA_MATCH_MASK_MAC_DA_2         BIT_8
+#define MACSEC_SA_MATCH_MASK_MAC_DA_3         BIT_9
+#define MACSEC_SA_MATCH_MASK_MAC_DA_4         BIT_10
+// Mask first byte received of MAC destination address
+#define MACSEC_SA_MATCH_MASK_MAC_DA_5         BIT_11
+
+#define MACSEC_SA_MATCH_MASK_MAC_DA_FULL      (BIT_6 | BIT_7 | BIT_8 | BIT_9 | BIT_10 | BIT_11)
+
+#define MACSEC_SA_MATCH_MASK_MAC_ETYPE        BIT_12
+#define MACSEC_SA_MATCH_MASK_VLAN_VALID       BIT_13
+#define MACSEC_SA_MATCH_MASK_QINQ_FOUND       BIT_14
+#define MACSEC_SA_MATCH_MASK_STAG_VALID       BIT_15
+#define MACSEC_SA_MATCH_MASK_QTAG_VALID       BIT_16
+#define MACSEC_SA_MATCH_MASK_VLAN_UP          BIT_17
+#define MACSEC_SA_MATCH_MASK_VLAN_ID          BIT_18
+#define MACSEC_SA_MATCH_MASK_SRC_PORT         BIT_19
+#define MACSEC_SA_MATCH_MASK_CTRL_PKT         BIT_20
+
+// For ingress only
+#define MACSEC_SA_MATCH_MASK_MACSEC_SCI       BIT_23
+#define MACSEC_SA_MATCH_MASK_MACSEC_TCI_AN_SC (BIT_24 | BIT_25 | BIT_29)
+
+#define MACSEC_SAB_CW0_MACSEC_EG32 0x9241e066
+#define MACSEC_SAB_CW0_MACSEC_IG32 0xd241e06f
+#define MACSEC_SAB_CW0_MACSEC_EG64 0xa241e066
+#define MACSEC_SAB_CW0_MACSEC_IG64 0xe241a0ef
+#define MACSEC_SAB_CW0_AES128      0x000a0000
+#define MACSEC_SAB_CW0_AES256      0x000e0000
+
+
+#define RTK_MACSEC_PORT_COMMON          0
+#define RTK_MACSEC_PORT_RESERVED        1
+#define RTK_MACSEC_PORT_CONTROLLED      2
+#define RTK_MACSEC_PORT_UNCONTROLLED    3
+
+
+
+typedef struct phy_macsec_flow_action_e_s
+{
+    // 1 - enable frame protection,
+    // 0 - bypass frame through device
+    uint8 protect_frame;
+
+    // 1 - SA is in use, packets classified for it can be transformed
+    // 0 - SA not in use, packets classified for it can not be transformed
+    uint8 sa_in_use;
+
+    // 1 - inserts explicit SCI in the packet,
+    // 0 - use implicit SCI (not transferred)
+    uint8 include_sci;
+
+    // 1 - enable ES bit in the generated SecTAG
+    // 0 - disable ES bit in the generated SecTAG
+    uint8 use_es;
+
+    // 1 - enable SCB bit in the generated SecTAG
+    // 0 - disable SCB bit in the generated SecTAG
+    uint8 use_scb;
+
+    // Number of VLAN tags to bypass for egress processing.
+    // Valid values: 0, 1 and 2.
+    // This feature is only available on HW4.1 and possibly later versions.
+    uint8 tag_bypass_size;
+
+    // 1 - Does not update sa_in_use flag
+    // 0 - Update sa_in_use flag
+    uint8 sa_index_update_by_hw;
+
+    // The number of bytes (in the range of 0-127) that are authenticated but
+    // not encrypted following the SecTAG in the encrypted packet. Values
+    // 65-127 are reserved in HW < 4.0 and should not be used there.
+    uint8 confidentiality_offset;
+
+    // 1 - enable confidentiality protection
+    // 0 - disable confidentiality protection
+    uint8 conf_protect;
+
+} phy_macsec_flow_action_e_t;
+
+typedef struct phy_macsec_flow_action_i_s
+{
+    // 1 - enable replay protection
+    // 0 - disable replay protection
+    uint8 replay_protect;
+
+    // true - SA is in use, packets classified for it can be transformed
+    // false - SA not in use, packets classified for it can not be transformed
+    uint8 sa_in_use;
+
+    // MACsec frame validation level
+    rtk_macsec_validate_t validate_frames;
+
+    // The number of bytes (in the range of 0-127) that are authenticated but
+    // not encrypted following the SecTAG in the encrypted packet.
+    uint8 confidentiality_offset;
+
+} phy_macsec_flow_action_i_t;
+
+typedef struct phy_macsec_flow_action_bd_s
+{
+    // 1 - enable statistics counting for the associated SA
+    // 0 - disable statistics counting for the associated SA
+    uint8 sa_in_use;
+} phy_macsec_flow_action_bd_t;
+
+typedef struct phy_macsec_flow_action_s
+{
+    uint32 sa_index;
+
+    rtk_macsec_flow_type_t flow_type;
+    union
+    {
+        phy_macsec_flow_action_e_t egress;
+        phy_macsec_flow_action_i_t ingress;
+        phy_macsec_flow_action_bd_t bypass_drop;
+    } params;
+
+    uint8 dest_port;
+
+} phy_macsec_flow_action_t;
+
+typedef struct
+{
+    // index for flow control rule entry
+    uint32 flow_index;
+
+    // Packet field values to match
+
+    // MAC source address
+    uint8 mac_sa[6];
+
+    // MAC destination address
+    uint8 mac_da[6];
+
+    // EtherType
+    uint16 etherType;
+
+    // SCI, for ingress only
+    uint8 sci[8];
+
+    // Parsed VLAN ID compare value
+    uint16 vlan_id;
+
+    // Parsed VLAN valid flag compare value
+    uint8 fVLANValid;
+
+    // Parsed QinQ found flag compare value
+    uint8 fQinQFound;
+
+    // Parsed STAG valid flag compare value
+    uint8 fSTagValid;
+
+    // Parsed QTAG valid flag compare value
+    uint8 fQTagFound;
+
+    // Parsed VLAN User Priority compare value
+    uint8 vlanUserPriority;
+
+    // Packet is a control packet (as pre-decoded) compare value
+    uint8 fControlPacket;
+
+    // true - allow packets without a MACsec tag to match
+    uint8 fUntagged;
+
+    // true - allow packets with a standard and valid MACsec tag to match
+    uint8 fTagged;
+
+    // true - allow packets with an invalid MACsec tag to match
+    uint8 fBadTag;
+
+    // true - allow packets with a MACsec tag indicating KaY handling
+    // to be done to match
+    uint8 fKayTag;
+
+    // Source port compare value
+    uint8 sourcePort;
+
+    // Priority of this entry for determining the actual transform used
+    // on a match when multiple entries match, 0 = lowest, 15 = highest.
+    // In case of identical priorities, the lowest numbered entry takes
+    // precedence.
+    uint8 matchPriority;
+
+    // MACsec TCI/AN byte compare value, bits are individually masked for
+    // comparing. The TCI bits are in bits [7:2] while the AN bits reside
+    // in bits [1:0]. the macsec_TCI_AN field should only be set to
+    // non-zero for an actual MACsec packet.
+    uint8 macsec_TCI_AN;
+
+    // Match mask for the SA flow rules, see MACSEC_SA_MATCH_MASK_*
+    uint32 matchMask;
+
+    // Parsed inner VLAN ID compare value
+    uint16 vlanIdInner;
+
+    // Parsed inner VLAN UP compare value
+    uint8 vlanUpInner;
+
+} phy_macsec_flow_match_t;
+
+typedef struct {
+    uint8 key_offs;
+    uint8 hkey_offs;
+    uint8 seq_offs;
+    uint8 mask_offs;
+    uint8 ctx_salt_offs;
+    uint8 iv_offs;
+    uint8 upd_ctrl_offs;
+} phy_macsec_sa_offset_t;
+
+#define RTK_PHY_MACSEC_SA_FLAG_XPN    0x00000001U    //Extended Packet Numbering
+
+typedef struct
+{
+    uint32 context_id;  //keep 0 for create
+    rtk_macsec_dir_t direction;
+    uint32 flow_index; //the flow entry index apply to this SA
+    uint32 flags;  // a bitmap of RTK_PHY_MACSEC_SA_FLAG_*
+
+    uint8 an;      // 2-bit AN inserted in SecTAG (egress).
+    uint8 sci[8];  // 8-byte SCI.([0:5] = MAC address, [6:7] = port index)
+
+    uint8 key[RTK_MACSEC_MAX_KEY_LEN];  // MACsec Key.
+    uint32 key_bytes; // Size of the MACsec key in bytes (16 for AES128, 32 for AES256).
+
+    uint8 salt[12];  // 12-byte salt (64-bit sequence numbers).
+    uint8 ssci[4];  // 4-byte SSCI value (64-bit sequence numbers).
+
+    uint32 seq; // sequence number.
+    uint32 seq_h; // High part of sequence number (64-bit sequence numbers)
+    uint32 replay_window; // Size of the replay window, 0 for strict ordering (ingress).
+
+    /* update ctrl */
+    uint32 next_sa_index; // SA index of the next chained SA (egress).
+    uint8 sa_expired_irq; // 1 if SA expired IRQ is to be generated.
+    uint8 next_sa_valid; // SA Index field is a valid SA.
+    uint8 update_en;  // Set to true if the SA must be updated.
+} phy_macsec_sa_params_t;
+
+typedef void (*phy_macsec_aes_cb)(
+        const uint8 * const In_p,
+        uint8 * const Out_p,
+        const uint8 * const Key_p,
+        const unsigned int KeyByteCount);
+
+#endif /* __RTK_PHYLIB_MACSEC_H */
diff --git a/sources/rtk-gp3000/src/hal/phy/rtk_phylib_rtl8224.c b/sources/rtk-gp3000/src/hal/phy/rtk_phylib_rtl8224.c
new file mode 100644
index 00000000..8c5192da
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/rtk_phylib_rtl8224.c
@@ -0,0 +1,896 @@
+/*
+ * Copyright (C) 2022 Realtek Semiconductor Corp.
+ * All Rights Reserved.
+ *
+ * This program is the proprietary software of Realtek Semiconductor
+ * Corporation and/or its licensors, and only be used, duplicated,
+ * modified or distributed under the authorized license from Realtek.
+ *
+ * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER
+ * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED.
+ *
+ * $Revision:  $
+ * $Date:  $
+ *
+ * Purpose : PHY 8224 Driver APIs.
+ *
+ * Feature : PHY 8224 Driver APIs
+ *
+ */
+
+/*
+ * Include Files
+ */
+#include "rtk_phylib.h"
+#include "rtk_phy.h"
+#include "rtk_phylib_rtl8224.h"
+#include "phy_rtl8224_patch.h"
+#include "error.h"
+#include "rtk_osal.h"
+
+/*
+ * Symbol Definition
+ */
+#define RTL8224_SWREG_ADDR(_addr)            ((_addr) & (0xffff))
+
+rtk_port_t _phy_8224_base_port_get(uint32 unit, rtk_port_t port)
+{
+    struct rtl8224_priv_info *priv = (struct rtl8224_priv_info *)port->priv;
+
+    return priv->basePort;
+}
+
+/*
+ * Function Declaration
+ */
+uint32
+_phy_8224_mask(uint8 msb, uint8 lsb)
+{
+    uint32  val = 0;
+    uint8   i = 0;
+
+    for (i = lsb; i <= msb; i++)
+    {
+        val |= (1 << i);
+    }
+    return val;
+}
+
+int32
+_phy_8224_mask_get(uint8 msb, uint8 lsb, uint32 *mask)
+{
+    if ((msb > 31) || (lsb > 31) || (msb < lsb))
+    {
+        return RT_ERR_FAILED;
+    }
+    *mask = _phy_8224_mask(msb, lsb);
+
+    return RT_ERR_OK;
+}
+
+static int32 _phy_8224_intReg_get(uint32 unit, rtk_port_t port, uint32 reg_addr, uint8 msb, uint8 lsb, uint32 *pData)
+{
+    int32           ret = RT_ERR_OK;
+    rtk_port_t      base_port = 0;
+    uint32          addr;
+    uint32          l_data = 0;
+    uint32          h_data = 0;
+    uint32          reg_data = 0;
+    uint32          mask = 0;
+
+    if ((msb > 31) || (lsb > 31) || (msb < lsb))
+    {
+        return RT_ERR_FAILED;
+    }
+
+    base_port = _phy_8224_base_port_get(unit, port);
+
+    /* Reg [15:0]*/
+    addr = RTL8224_SWREG_ADDR(reg_addr);
+    ret = phy_common_general_reg_mmd_get(unit, base_port, PHY_MMD_VEND1, addr, &l_data);
+    if(ret != RT_ERR_OK)
+        return ret;
+
+    /* Reg [31:16]*/
+    ret = phy_common_general_reg_mmd_get(unit, base_port, PHY_MMD_VEND1, (addr+1), &h_data);
+    if(ret != RT_ERR_OK)
+        return ret;
+
+    ret = _phy_8224_mask_get(msb, lsb, &mask);
+    if(ret != RT_ERR_OK)
+        return ret;
+
+    reg_data = ((h_data << 16) | (l_data));
+    *pData = (((reg_data) & (mask)) >> lsb);
+
+    return ret;
+}
+
+static int32 _phy_8224_intReg_set(uint32 unit, rtk_port_t port, uint32 reg_addr, uint8 msb, uint8 lsb, uint32 data)
+{
+    int32           ret = RT_ERR_OK;
+    rtk_port_t      base_port = 0;
+    uint32          addr;
+    uint32          l_data = 0;
+    uint32          h_data = 0;
+    uint32          reg_data = 0;
+    uint32          mask = 0;
+
+    if ((msb > 31) || (lsb > 31) || (msb < lsb))
+    {
+        return RT_ERR_FAILED;
+    }
+
+    base_port = _phy_8224_base_port_get(unit, port);
+
+    /* Reg [15:0]*/
+    addr = RTL8224_SWREG_ADDR(reg_addr);
+    ret = phy_common_general_reg_mmd_get(unit, base_port, PHY_MMD_VEND1, addr, &l_data);
+    if(ret != RT_ERR_OK)
+        return ret;
+
+    /* Reg [31:16]*/
+    ret = phy_common_general_reg_mmd_get(unit, base_port, PHY_MMD_VEND1, (addr+1), &h_data);
+    if(ret != RT_ERR_OK)
+        return ret;
+
+    ret = _phy_8224_mask_get(msb, lsb, &mask);
+    if(ret != RT_ERR_OK)
+        return ret;
+
+    reg_data = ((h_data << 16) | (l_data));
+    reg_data &= ~(mask);
+    reg_data |= (((data) << lsb) & mask);
+
+    l_data = (reg_data & 0xffff);
+    h_data = ((reg_data >> 16)& 0xffff);
+
+    ret = phy_common_general_reg_mmd_set(unit, base_port, PHY_MMD_VEND1, addr, l_data);
+    if(ret != RT_ERR_OK)
+        return ret;
+
+    ret = phy_common_general_reg_mmd_set(unit, base_port, PHY_MMD_VEND1, (addr+1), h_data);
+    if(ret != RT_ERR_OK)
+        return ret;
+
+    return RT_ERR_OK;
+}
+
+static int32 _phy_8224_intRegBit_set(uint32 unit, rtk_port_t port, uint32 reg_addr, uint8 bit, uint32 data)
+{
+    if (bit > 31)
+    {
+        return RT_ERR_FAILED;
+    }
+    return _phy_8224_intReg_set(unit, port, reg_addr, bit, bit, data);
+}
+
+static int32 _phy_8224_sram_get(uint32 unit, rtk_port_t port, uint32 sramAddr, uint32 *pData)
+{
+    int32           ret;
+
+    ret = phy_common_general_reg_mmd_set(unit, port, PHY_MMD_VEND2, 0xa436, sramAddr);
+    if(ret != RT_ERR_OK)
+        return ret;
+
+    ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_VEND2, 0xa438, pData);
+    if(ret != RT_ERR_OK)
+        return ret;
+
+    return ret;
+}
+
+int32
+_phy_8224_interrupt_init(uint32 unit, rtk_port_t port)
+{
+    int32           ret = RT_ERR_OK;
+    uint32          phyData;
+    rtk_port_t      base_port;
+    uint8           port_offset;
+
+    base_port = _phy_8224_base_port_get(unit, port);
+    if ((ret = phy_8224_get_port_offset(base_port, port, &port_offset)) != RT_ERR_OK)
+        return ret;
+
+    /* Clean GPHY Interrupt Pending bits*/
+    /* Read and Clear*/
+    if ((ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_VEND2, 0xA43A, &phyData)) != RT_ERR_OK)
+        return ret;
+    /* Clean ISR_EXT_GPHY */
+    /* Write 1 to clear */
+    if ((ret = _phy_8224_intRegBit_set(unit, port, RTL8224_ISR_EXT_GPHY, port_offset, 1)) != RT_ERR_OK)
+       return ret;
+
+    if (port == base_port)
+    {
+        /* Disable IMR_EXT_GPHY */
+        if ((ret = _phy_8224_intReg_set(unit, port, RTL8224_IMR_EXT_GPHY, RTL8224_IMR_EXT_GPHY_3_0_MSB, RTL8224_IMR_EXT_GPHY_3_0_OFFSET, 0)) != RT_ERR_OK)
+            return ret;
+
+        /* Disable Thermal/PTP 1588/MACsec IMR */
+        if ((ret = _phy_8224_intReg_set(unit, port, 0xbb005f78, RTL8224_INTER_REG_MSB, RTL8224_INTER_REG_LSB, 0)) != RT_ERR_OK)
+            return ret;
+        if ((ret = _phy_8224_intReg_set(unit, port, 0xbb005f68, RTL8224_INTER_REG_MSB, RTL8224_INTER_REG_LSB, 0)) != RT_ERR_OK)
+            return ret;
+
+        /* Disable RLFD Interrupt pin output */
+        if ((ret = _phy_8224_intReg_set(unit, port, 0xbb005f64, RTL8224_INTER_REG_MSB, RTL8224_INTER_REG_LSB, 0)) != RT_ERR_OK)
+            return ret;
+        if ((ret = _phy_8224_intReg_set(unit, port, 0xbb005f40, RTL8224_INTER_REG_MSB, RTL8224_INTER_REG_LSB, 0)) != RT_ERR_OK)
+            return ret;
+        /* Enable RLFD IMR */
+        if ((ret = _phy_8224_intReg_set(unit, port, RTL8224_RLFD_CTRL_REG, RTL8224_RLFD_SEL_OFFSET, RTL8224_RLFD_EN_OFFSET, 1)) != RT_ERR_OK)
+            return ret;
+        if ((ret = _phy_8224_intReg_set(unit, port, RTL8224_CFG_PHY_POLL_CMD1_REG, RTL8224_CMD_RD_EN_3_0_MSB, RTL8224_CMD_RD_EN_3_0_LSB, 7)) != RT_ERR_OK)
+            return ret;
+
+        /* Enable Global IMR for interrupt GPIO output, high level trigger*/
+        if ((ret = _phy_8224_intReg_set(unit, port, RTL8224_ISR_SW_INT_MODE, RTL8224_SWITCH_IE_OFFSET, RTL8224_SWITCH_IE_OFFSET, 1)) != RT_ERR_OK)
+            return ret;
+        if ((ret = _phy_8224_intReg_set(unit, port, RTL8224_ISR_SW_INT_MODE, RTL8224_SWITCH_INT_MODE_MSB, RTL8224_SWITCH_INT_MODE_OFFSET, PHY_8224_INT_MODE_LOW_LEVEL)) != RT_ERR_OK)
+            return ret;
+    }
+
+    /*All ports*/
+    if ((ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_VEND2, 0xA442, &phyData)) != RT_ERR_OK)
+        return ret;
+    phyData |= (0x1 << PHY_8224_RLFD_ENABLE_OFFSET);
+    if ((ret = phy_common_general_reg_mmd_set(unit, port, PHY_MMD_VEND2, 0xA442, phyData)) != RT_ERR_OK)
+        return ret;
+
+    return ret;
+}
+
+int32
+_phy_8224_rtctChannelLen_get(uint32 unit, rtk_port_t port, uint32 channel, uint32 *pChLen)
+{
+    int32       ret = RT_ERR_OK;
+    uint32      channel_l, channel_h;
+    uint32      cable_len;
+
+    switch (channel)
+    {
+        case 0:
+            if ((ret = _phy_8224_sram_get(unit, port, (0x802c - 0x4), &channel_h)) != RT_ERR_OK)
+                return ret;
+            if ((ret = _phy_8224_sram_get(unit, port, (0x802d - 0x4), &channel_l)) != RT_ERR_OK)
+                return ret;
+            break;
+        case 1:
+            if ((ret = _phy_8224_sram_get(unit, port, (0x8030 - 0x4), &channel_h)) != RT_ERR_OK)
+                return ret;
+            if ((ret = _phy_8224_sram_get(unit, port, (0x8031 - 0x4), &channel_l)) != RT_ERR_OK)
+                return ret;
+            break;
+        case 2:
+            if ((ret = _phy_8224_sram_get(unit, port, (0x8034 - 0x4), &channel_h)) != RT_ERR_OK)
+                return ret;
+            if ((ret = _phy_8224_sram_get(unit, port, (0x8035 - 0x4), &channel_l)) != RT_ERR_OK)
+                return ret;
+            break;
+        case 3:
+            if ((ret = _phy_8224_sram_get(unit, port, (0x8038 - 0x4), &channel_h)) != RT_ERR_OK)
+                return ret;
+            if ((ret = _phy_8224_sram_get(unit, port, (0x8039 - 0x4), &channel_l)) != RT_ERR_OK)
+                return ret;
+            break;
+        default:
+                return RT_ERR_OUT_OF_RANGE;
+            break;
+    }
+
+    cable_len = ((channel_h & 0xff00)+((channel_l >> 8) & 0xff));
+    if (cable_len >= RTL8224_RTCT_LEN_OFFSET)
+        cable_len = cable_len - RTL8224_RTCT_LEN_OFFSET;
+    else
+        cable_len = 0;
+
+    cable_len = (cable_len*10)/RTL8224_RTCT_LEN_CABLE_FACTOR;
+
+    *pChLen = cable_len;
+
+    return ret;
+}
+
+
+int32
+_phy_8224_rtctStatus_convert(uint32 phyData,
+                                uint32 *pShort, uint32 *pOpen,
+                                uint32 *pMismatch, uint32 *pPairBusy)
+{
+    if (phyData & BIT_6)
+    {
+        if (phyData & BIT_5)
+        {
+            /* normal */
+            return RT_ERR_OK;
+        }
+        else if (phyData & BIT_3)
+        {
+            *pOpen = 1;
+        }
+        else if (phyData & BIT_4)
+        {
+            *pShort = 1;
+        }
+        else if (phyData & BIT_0)
+        {
+            *pPairBusy = 1;
+        }
+        else if (phyData & BIT_7) /* Interpair short */
+        {
+            *pShort = 2;
+        }
+    }
+    else
+    {
+        return RT_ERR_PHY_RTCT_NOT_FINISH;
+    }
+    return RT_ERR_OK;
+}
+
+
+int32
+_phy_8224_common_c45_enable_get(uint32 unit, rtk_port_t port, rtk_enable_t *pEnable)
+{
+    int32   ret;
+    uint32  phyData = 0;
+
+    if ((ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_PMAPMD, 0, &phyData)) != RT_ERR_OK)
+        return ret;
+
+    *pEnable = (phyData & BIT_11) ? (DISABLED) : (ENABLED);
+    return ret;
+}
+
+int32
+_phy_8224_common_c45_speedDuplexStatusResReg_get(uint32 unit, rtk_port_t port, rtk_port_speed_t *pSpeed, rtk_port_duplex_t *pDuplex)
+{
+    int32   ret = RT_ERR_FAILED;
+    uint32  phyData, spd;
+
+    *pSpeed = PORT_SPEED_10M;
+    *pDuplex = PORT_HALF_DUPLEX;
+    if ((ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_VEND2, 0xA434, &phyData)) != RT_ERR_OK)
+        return ret;
+
+    /* [10:9,5:4] */
+    spd = ((phyData & (0x3 << 9)) >> (9 - 2)) | ((phyData & (0x3 << 4)) >> 4);
+    switch (spd)
+    {
+        case 0x0:
+          *pSpeed = PORT_SPEED_10M;
+          break;
+        case 0x1:
+          *pSpeed = PORT_SPEED_100M;
+          break;
+        case 0x2:
+          *pSpeed = PORT_SPEED_1000M;
+          break;
+        case 0x3:
+          *pSpeed = PORT_SPEED_500M;
+          break;
+        case 0x4:
+          *pSpeed = PORT_SPEED_10G;
+          break;
+        case 0x5:
+          *pSpeed = PORT_SPEED_2_5G;
+          break;
+        case 0x6:
+          *pSpeed = PORT_SPEED_5G;
+          break;
+        case 0x7:
+          *pSpeed = PORT_SPEED_2_5G_LITE;
+          break;
+        case 0x8:
+          *pSpeed = PORT_SPEED_5G_LITE;
+          break;
+        case 0x9:
+          *pSpeed = PORT_SPEED_10G_LITE;
+          break;
+        default:
+          *pSpeed = PORT_SPEED_10M;
+          break;
+    }
+
+    *pDuplex = (phyData & 0x8)? PORT_FULL_DUPLEX : PORT_HALF_DUPLEX;
+    return RT_ERR_OK;
+}
+
+int32
+_phy_8224_tx_polarity_swap_set(rtk_port_t port, uint32 value)
+{
+    struct rtl8224_priv_info *priv = (struct rtl8224_priv_info *)port->priv;
+    int32           ret = RT_ERR_OK;
+    uint32          phyData, msb_bit, lsb_bit;
+    uint32          unit = 0;
+    rtk_port_t      base_port;
+    uint8           port_offset = 0;
+
+    base_port = priv->basePort;
+    if ((ret = phy_8224_get_port_offset(base_port, port, &port_offset)) != RT_ERR_OK)
+        return ret;
+
+
+    lsb_bit = (port_offset*RTL8224_PHY_TX_POLARITY_SWAP_OFFSET);
+    msb_bit = lsb_bit + (RTL8224_PHY_TX_POLARITY_SWAP_OFFSET - 1);
+    if ((ret = _phy_8224_intReg_get(unit, port, RTL8224_PHY_TX_POLARITY_SWAP, msb_bit, lsb_bit, &phyData)) != RT_ERR_OK)
+        return ret;
+
+    phyData &= (~(BIT_0 | BIT_1 | BIT_2 | BIT_3));
+    phyData |= (value & RTK_PHY_CTRL_MDI_POLARITY_SWAP_CH_A)? (BIT_0) : (0);
+    phyData |= (value & RTK_PHY_CTRL_MDI_POLARITY_SWAP_CH_B)? (BIT_1) : (0);
+    phyData |= (value & RTK_PHY_CTRL_MDI_POLARITY_SWAP_CH_C)? (BIT_2) : (0);
+    phyData |= (value & RTK_PHY_CTRL_MDI_POLARITY_SWAP_CH_D)? (BIT_3) : (0);
+    if ((ret = _phy_8224_intReg_set(unit, port, RTL8224_PHY_TX_POLARITY_SWAP, msb_bit, lsb_bit, phyData)) != RT_ERR_OK)
+        return ret;
+
+    return ret;
+}
+
+
+int32
+_phy_8224_mdi_reverse_set(rtk_port_t port, uint32 value)
+{
+    struct rtl8224_priv_info *priv = (struct rtl8224_priv_info *)port->priv;
+    int32           ret = RT_ERR_OK;
+    uint32          phyData;
+    uint32          unit = 0;
+    rtk_port_t      base_port;
+    uint8           port_offset = 0;
+
+    base_port = priv->basePort;
+    if ((ret = phy_8224_get_port_offset(base_port, port, &port_offset)) != RT_ERR_OK)
+        return ret;
+
+    if ((ret = _phy_8224_intReg_get(unit, port, RTL8224_PHY_MDI_REVERSE, port_offset, port_offset, &phyData)) != RT_ERR_OK)
+        return ret;
+    /* PortOffset 0&1 --> 0: Reverse, 1: Normal */
+    /* PortOffset 2&3 --> 0: Normal,  1: Reverse */
+    if(value != 0) /*Need to reverse*/
+    {
+        switch(port_offset)
+        {
+            case 0:
+            case 1:
+                phyData = 0;
+                break;
+            case 2:
+            case 3:
+                phyData = 1;
+                break;
+            default:
+                return RT_ERR_FAILED;
+        }
+    }else{
+        switch(port_offset)
+        {
+            case 0:
+            case 1:
+        phyData = 1;
+                break;
+            case 2:
+            case 3:
+        phyData = 0;
+                break;
+            default:
+                return RT_ERR_FAILED;
+        }
+    }
+    if ((ret = _phy_8224_intReg_set(unit, port, RTL8224_PHY_MDI_REVERSE, port_offset, port_offset, phyData)) != RT_ERR_OK)
+        return ret;
+
+
+    return ret;
+}
+
+rtk_port_t
+_phy_8224_get_phydevice_by_offset(int32 unit, rtk_port_t baseId, uint8 offset)
+{
+    struct rtl8224_priv_info *priv = (struct rtl8224_priv_info *)baseId->priv;
+
+    if(priv->memberPort[offset] != NULL)
+    {
+        return priv->memberPort[offset];
+    }else{
+        return NULL;
+    }
+}
+
+static int32 _phy_8224_sdsRegField_set(uint32 unit, rtk_port_t port, uint32 sdsPage, uint32 sdsReg, uint8 msb, uint8 lsb, uint32 data)
+{
+    struct rtl8224_priv_info *priv = (struct rtl8224_priv_info *)port->priv;
+    int32           ret;
+    rtk_port_t      base_port;
+    uint32          reg_data = 0;
+    uint32          mask = 0;
+
+    if ((msb > 15) || (lsb > 15) || (msb < lsb))
+    {
+        return RT_ERR_FAILED;
+    }
+
+    base_port = priv->basePort;
+
+    phy_rtl8224_sdsReg_get(unit, base_port, sdsPage, sdsReg, &reg_data);
+
+    ret = _phy_8224_mask_get(msb, lsb, &mask);
+    if(ret != RT_ERR_OK)
+        return ret;
+
+    reg_data &= ~(mask);
+    reg_data |= (((data) << lsb) & mask);
+
+    phy_rtl8224_sdsReg_set(unit, base_port, sdsPage, sdsReg, reg_data);
+
+    return RT_ERR_OK;
+}
+
+int32
+_phy_8224_rtctResult_get(uint32 unit, rtk_port_t port, rtk_rtctResult_t *pRtctResult)
+{
+    int32           ret = RT_ERR_OK;
+    uint32          phyData = 0, speed = 0, duplex = 0;
+    uint32          channel_status = 0;
+    uint32          channel_length;
+
+
+    osal_memset(pRtctResult, 0, sizeof(rtk_rtctResult_t));
+
+    /* Check the port is link up or not?
+     * Due to bit 2 is LL(latching low), need to read twice to get current status
+     */
+    if ((ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_PMAPMD, 0x1, &phyData)) != RT_ERR_OK)
+        return ret;
+    if ((ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_PMAPMD, 0x1, &phyData)) != RT_ERR_OK)
+        return ret;
+
+    _phy_8224_common_c45_speedDuplexStatusResReg_get(unit, port, &speed, &duplex);
+    if (phyData & BIT_2)
+    {
+        if (speed == PORT_SPEED_10M)
+        {
+            return RT_ERR_PORT_NOT_SUPPORTED;
+        }
+        /* If the port link is up,
+         * return cable length from Channel Estimation
+         */
+        osal_memset(pRtctResult, 0, sizeof(rtk_rtctResult_t));
+        if (speed == PORT_SPEED_2_5G) /* 2.5GM */
+        {
+            pRtctResult->linkType = PORT_SPEED_2_5G;
+            /* The channel A length is store in UC 0x8ff5 [15:8]*/
+            if ((ret = phy_common_general_reg_mmd_set(unit, port, PHY_MMD_VEND2, 0xb87c, 0x8ff5)) != RT_ERR_OK)
+                return ret;
+            if ((ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_VEND2, 0xb87e, &phyData)) != RT_ERR_OK)
+                return ret;
+            pRtctResult->un.ge_result.channelALen = ((phyData & 0xFF00) >> 8)*100;
+
+            /* The channel B length is store in UC 0x8ff6 [15:8]*/
+            if ((ret = phy_common_general_reg_mmd_set(unit, port, PHY_MMD_VEND2, 0xb87c, 0x8ff6)) != RT_ERR_OK)
+                return ret;
+            if ((ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_VEND2, 0xb87e, &phyData)) != RT_ERR_OK)
+                return ret;
+            pRtctResult->un.ge_result.channelBLen = ((phyData & 0xFF00) >> 8)*100;
+
+            /* The channel C length is store in UC 0x8ff7 [15:8]*/
+            if ((ret = phy_common_general_reg_mmd_set(unit, port, PHY_MMD_VEND2, 0xb87c, 0x8ff7)) != RT_ERR_OK)
+                return ret;
+            if ((ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_VEND2, 0xb87e, &phyData)) != RT_ERR_OK)
+                return ret;
+            pRtctResult->un.ge_result.channelCLen = ((phyData & 0xFF00) >> 8)*100;
+
+            /* The channel D length is store in UC 0x8ff8 [15:8]*/
+            if ((ret = phy_common_general_reg_mmd_set(unit, port, PHY_MMD_VEND2, 0xb87c, 0x8ff8)) != RT_ERR_OK)
+                return ret;
+            if ((ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_VEND2, 0xb87e, &phyData)) != RT_ERR_OK)
+                return ret;
+            pRtctResult->un.ge_result.channelDLen = ((phyData & 0xFF00) >> 8)*100;
+        }
+        else if (speed == PORT_SPEED_1000M) /* 1000M */
+        {
+            /* The Length is store in [7:0], and the unit is meter*/
+            if ((ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_VEND2, 0xA880, &phyData)) != RT_ERR_OK)
+                return ret;
+            pRtctResult->linkType = PORT_SPEED_1000M;
+            pRtctResult->un.ge_result.channelALen = (phyData & 0x00FF)*100;
+            pRtctResult->un.ge_result.channelBLen = (phyData & 0x00FF)*100;
+            pRtctResult->un.ge_result.channelCLen = (phyData & 0x00FF)*100;
+            pRtctResult->un.ge_result.channelDLen = (phyData & 0x00FF)*100;
+        }
+        else /* 100M */
+        {
+            /* The Length is store in [7:0], and the unit is meter*/
+            if ((ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_VEND2, 0xA880, &phyData)) != RT_ERR_OK)
+                return ret;
+            pRtctResult->linkType = PORT_SPEED_100M;
+            pRtctResult->un.fe_result.rxLen = (phyData & 0x00FF)*100;
+            pRtctResult->un.fe_result.txLen = (phyData & 0x00FF)*100;
+        }
+    }
+    else
+    {
+	    if ((ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_VEND2, 0xA422, &phyData)) != RT_ERR_OK)
+	        return ret;
+
+	    if ((phyData & BIT_15) == 0)
+	        return RT_ERR_PHY_RTCT_NOT_FINISH;
+
+	    pRtctResult->linkType = PORT_SPEED_1000M;
+
+	    if ((ret = _phy_8224_rtctChannelLen_get(unit, port, 0, &channel_length)) != RT_ERR_OK)
+	        return ret;
+	    pRtctResult->un.ge_result.channelALen = (channel_length*100); /* RTCT length unit is cm */
+	    RT_LOG(LOG_DEBUG, (MOD_HAL|MOD_PORT), "%s[CHANNEL A]: Length 0x%d\n", __FUNCTION__, channel_length);
+
+	    if ((ret = _phy_8224_rtctChannelLen_get(unit, port, 1, &channel_length)) != RT_ERR_OK)
+	        return ret;
+	    pRtctResult->un.ge_result.channelBLen = (channel_length*100);  /* RTCT length unit is cm */
+	    RT_LOG(LOG_DEBUG, (MOD_HAL|MOD_PORT), "%s[CHANNEL B]: Length 0x%d\n", __FUNCTION__, channel_length);
+
+	    if ((ret = _phy_8224_rtctChannelLen_get(unit, port, 2, &channel_length)) != RT_ERR_OK)
+	        return ret;
+	    pRtctResult->un.ge_result.channelCLen = (channel_length*100);  /* RTCT length unit is cm */
+	    RT_LOG(LOG_DEBUG, (MOD_HAL|MOD_PORT), "%s[CHANNEL C]: Length 0x%d\n", __FUNCTION__, channel_length);
+
+	    if ((ret = _phy_8224_rtctChannelLen_get(unit, port, 3, &channel_length)) != RT_ERR_OK)
+	        return ret;
+	    pRtctResult->un.ge_result.channelDLen = (channel_length*100);  /* RTCT length unit is cm */
+	    RT_LOG(LOG_DEBUG, (MOD_HAL|MOD_PORT), "%s[CHANNEL D]: Length 0x%d\n", __FUNCTION__, channel_length);
+
+
+
+	    if ((ret = _phy_8224_sram_get(unit, port, 0x8026, &channel_status)) != RT_ERR_OK)
+	        return ret;
+	    if ((ret = _phy_8224_rtctStatus_convert(channel_status,
+	                                            &pRtctResult->un.ge_result.channelAShort,        &pRtctResult->un.ge_result.channelAOpen,
+	                                            &pRtctResult->un.ge_result.channelAMismatch,     &pRtctResult->un.ge_result.channelAPairBusy)) != RT_ERR_OK)
+	        return ret;
+	    RT_LOG(LOG_DEBUG, (MOD_HAL|MOD_PORT), "%s[CHANNEL A]: Status 0x%04X\n", __FUNCTION__, channel_status);
+
+	    if ((ret = _phy_8224_sram_get(unit, port, 0x802A, &channel_status)) != RT_ERR_OK)
+	        return ret;
+	    if ((ret = _phy_8224_rtctStatus_convert(channel_status,
+	                                            &pRtctResult->un.ge_result.channelBShort,        &pRtctResult->un.ge_result.channelBOpen,
+	                                            &pRtctResult->un.ge_result.channelBMismatch,     &pRtctResult->un.ge_result.channelBPairBusy)) != RT_ERR_OK)
+	        return ret;
+	    RT_LOG(LOG_DEBUG, (MOD_HAL|MOD_PORT), "%s[CHANNEL B]: Status 0x%04X\n", __FUNCTION__, channel_status);
+
+	    if ((ret = _phy_8224_sram_get(unit, port, 0x802E, &channel_status)) != RT_ERR_OK)
+	        return ret;
+	    if ((ret = _phy_8224_rtctStatus_convert(channel_status,
+	                                            &pRtctResult->un.ge_result.channelCShort,        &pRtctResult->un.ge_result.channelCOpen,
+	                                            &pRtctResult->un.ge_result.channelCMismatch,     &pRtctResult->un.ge_result.channelCPairBusy)) != RT_ERR_OK)
+	        return ret;
+	    RT_LOG(LOG_DEBUG, (MOD_HAL|MOD_PORT), "%s[CHANNEL C]: Status 0x%04X\n", __FUNCTION__, channel_status);
+
+	    if ((ret = _phy_8224_sram_get(unit, port, 0x8032, &channel_status)) != RT_ERR_OK)
+	        return ret;
+	    if ((ret = _phy_8224_rtctStatus_convert(channel_status,
+	                                            &pRtctResult->un.ge_result.channelDShort,        &pRtctResult->un.ge_result.channelDOpen,
+	                                            &pRtctResult->un.ge_result.channelDMismatch,     &pRtctResult->un.ge_result.channelDPairBusy)) != RT_ERR_OK)
+	        return ret;
+	    RT_LOG(LOG_DEBUG, (MOD_HAL|MOD_PORT), "%s[CHANNEL D]: Status 0x%04X\n", __FUNCTION__, channel_status);
+    }
+    return ret;
+}
+
+int32
+_phy_8224_intr_enable(rtk_port_t port, uint32 enable)
+{
+    int32           ret = RT_ERR_OK;
+    uint32          phyData, bit_idx;
+    rtk_port_t      base_port = 0;
+    uint8           port_offset = 0;
+    uint32          unit = 0;
+
+    base_port = _phy_8224_base_port_get(unit, port);
+    if ((ret = phy_8224_get_port_offset(base_port, port, &port_offset)) != RT_ERR_OK)
+        return ret;
+
+    if (enable == DISABLED)
+        phyData = 0;
+    else
+        phyData = 1;
+
+    bit_idx = (RTL8224_IMR_EXT_GPHY_3_0_OFFSET + port_offset);
+    ret = _phy_8224_intRegBit_set(unit, port, RTL8224_IMR_EXT_GPHY, bit_idx, phyData);
+
+    return ret;
+}
+
+int32
+_phy_8224_intr_read_clear(rtk_port_t port, uint32 *pStatus)
+{
+    int32           ret = RT_ERR_OK;
+    uint32          phyData = 0;
+    rtk_port_t      base_port;
+    uint8           port_offset;
+    uint32          unit = 0;
+
+    base_port = _phy_8224_base_port_get(unit, port);
+    if ((ret = phy_8224_get_port_offset(base_port, port, &port_offset)) != RT_ERR_OK)
+        return ret;
+
+
+    /* Read and Clear */
+    if ((ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_VEND2, 0xA43A, &phyData)) != RT_ERR_OK)
+        return ret;
+
+    /* Clean ISR_EXT_GPHY */
+    /* Write 1 to clear */
+    if ((ret = _phy_8224_intRegBit_set(unit, port, RTL8224_ISR_EXT_GPHY, port_offset, 1)) != RT_ERR_OK)
+       return ret;
+
+    *pStatus = phyData;
+    return ret;
+}
+
+int32
+phy_8224_sdsReg_set(uint32 unit, rtk_port_t port, uint32 sdsPage, uint32 sdsReg, uint32 data)
+{
+    struct rtl8224_priv_info *priv = (struct rtl8224_priv_info *)port->priv;
+    rtk_port_t      base_port;
+
+    base_port = priv->basePort;
+
+    return phy_rtl8224_sdsReg_set(unit, base_port, sdsPage, sdsReg, data);
+}
+
+
+int32
+phy_8224_sdsOpCode_set(uint32 unit, rtk_port_t port, uint32 opCode)
+{
+    struct rtl8224_priv_info *priv = (struct rtl8224_priv_info *)port->priv;
+    rtk_port_t      base_port;
+
+    base_port = priv->basePort;
+
+
+    return _phy_8224_sdsRegField_set(unit, base_port, PHY_8224_NWAY_OPCODE_PAGE, PHY_8224_NWAY_OPCODE_REG, PHY_8224_NWAY_OPCODE_HIGH_BIT, PHY_8224_NWAY_OPCODE_LOW_BIT, opCode);
+}
+
+
+int32
+phy_8224_sdsAmPeriod_set(uint32 unit, rtk_port_t port, uint32 amPeriod)
+{
+    struct rtl8224_priv_info *priv = (struct rtl8224_priv_info *)port->priv;
+    rtk_port_t      base_port;
+
+    base_port = priv->basePort;
+
+
+    return _phy_8224_sdsRegField_set(unit, base_port, PHY_8224_AM_PERIOD_PAGE, PHY_8224_AM_PERIOD_REG, PHY_8224_AM_PERIOD_HIGH_BIT, PHY_8224_AM_PERIOD_LOW_BIT, amPeriod);
+}
+
+int32
+phy_8224_sdsAllAm_set(uint32 unit, rtk_port_t port, uint32 value)
+{
+    struct rtl8224_priv_info *priv = (struct rtl8224_priv_info *)port->priv;
+    rtk_port_t      base_port;
+
+    base_port = priv->basePort;
+
+    /* AM0 */
+    _phy_8224_sdsRegField_set(unit, base_port, PHY_8224_AM_PAGE, PHY_8224_AM_CFG0_REG, PHY_8224_AM0_M0_HIGH_BIT, PHY_8224_AM0_M0_LOW_BIT, value);
+    _phy_8224_sdsRegField_set(unit, base_port, PHY_8224_AM_PAGE, PHY_8224_AM_CFG0_REG, PHY_8224_AM0_M1_HIGH_BIT, PHY_8224_AM0_M1_LOW_BIT, value);
+    _phy_8224_sdsRegField_set(unit, base_port, PHY_8224_AM_PAGE, PHY_8224_AM_CFG1_REG, PHY_8224_AM0_M2_HIGH_BIT, PHY_8224_AM0_M2_LOW_BIT, value);
+    /* AM1 */
+    _phy_8224_sdsRegField_set(unit, base_port, PHY_8224_AM_PAGE, PHY_8224_AM_CFG1_REG, PHY_8224_AM1_M0_HIGH_BIT, PHY_8224_AM1_M0_LOW_BIT, value);
+    _phy_8224_sdsRegField_set(unit, base_port, PHY_8224_AM_PAGE, PHY_8224_AM_CFG2_REG, PHY_8224_AM1_M1_HIGH_BIT, PHY_8224_AM1_M1_LOW_BIT, value);
+    _phy_8224_sdsRegField_set(unit, base_port, PHY_8224_AM_PAGE, PHY_8224_AM_CFG2_REG, PHY_8224_AM1_M2_HIGH_BIT, PHY_8224_AM1_M2_LOW_BIT, value);
+    /* AM2 */
+    _phy_8224_sdsRegField_set(unit, base_port, PHY_8224_AM_PAGE, PHY_8224_AM_CFG3_REG, PHY_8224_AM2_M0_HIGH_BIT, PHY_8224_AM2_M0_LOW_BIT, value);
+    _phy_8224_sdsRegField_set(unit, base_port, PHY_8224_AM_PAGE, PHY_8224_AM_CFG3_REG, PHY_8224_AM2_M1_HIGH_BIT, PHY_8224_AM2_M1_LOW_BIT, value);
+    _phy_8224_sdsRegField_set(unit, base_port, PHY_8224_AM_PAGE, PHY_8224_AM_CFG4_REG, PHY_8224_AM2_M2_HIGH_BIT, PHY_8224_AM2_M2_LOW_BIT, value);
+    /* AM3 */
+    _phy_8224_sdsRegField_set(unit, base_port, PHY_8224_AM_PAGE, PHY_8224_AM_CFG4_REG, PHY_8224_AM3_M0_HIGH_BIT, PHY_8224_AM3_M0_LOW_BIT, value);
+    _phy_8224_sdsRegField_set(unit, base_port, PHY_8224_AM_PAGE, PHY_8224_AM_CFG5_REG, PHY_8224_AM3_M1_HIGH_BIT, PHY_8224_AM3_M1_LOW_BIT, value);
+    _phy_8224_sdsRegField_set(unit, base_port, PHY_8224_AM_PAGE, PHY_8224_AM_CFG5_REG, PHY_8224_AM3_M2_HIGH_BIT, PHY_8224_AM3_M2_LOW_BIT, value);
+
+    return RT_ERR_OK;
+}
+
+int32
+phy_8224_sdsExtra_set(uint32 unit, rtk_port_t port)
+{
+    struct rtl8224_priv_info *priv = (struct rtl8224_priv_info *)port->priv;
+    rtk_port_t      base_port;
+
+    base_port = priv->basePort;
+
+    _phy_8224_sdsRegField_set(unit, base_port, PHY_8224_AM_PERIOD_PAGE, PHY_8224_TGR_PRO_0_REG17, PHY_8224_USXG_V2P1P2_RXOFF_HIGH_BIT, PHY_8224_USXG_V2P1P2_RXOFF_LOW_BIT, 0x1);
+    _phy_8224_sdsRegField_set(unit, base_port, PHY_8224_NWAY_OPCODE_PAGE, PHY_8224_TGR_PRO_1_REG19, PHY_8224_USXG_RXDV_OFF_HIGH_BIT, PHY_8224_USXG_RXDV_OFF_LOW_BIT, 0x1);
+
+    return RT_ERR_OK;
+}
+
+
+/* Function Name:
+ *      phy_8224_chipVer_get
+ * Description:
+ *      Set PHY registers.
+ * Input:
+ *      unit    - unit id
+ *      port    - port id
+ * Output:
+ *      pVer    - chip version
+ * Return:
+ *      RT_ERR_OK     - OK
+ *      RT_ERR_FAILED - Failed
+ * Note:
+ *      NA
+ */
+int32
+phy_8224_chipVer_get(uint32 unit, rtk_port_t port, uint32 *pVer)
+{
+    int32       ret;
+    uint32      regData;
+
+    if ((ret = _phy_8224_intReg_set(unit, port, 0xbb00000c, 19, 16, 0xa)) != RT_ERR_OK)
+        return ret;
+
+    if ((ret = _phy_8224_intReg_get(unit, port, 0xbb00000c, 31, 28, &regData)) != RT_ERR_OK)
+        return ret;
+
+    *pVer = regData;
+
+    if ((ret = _phy_8224_intReg_set(unit, port, 0xbb00000c, 19, 16, 0x0)) != RT_ERR_OK)
+        return ret;
+
+    return RT_ERR_OK;
+}
+
+int32
+phy_8224_linkDownPowerSavingEnable_set(uint32 unit, rtk_port_t port, rtk_enable_t enable)
+{
+    int32 ret = 0;
+    uint32  phyData = 0;
+    if ((ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_VEND2, 0xA430, &phyData)) != RT_ERR_OK)
+        return ret;
+    phyData &= (~BIT_2);
+    phyData |= (enable == DISABLED) ? (0) : (BIT_2);
+    if ((ret = phy_common_general_reg_mmd_set(unit, port, PHY_MMD_VEND2, 0xA430, phyData)) != RT_ERR_OK)
+        return ret;
+    return RT_ERR_OK;
+}
+
+
+int32
+phy_8224_linkDownPowerSavingEnable_get(uint32 unit, rtk_port_t port, rtk_enable_t *pEnable)
+{
+    int32 ret = 0;
+    uint32  phyData = 0;
+
+    if ((ret = phy_common_general_reg_mmd_get(unit, port, PHY_MMD_VEND2, 0xA430, &phyData)) != RT_ERR_OK)
+        return ret;
+    *pEnable = (phyData & BIT_2) ? (ENABLED) : (DISABLED);
+
+    return RT_ERR_OK;
+}
+
+int
+phy_8224_get_port_offset(rtk_port_t baseId, rtk_port_t port, uint8 *offset)
+{
+    *offset = (uint8)((port->mdio.addr) - (baseId->mdio.addr));
+    if(*offset >= RTL8224_PORT_NUM)
+        return -1;
+    else
+        return 0;
+}
+
+int32
+phy_8224_sdsReg_get(uint32 unit, rtk_port_t port, uint32 sdsPage, uint32 sdsReg, uint32 *pData)
+{
+    struct rtl8224_priv_info *priv = (struct rtl8224_priv_info *)port->priv;
+    rtk_port_t      base_port;
+
+    base_port = priv->basePort;
+
+    return phy_rtl8224_sdsReg_get(unit, base_port, sdsPage, sdsReg, pData);
+
+}
+
+
+
+
diff --git a/sources/rtk-gp3000/src/hal/phy/rtk_phylib_rtl8224.h b/sources/rtk-gp3000/src/hal/phy/rtk_phylib_rtl8224.h
new file mode 100644
index 00000000..855973fe
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/rtk_phylib_rtl8224.h
@@ -0,0 +1,231 @@
+/*
+ * Copyright (C) 2022 Realtek Semiconductor Corp.
+ * All Rights Reserved.
+ *
+ * This program is the proprietary software of Realtek Semiconductor
+ * Corporation and/or its licensors, and only be used, duplicated,
+ * modified or distributed under the authorized license from Realtek.
+ *
+ * ANY USE OF THE SOFTWARE OTHER THAN AS AUTHORIZED UNDER
+ * THIS LICENSE OR COPYRIGHT LAW IS PROHIBITED.
+ *
+ * $Revision:  $
+ * $Date:  $
+ *
+ * Purpose : PHY 8224 Driver APIs.
+ *
+ * Feature : PHY 8224 Driver APIs.
+ *
+ */
+#ifndef __HAL_PHY_PHY_RTL8224_H__
+#define __HAL_PHY_PHY_RTL8224_H__
+
+/*
+ * Include Files
+ */
+
+#include "rtk_phylib.h"
+
+/*
+ * Symbol Definition
+ */
+
+/*
+ * Data Declaration
+ */
+//extern rt_phyInfo_t phy_8224_info;
+
+/*
+ * Macro Declaration
+ */
+#define RTL8224_PORT_NUM                            (4)
+#define RTL8224_PER_PORT_MAX_LED                    (4)
+#define RTL8224_LED_PAD_MAX_INDEX                   (29)
+
+
+#define RTL8224_INTER_REG_LSB                       (0)
+#define RTL8224_INTER_REG_MSB                       (31)
+
+#define RTL8224_PHY_MDI_REVERSE                     0xbb000a90
+#define RTL8224_MDI_REVERSE_OFFSET                  (0)
+
+#define RTL8224_PHY_TX_POLARITY_SWAP                0xbb000a94
+#define RTL8224_PHY_TX_POLARITY_SWAP_OFFSET         (4)
+
+#define RTL8224_CFG_PHY_POLL_CMD1_REG               (0xbb000ad8)
+#define RTL8224_CMD_RD_EN_3_0_MSB                   (3)
+#define RTL8224_CMD_RD_EN_3_0_LSB                   (0)
+
+
+/* Internal Register */
+/* Global interrupt control */
+#define PHY_8224_INT_MODE_HIGH_LEVEL                (0)
+#define PHY_8224_INT_MODE_LOW_LEVEL                 (1)
+#define PHY_8224_INT_MODE_POS_EDGE                  (2)
+#define PHY_8224_INT_MODE_NEG_EDGE                  (3)
+
+#define RTL8224_ISR_SW_INT_MODE                     0xbb005f84
+#define RTL8224_SWITCH_IE_OFFSET                    (6)
+#define RTL8224_SWITCH_INT_MODE_OFFSET              (1)
+#define RTL8224_SWITCH_INT_MODE_MSB                 (2)
+
+/* GPHY interrupt control */
+#define RTL8224_IMR_EXT_GPHY                        0xbb005f5c
+#define RTL8224_IMR_EXT_GPHY_3_0_OFFSET             (0)
+#define RTL8224_IMR_EXT_GPHY_3_0_MSB                (3)
+
+#define RTL8224_ISR_EXT_GPHY                        0xbb005fb0
+#define RTL8224_ISR_EXT_GPHY_OFFSET                 (0)
+#define RTL8224_ISR_EXT_GPHY_MSB                    (3)
+
+#define RTL8224_IMR_EXT_WOL                         0xbb005f68
+#define RTL8224_IMR_EXT_PHYWOL_PORT_3_0_OFFSET      (9)
+#define RTL8224_IMR_EXT_PHYWOL_PORT_3_0_MSB         (12)
+
+#define RTL8224_IMR_INT_RLFD                        0xbb005f40
+#define RTL8224_IMR_INT_RLFD_PORT_8_0_OFFSET        (0)
+
+#define RTL8224_IMR_EXT_RLFD                        0xbb005f64
+#define RTL8224_IMR_EXT_RLFD_PORT_8_0_OFFSET        (0)
+#define RTL8224_IMR_EXT_RLFD_PORT_SHIFT             (4)
+
+#define RTL8224_GPHY_INTR_STATUS_REG                (0xbb00a43a)
+#define GPHY_AN_ERROR_BIT                           (0)
+#define GPHY_AN_NEXT_PAGE_RECEIVE_BIT               (2)
+#define GPHY_LINK_CHG_BIT                           (4)
+#define GPHY_ALDPS_STS_CHG_BIT                      (9)
+#define GPHY_FATEL_ERROR_BIT                        (11)
+
+#define RTL8224_ISR_INT_TM_RLFD_REG                 (0xbb005f94)
+#define RTL8224_ISR_INT_RLFD_PORT_8_0_OFFSET        (0)
+#define RTL8224_ISR_INT_RLFD_PORT_8_0_MSB           (8)
+
+#define RTL8224_ISR_EXT_TM_RLFD_REG                 (0xbb005fb8)
+#define RTL8224_ISR_EXT_RLFD_PORT_8_0_OFFSET        (0)
+#define RTL8224_ISR_EXT_RLFD_PORT_8_0_MSB           (8)
+#define RTL8224_ISR_EXT_RLFD_PORT_SHIFT             (4)
+
+#define RTL8224_RLFD_CTRL_REG                       (0xbb006458)
+#define RTL8224_RLFD_SEL_OFFSET                     (10)
+#define RTL8224_RLFD_EN_OFFSET                      (9)
+
+#define PHY_RTL8224_VER_A                           (0)
+#define PHY_RTL8224_VER_B                           (1)
+#define PHY_RTL8224_VER_C                           (2)
+
+#define PHY_8224_NWAY_OPCODE_PAGE                   (0x7)
+#define PHY_8224_NWAY_OPCODE_REG                    (16)
+#define PHY_8224_NWAY_OPCODE_HIGH_BIT               (7)
+#define PHY_8224_NWAY_OPCODE_LOW_BIT                (0)
+
+#define PHY_8224_NWAY_OPCODE_PAGE                   (0x7)
+#define PHY_8224_TGR_PRO_1_REG19                    (19)
+#define PHY_8224_USXG_RXDV_OFF_HIGH_BIT             (12)
+#define PHY_8224_USXG_RXDV_OFF_LOW_BIT              (12)
+
+#define PHY_8224_AM_PERIOD_PAGE                     (0x6)
+#define PHY_8224_TGR_PRO_0_REG17                    (17)
+#define PHY_8224_USXG_V2P1P2_RXOFF_HIGH_BIT         (13)
+#define PHY_8224_USXG_V2P1P2_RXOFF_LOW_BIT          (13)
+
+#define PHY_8224_AM_PERIOD_PAGE                     (0x6)
+#define PHY_8224_AM_PERIOD_REG                      (18)
+#define PHY_8224_AM_PERIOD_HIGH_BIT                 (15)
+#define PHY_8224_AM_PERIOD_LOW_BIT                  (0)
+
+#define PHY_8224_AM_PAGE                            (0x6)
+#define PHY_8224_AM_CFG0_REG                        (19)
+#define PHY_8224_AM0_M0_HIGH_BIT                    (7)
+#define PHY_8224_AM0_M0_LOW_BIT                     (0)
+#define PHY_8224_AM0_M1_HIGH_BIT                    (15)
+#define PHY_8224_AM0_M1_LOW_BIT                     (8)
+
+#define PHY_8224_AM_PAGE                            (0x6)
+#define PHY_8224_AM_CFG1_REG                        (20)
+#define PHY_8224_AM0_M2_HIGH_BIT                    (7)
+#define PHY_8224_AM0_M2_LOW_BIT                     (0)
+#define PHY_8224_AM1_M0_HIGH_BIT                    (15)
+#define PHY_8224_AM1_M0_LOW_BIT                     (8)
+
+#define PHY_8224_AM_PAGE                            (0x6)
+#define PHY_8224_AM_CFG2_REG                        (21)
+#define PHY_8224_AM1_M1_HIGH_BIT                    (7)
+#define PHY_8224_AM1_M1_LOW_BIT                     (0)
+#define PHY_8224_AM1_M2_HIGH_BIT                    (15)
+#define PHY_8224_AM1_M2_LOW_BIT                     (8)
+
+#define PHY_8224_AM_PAGE                            (0x6)
+#define PHY_8224_AM_CFG3_REG                        (22)
+#define PHY_8224_AM2_M0_HIGH_BIT                    (7)
+#define PHY_8224_AM2_M0_LOW_BIT                     (0)
+#define PHY_8224_AM2_M1_HIGH_BIT                    (15)
+#define PHY_8224_AM2_M1_LOW_BIT                     (8)
+
+#define PHY_8224_AM_PAGE                            (0x6)
+#define PHY_8224_AM_CFG4_REG                        (23)
+#define PHY_8224_AM2_M2_HIGH_BIT                    (7)
+#define PHY_8224_AM2_M2_LOW_BIT                     (0)
+#define PHY_8224_AM3_M0_HIGH_BIT                    (15)
+#define PHY_8224_AM3_M0_LOW_BIT                     (8)
+
+#define PHY_8224_AM_PAGE                            (0x6)
+#define PHY_8224_AM_CFG5_REG                        (24)
+#define PHY_8224_AM3_M1_HIGH_BIT                    (7)
+#define PHY_8224_AM3_M1_LOW_BIT                     (0)
+#define PHY_8224_AM3_M2_HIGH_BIT                    (15)
+#define PHY_8224_AM3_M2_LOW_BIT                     (8)
+
+#define PHY_8224_NWAY_AN_PAGE                       (0x7)
+#define PHY_8224_NWAY_AN_REG                        (17)
+#define PHY_8224_QHSG_AN_CH3_EN_BIT                 (3)
+#define PHY_8224_QHSG_AN_CH2_EN_BIT                 (2)
+#define PHY_8224_QHSG_AN_CH1_EN_BIT                 (1)
+#define PHY_8224_QHSG_AN_CH0_EN_BIT                 (0)
+
+#define RTL8224_RTCT_LEN_OFFSET                     (620)
+#define RTL8224_RTCT_LEN_CABLE_FACTOR               (780)
+
+/* tapbin def bitmask */
+#define RTL8224_TAPBIN_DEF_OFFSET                   (8)
+#define RTL8224_TAPBIN_DEF_BITMASK                  (0x00000F00)
+
+#define PHY_8224_RLFD_ENABLE_OFFSET                 (15)
+
+#define INVALID_BASE_PORT_PHY_ADDRESS               (255)
+#define RTL8224_BASE_PORT_OFFSET                    (0)
+#define RTL8224_MDI_PIN_SWAP                        (1)
+#define RTL8224_MDI_PAIR_SWAP                       (0)
+#define RT_ERR_PHY_RTCT_NOT_FINISH                  (-2)
+
+struct rtl8224_priv_info
+{
+    rtk_phylib_phy_t phytype;
+    struct phy_device * basePort;
+    struct phy_device * memberPort[RTL8224_PORT_NUM];
+    int32  is_basePort;
+    int32  port_offset;
+};
+
+
+extern int32 phy_8224_chipVer_get(uint32 unit, rtk_port_t port, uint32 *pVer);
+extern int32 phy_8224_sdsReg_get(uint32 unit, rtk_port_t port, uint32 sdsPage, uint32 sdsReg, uint32 *pData);
+extern int32 phy_8224_sdsReg_set(uint32 unit, rtk_port_t port, uint32 sdsPage, uint32 sdsReg, uint32 data);
+extern int32 phy_8224_sdsOpCode_set(uint32 unit, rtk_port_t port, uint32 opCode);
+extern int32 phy_8224_sdsAmPeriod_set(uint32 unit, rtk_port_t port, uint32 amPeriod);
+extern int32 phy_8224_sdsAllAm_set(uint32 unit, rtk_port_t port, uint32 value);
+extern int32 phy_8224_sdsExtra_set(uint32 unit, rtk_port_t port);
+extern int phy_8224_get_port_offset(rtk_port_t baseId, rtk_port_t port, uint8 *offset);
+extern int32 phy_8224_linkDownPowerSavingEnable_set(uint32 unit, rtk_port_t port, rtk_enable_t enable);
+extern int32 phy_8224_linkDownPowerSavingEnable_get(uint32 unit, rtk_port_t port, rtk_enable_t *pEnable);
+extern rtk_port_t _phy_8224_get_phydevice_by_offset(int32 unit, rtk_port_t baseId, uint8 offset);
+extern int32 _phy_8224_tx_polarity_swap_set(rtk_port_t port, uint32 value);
+extern int32 _phy_8224_mdi_reverse_set(rtk_port_t port, uint32 value);
+extern int32 _phy_8224_common_c45_enable_get(uint32 unit, rtk_port_t port, rtk_enable_t *pEnable);
+extern int32 _phy_8224_common_c45_speedDuplexStatusResReg_get(uint32 unit, rtk_port_t port, rtk_port_speed_t *pSpeed, rtk_port_duplex_t *pDuplex);
+extern int32 _phy_8224_intr_enable(rtk_port_t port, uint32 enable);
+extern int32 _phy_8224_intr_read_clear(rtk_port_t port, uint32 *pStatus);
+extern int32 _phy_8224_interrupt_init(uint32 unit, rtk_port_t port);
+extern int32 _phy_8224_rtctResult_get(uint32 unit, rtk_port_t port, rtk_rtctResult_t *pRtctResult);
+
+
+#endif /* __HAL_PHY_PHY_RTL8224_H__ */
diff --git a/sources/rtk-gp3000/src/hal/phy/rtk_phylib_rtl826xb.c b/sources/rtk-gp3000/src/hal/phy/rtk_phylib_rtl826xb.c
new file mode 100644
index 00000000..7f2b983f
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/rtk_phylib_rtl826xb.c
@@ -0,0 +1,572 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
+ */
+
+#include "rtk_phylib_rtl826xb.h"
+
+/* Indirect Register Access APIs */
+int rtk_phylib_826xb_sds_read(rtk_phydev *phydev, uint32 page, uint32 reg, uint8 msb, uint8 lsb, uint32 *pData)
+{
+    int32  ret = 0;
+    uint32 rData = 0;
+    uint32 op = (page & 0x3f) | ((reg & 0x1f) << 6) | (0x8000);
+    uint32 i = 0;
+    uint32 mask = 0;
+    mask = UINT32_BITS_MASK(msb,lsb);
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 323, 15, 0, op));
+
+    for (i = 0; i < 10; i++)
+    {
+        RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 30, 323, 15, 15, &rData));
+        if (rData == 0)
+        {
+            break;
+        }
+        rtk_phylib_udelay(10);
+    }
+    if (i == 10)
+    {
+        return -1;
+    }
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 30, 322, 15, 0, &rData));
+    *pData = REG32_FIELD_GET(rData, lsb, mask);
+
+    return ret;
+}
+
+int rtk_phylib_826xb_sds_write(rtk_phydev *phydev, uint32 page, uint32 reg, uint8 msb, uint8 lsb, uint32 data)
+{
+    int32  ret = 0;
+    uint32 wData = 0, rData = 0;
+    uint32 op = (page & 0x3f) | ((reg & 0x1f) << 6) | (0x8800);
+    uint32 mask = 0;
+    mask = UINT32_BITS_MASK(msb,lsb);
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_sds_read(phydev, page, reg, 15, 0, &rData));
+
+    wData = REG32_FIELD_SET(rData, data, lsb, mask);
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 321, 15, 0, wData));
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 323, 15, 0, op));
+
+    return ret;
+}
+
+int rtk_phylib_826xb_indirect_read(rtk_phydev *phydev,  uint32 indr_addr, uint32 *pData)
+{
+    int32   ret = 0;
+    uint32  rData;
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xA436, 15, 0, indr_addr));
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 31, 0xA438, 15, 0, &rData));
+    *pData = rData;
+
+    return ret;
+}
+
+int rtk_phylib_826xb_sram_read(rtk_phydev *phydev,  uint32 indr_addr, uint8 msb, uint8 lsb, uint32 *pData)
+{
+    int32  ret = 0;
+    uint32 mask = 0, rData = 0;
+
+    mask = UINT32_BITS_MASK(msb,lsb);
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_indirect_read(phydev, indr_addr, &rData));
+    *pData = REG32_FIELD_GET(rData, lsb, mask);
+    return ret;
+}
+
+/* MACsec */
+int rtk_phylib_826xb_macsec_read(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 reg, uint8 msb, uint8 lsb, uint32 *pData)
+{
+    int32  ret = 0;
+    uint32 data_h = 0, data_l = 0;
+    uint32 rData = 0;
+    uint32 mask = 0;
+    uint32 data_e = 0;
+    WAIT_COMPLETE_VAR();
+
+    mask = UINT32_BITS_MASK(msb,lsb);
+
+    switch(dir)
+    {
+        case RTK_MACSEC_DIR_EGRESS:
+            RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x02FB, 15, 0, reg));
+            RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x02FC, 15, 0, 0x10));
+            WAIT_COMPLETE(10000000)
+            {
+                RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 30, 0x02FC, 15, 0, &data_e));
+                if ((data_e & 0x10) == 0x0)
+                {
+                    #ifdef MACSEC_DBG_PRINT
+                    if (_t_wait != 0)
+                        PR_DBG("[%s-%u] _t_wait: %u\n", __FUNCTION__, dir, _t_wait);
+                    #endif
+                    break;
+                }
+            }
+            if (WAIT_COMPLETE_IS_TIMEOUT())
+            {
+                PR_ERR("[%s-%u] timeout!\n", __FUNCTION__, dir);
+                return RTK_PHYLIB_ERR_TIMEOUT;
+            }
+            RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 30, 0x02F8, 15, 0, &data_h));
+            RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 30, 0x02F9, 15, 0, &data_l));
+            break;
+        case RTK_MACSEC_DIR_INGRESS:
+            RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xA6EA, 1, 1, 0x1));
+            RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x0300, 15, 0, reg));
+            RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x0301, 15, 0, 0x10));
+            WAIT_COMPLETE(10000000)
+            {
+                RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 30, 0x0301, 15, 0, &data_e));
+                if ((data_e & 0x10) == 0x0)
+                {
+                    #ifdef MACSEC_DBG_PRINT
+                    if (_t_wait != 0)
+                        PR_DBG("[%s-%u] _t_wait: %u\n", __FUNCTION__, dir, _t_wait);
+                    #endif
+                    break;
+                }
+            }
+            if (WAIT_COMPLETE_IS_TIMEOUT())
+            {
+                PR_ERR("[%s-%u] timeout!\n", __FUNCTION__, dir);
+                RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xA6EA, 1, 1, 0x0));
+                return RTK_PHYLIB_ERR_TIMEOUT;
+            }
+            RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 30, 0x02FD, 15, 0, &data_h));
+            RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 30, 0x02FE, 15, 0, &data_l));
+            RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xA6EA, 1, 1, 0x0));
+            break;
+        default:
+            return -1;
+    }
+
+    rData = (data_h << 16) + data_l;
+    *pData = REG32_FIELD_GET(rData, lsb, mask);
+    return ret;
+}
+
+int rtk_phylib_826xb_macsec_write(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 reg, uint8 msb, uint8 lsb, uint32 data)
+{
+    int32 ret = 0;
+    uint32 data_l = data & 0xFFFF;
+    uint32 data_h = (data >> 16) & 0xFFFF;
+    uint32 data_e = 0;
+    WAIT_COMPLETE_VAR();
+
+    switch(dir)
+    {
+        case RTK_MACSEC_DIR_EGRESS:
+            RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x02F8 , 15, 0, data_h));
+            RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x02F9 , 15, 0, data_l));
+            RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x02FB , 15, 0, reg));
+            RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x02FC, 15, 0, 0x1));
+            WAIT_COMPLETE(10000000)
+            {
+                RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 30, 0x02FC, 15, 0, &data_e));
+                if ((data_e & 0x1) == 0x0)
+                {
+                    #ifdef MACSEC_DBG_PRINT
+                    if (_t_wait != 0)
+                        PR_DBG("[%s-%u] _t_wait: %u\n", __FUNCTION__, dir, _t_wait);
+                    #endif
+                    break;
+                }
+            }
+            if (WAIT_COMPLETE_IS_TIMEOUT())
+            {
+                PR_ERR("[%s-%u] timeout!\n", __FUNCTION__, dir);
+                return RTK_PHYLIB_ERR_TIMEOUT;
+            }
+            break;
+
+        case RTK_MACSEC_DIR_INGRESS:
+            RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xA6EA, 1, 1, 0x1));
+            RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x02FD, 15, 0, data_h));
+            RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x02FE, 15, 0, data_l));
+            RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x0300, 15, 0, reg));
+            RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x0301, 15, 0, 0x1));
+            WAIT_COMPLETE(10000000)
+            {
+                RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 30, 0x0301, 15, 0, &data_e));
+                if ((data_e & 0x1) == 0x0)
+                {
+                    #ifdef MACSEC_DBG_PRINT
+                    if (_t_wait != 0)
+                        PR_DBG("[%s-%u] _t_wait: %u\n", __FUNCTION__, dir, _t_wait);
+                    #endif
+                    break;
+                }
+            }
+            if (WAIT_COMPLETE_IS_TIMEOUT())
+            {
+                PR_ERR("[%s-%u] timeout!\n", __FUNCTION__, dir);
+                RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xA6EA, 1, 1, 0x0));
+                return RTK_PHYLIB_ERR_TIMEOUT;
+            }
+            RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xA6EA, 1, 1, 0x0));
+            break;
+
+        default:
+            return RTK_PHYLIB_ERR_INPUT;
+    }
+    return ret;
+}
+
+int rtk_phylib_826xb_macsec_init(rtk_phydev *phydev)
+{
+    int32 ret = 0;
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x2e0, 1, 0, 0b11));
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x2d8, 15, 0, 0x5313));
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x2da, 15, 0, 0x0101));
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x2dc, 15, 0, 0x0101));
+
+    //MACSEC_RXSYS_CFG4
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x3c6, 7, 0, 0xa));
+    //MACSEC_TXLINE_CFG4
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x37b, 7, 0, 0x6));
+    //loopback fifo_setting
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x2f7, 15, 0, 0x486c));
+    //RA_setting
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x3f1, 15, 0, 0x72));
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x3f0, 15, 0, 0x0b0b));
+    //RA ifg
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x3ee, 15, 13, 0x2));
+    return ret;
+}
+
+int rtk_phylib_826xb_macsec_bypass_set(rtk_phydev *phydev, uint32 bypass)
+{
+    int32 ret = 0;
+
+    if (bypass != 0)
+    {
+        RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x2d8, 15, 0, 0x5313));
+        RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x3f1, 15, 0, 0x72));
+        RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x3f0, 15, 0, 0x0b0b));
+        RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x398, 2, 0, 0x7));
+    }
+    else
+    {
+        RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x2d8, 15, 0, 0x5111));
+        RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x3f1, 15, 0, 0xe871));
+        RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x3f0, 15, 0, 0x0c0c));
+        RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x398, 2, 0, 0x5));
+    }
+    return ret;
+}
+
+int rtk_phylib_826xb_macsec_bypass_get(rtk_phydev *phydev, uint32 *pBypass)
+{
+    int32 ret = 0;
+    uint32 bypass_rx = 0;
+    uint32 bypass_tx = 0;
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 30, 0x2d8, 9, 9, &bypass_rx));
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 30, 0x2d8, 1, 1, &bypass_tx));
+
+    *pBypass = (bypass_rx == 0 && bypass_tx == 0) ? 0 : 1;
+
+    return ret;
+}
+
+/* RTCT */
+int rtk_phylib_826xb_cable_test_start(rtk_phydev *phydev)
+{
+    int32  ret = 0;
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xa4a0, 10, 10, 1));
+    rtk_phylib_mdelay(1000);
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xa422, 15, 0, 0xF2));
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xa422, 0, 0, 1));
+
+    return 0;
+}
+
+int rtk_phylib_826xb_cable_test_finished_get(rtk_phydev *phydev, uint32 *finished)
+{
+    int32  ret = 0;
+    uint32 rData = 0;
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 31, 0xA422, 15, 15, &rData));
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xa4a0, 10, 10, 0));
+    *finished = rData;
+
+    return 0;
+}
+
+int rtk_phylib_826xb_cable_test_result_get(rtk_phydev *phydev, uint32 pair, rtk_rtct_channel_result_t *result)
+{
+    int32  ret = 0;
+    uint32 cable_factor = 7820;
+    uint32 cable_offset = 585;
+    uint32 indr_add_ss = 0x8027 + (pair * 0x4);
+    uint32 indr_add_lh = 0x8028 + (pair * 0x4);
+    uint32 indr_add_ll = 0x8029 + (pair * 0x4);
+    uint32 rtct_status = 0;
+    uint32 rtct_len_h = 0;
+    uint32 rtct_len_l = 0;
+    int32 len_cnt = 0;
+
+    if (pair > 3)
+        return RTK_PHYLIB_ERR_INPUT;
+
+    rtk_phylib_memset(result, 0x0, sizeof(rtk_rtct_channel_result_t));
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_sram_read(phydev, indr_add_ss, 15, 8, &rtct_status));
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_sram_read(phydev, indr_add_lh, 15, 8, &rtct_len_h));
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_sram_read(phydev, indr_add_ll, 15, 8, &rtct_len_l));
+
+    result->cable_status = RTK_PHYLIB_CABLE_STATUS_NORMAL;
+    switch (rtct_status)
+    {
+        case 0x60: /* normal */
+            result->cable_status = RTK_PHYLIB_CABLE_STATUS_NORMAL;
+            break;
+        case 0x48: /* open */
+            result->cable_status |= RTK_PHYLIB_CABLE_STATUS_OPEN;
+            break;
+        case 0x50: /* short */
+            result->cable_status |= RTK_PHYLIB_CABLE_STATUS_SHORT;
+            break;
+        case 0xC0: /* inter pair short */
+            result->cable_status |= RTK_PHYLIB_CABLE_STATUS_INTER_PAIR_SHORT;
+            break;
+        case 0x42: /* mismatch-open */
+            result->cable_status |= RTK_PHYLIB_CABLE_STATUS_MISMATCH;
+            result->cable_status |= RTK_PHYLIB_CABLE_STATUS_OPEN;
+            break;
+        case 0x44: /* mismatch-short */
+            result->cable_status |= RTK_PHYLIB_CABLE_STATUS_MISMATCH;
+            result->cable_status |= RTK_PHYLIB_CABLE_STATUS_SHORT;
+            break;
+        default:
+            result->cable_status |= RTK_PHYLIB_CABLE_STATUS_INTER_PAIR_SHORT;
+            break;
+    }
+
+    len_cnt = ((int32)rtct_len_h << 8) + (int32)rtct_len_l - cable_offset;
+    if (len_cnt < 0)
+        result->length_cm = 0;
+    else
+        result->length_cm = ((uint32)len_cnt * 10000)/cable_factor;
+
+    if ((rtct_status == 0x60) && (result->length_cm < 1500)) //status is normal && length < 15M
+        result->length_cm = result->length_cm/2;
+
+    return 0;
+}
+
+/* Interrupt */
+int rtk_phylib_826xb_intr_enable(rtk_phydev *phydev, uint32 en)
+{
+    int32  ret = 0;
+    /* enable normal interrupt IMR_INT_PHY0 */
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0xE1, 0, 0, (en == 0) ? 0x0 : 0x1));
+
+    return ret;
+}
+
+int rtk_phylib_826xb_intr_read_clear(rtk_phydev *phydev, uint32 *status)
+{
+    int32  ret = 0;
+    uint32 rData = 0;
+    uint32 rStatus = 0;
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 31, 0xA43A, 15, 0, &rData));
+    if(rData & BIT_1)
+        rStatus |= RTK_PHY_INTR_RLFD;
+    if(rData & BIT_2)
+        rStatus |= RTK_PHY_INTR_NEXT_PAGE_RECV;
+    if(rData & BIT_3)
+        rStatus |= RTK_PHY_INTR_AN_COMPLETE;
+    if(rData & BIT_4)
+        rStatus |= RTK_PHY_INTR_LINK_CHANGE;
+    if(rData & BIT_9)
+        rStatus |= RTK_PHY_INTR_ALDPS_STATE_CHANGE;
+    if(rData & BIT_11)
+        rStatus |= RTK_PHY_INTR_FATAL_ERROR;
+    if(rData & BIT_7)
+        rStatus |= RTK_PHY_INTR_WOL;
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 30, 0xE2, 15, 0, &rData));
+    if(rData & BIT_3)
+        rStatus |= RTK_PHY_INTR_TM_LOW;
+    if(rData & BIT_4)
+        rStatus |= RTK_PHY_INTR_TM_HIGH;
+    if(rData & BIT_6)
+        rStatus |= RTK_PHY_INTR_MACSEC;
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0xE2, 15, 0, 0xFF));
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x2DC, 15, 0, 0xFF));
+
+    *status = rStatus;
+    return ret;
+}
+
+int rtk_phylib_826xb_intr_init(rtk_phydev *phydev)
+{
+    int32  ret = 0;
+    uint32 status = 0;
+
+    /* Disable all IMR*/
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0xE1, 15, 0, 0));
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0xE3, 15, 0, 0));
+
+    /* source */
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0xE4, 15, 0, 0x1));
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0xE0, 15, 0, 0x2F));
+
+    /* init common link change */
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xA424,  15,  0, 0x10));
+    /* init rlfd */
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xA442, 15, 15, 0x1));
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xA448, 7, 7, 0x1));
+    /* init tm */
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x1A0, 11, 11, 0x1));
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x19D, 11, 11, 0x1));
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x1A1, 11, 11, 0x1));
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 30, 0x19F, 11, 11, 0x1));
+    /* init WOL */
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xA424,  7,  7, 0x1));
+
+    /* clear status */
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_826xb_intr_read_clear(phydev, &status));
+
+    return ret;
+}
+
+int rtk_phylib_826xb_link_down_power_saving_set(rtk_phydev *phydev, uint32 ena)
+{
+    int32  ret = 0;
+    uint32 data =  (ena > 0) ? 0x1 : 0x0;
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xA430, 2, 2, data));
+    return ret;
+}
+
+int rtk_phylib_826xb_link_down_power_saving_get(rtk_phydev *phydev, uint32 *pEna)
+{
+    int32  ret = 0;
+    uint32 data = 0;
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 31, 0xA430, 2, 2, &data));
+    *pEna = data;
+    return ret;
+}
+
+int rtk_phylib_826xb_wol_reset(rtk_phydev *phydev)
+{
+    int32  ret = 0;
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xD8A2, 15, 15, 0));
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xD8A2, 15, 15, 1));
+    return ret;
+}
+
+int rtk_phylib_826xb_wol_set(rtk_phydev *phydev, uint32 wol_opts)
+{
+    int32 ret = 0;
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xD8A0, 13, 13, (wol_opts & RTK_WOL_OPT_LINK) ? 1 : 0));
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xD8A0, 12, 12, (wol_opts & RTK_WOL_OPT_MAGIC) ? 1 : 0));
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xD8A0, 10, 10, (wol_opts & RTK_WOL_OPT_UCAST) ? 1 : 0));
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xD8A0, 9, 9, (wol_opts & RTK_WOL_OPT_MCAST) ? 1 : 0));
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xD8A0, 8, 8, (wol_opts & RTK_WOL_OPT_BCAST) ? 1 : 0));
+
+    return  ret;
+
+}
+
+int rtk_phylib_826xb_wol_get(rtk_phydev *phydev, uint32 *pWol_opts)
+{
+    int32 ret = 0;
+    uint32 data = 0;
+    uint32 wol_opts = 0;
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 31, 0xD8A0, 13, 13, &data));
+    wol_opts |= ((data) ? RTK_WOL_OPT_LINK : 0);
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 31, 0xD8A0, 12, 12, &data));
+    wol_opts |= ((data) ? RTK_WOL_OPT_MAGIC : 0);
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 31, 0xD8A0, 10, 10, &data));
+    wol_opts |= ((data) ? RTK_WOL_OPT_UCAST : 0);
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 31, 0xD8A0, 9, 9, &data));
+    wol_opts |= ((data) ? RTK_WOL_OPT_MCAST : 0);
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 31, 0xD8A0, 8, 8, &data));
+    wol_opts |= ((data) ? RTK_WOL_OPT_BCAST : 0);
+
+    *pWol_opts = wol_opts;
+    return  ret;
+}
+
+int rtk_phylib_826xb_wol_unicast_addr_set(rtk_phydev *phydev, uint8 *mac_addr)
+{
+    int32 ret = 0;
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xD8C0, 15, 0, (mac_addr[1] << 8 | mac_addr[0])));
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xD8C2, 15, 0, (mac_addr[3] << 8 | mac_addr[2])));
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, 0xD8C4, 15, 0, (mac_addr[5] << 8 | mac_addr[4])));
+    return ret;
+}
+
+uint32 rtk_phylib_826xb_wol_multicast_mac2offset(uint8 *mac_addr)
+{
+    uint32 crc = 0xFFFFFFFF;
+    uint32 i = 0, j = 0;
+    uint32 b0 = 0, b1 = 0, b2 = 0, b3 = 0, b4 = 0, b5 = 0;
+
+    for (i = 0; i < 6; i++) {
+        crc ^= mac_addr[i];
+        for (j = 0; j < 8; j++) {
+            if (crc & 1) {
+                crc = (crc >> 1) ^ 0xEDB88320;
+            } else {
+                crc >>= 1;
+            }
+        }
+    }
+    crc = ~crc;
+
+    b5 = ((crc & 0b000001) << 5 );
+    b4 = ((crc & 0b000010) << 3 );
+    b3 = ((crc & 0b000100) << 1 );
+    b2 = (((crc & 0b001000) ? 0 : 1) << 2 );
+    b1 = (((crc & 0b010000) ? 0 : 1) << 1 );
+    b0 = (((crc & 0b100000) ? 0 : 1) << 0 );
+
+    return (b5 | b4 | b3 | b2 | b1 | b0);
+}
+
+int rtk_phylib_826xb_wol_multicast_mask_add(rtk_phydev *phydev, uint32 offset)
+{
+    const uint32 cfg_reg[4] = {0xD8C6, 0xD8C8, 0xD8CA, 0xD8CC};
+    int32 ret = 0;
+    uint32 idx = offset/16;
+    uint32 multicast_cfg = 0;
+
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_read(phydev, 31, cfg_reg[idx], 15, 0, &multicast_cfg));
+
+    multicast_cfg = (multicast_cfg | (0b1 << (offset % 16)));
+
+    RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, cfg_reg[idx], 15, 0, multicast_cfg));
+    return ret;
+}
+
+int rtk_phylib_826xb_wol_multicast_mask_reset(rtk_phydev *phydev)
+{
+    const uint32 cfg_reg[4] = {0xD8C6, 0xD8C8, 0xD8CA, 0xD8CC};
+    int32 ret = 0;
+    uint32 idx = 0;
+
+    for (idx = 0; idx < 4; idx++)
+    {
+        RTK_PHYLIB_ERR_CHK(rtk_phylib_mmd_write(phydev, 31, cfg_reg[idx], 15, 0, 0));
+    }
+
+    return ret;
+}
diff --git a/sources/rtk-gp3000/src/hal/phy/rtk_phylib_rtl826xb.h b/sources/rtk-gp3000/src/hal/phy/rtk_phylib_rtl826xb.h
new file mode 100644
index 00000000..377ff41f
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/rtk_phylib_rtl826xb.h
@@ -0,0 +1,46 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
+ */
+
+#ifndef __RTK_PHYLIB_RTL826XB_H
+#define __RTK_PHYLIB_RTL826XB_H
+
+#include "rtk_phylib.h"
+
+/* Register Access*/
+int rtk_phylib_826xb_sds_read(rtk_phydev *phydev, uint32 page, uint32 reg, uint8 msb, uint8 lsb, uint32 *pData);
+int rtk_phylib_826xb_sds_write(rtk_phydev *phydev, uint32 page, uint32 reg, uint8 msb, uint8 lsb, uint32 data);
+
+/* Interrupt */
+int rtk_phylib_826xb_intr_enable(rtk_phydev *phydev, uint32 en);
+int rtk_phylib_826xb_intr_read_clear(rtk_phydev *phydev, uint32 *status);
+int rtk_phylib_826xb_intr_init(rtk_phydev *phydev);
+
+/* Cable Test */
+int rtk_phylib_826xb_cable_test_start(rtk_phydev *phydev);;
+int rtk_phylib_826xb_cable_test_finished_get(rtk_phydev *phydev, uint32 *finished);
+int rtk_phylib_826xb_cable_test_result_get(rtk_phydev *phydev, uint32 pair, rtk_rtct_channel_result_t *result);
+
+/* MACsec */
+int rtk_phylib_826xb_macsec_init(rtk_phydev *phydev);
+int rtk_phylib_826xb_macsec_read(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 reg, uint8 msb, uint8 lsb, uint32 *pData);
+int rtk_phylib_826xb_macsec_write(rtk_phydev *phydev, rtk_macsec_dir_t dir, uint32 reg, uint8 msb, uint8 lsb, uint32 data);
+int rtk_phylib_826xb_macsec_bypass_set(rtk_phydev *phydev, uint32 bypass);
+int rtk_phylib_826xb_macsec_bypass_get(rtk_phydev *phydev, uint32 *pBypass);
+
+/* Link-down-power-saving/EDPD */
+int rtk_phylib_826xb_link_down_power_saving_set(rtk_phydev *phydev, uint32 ena);
+int rtk_phylib_826xb_link_down_power_saving_get(rtk_phydev *phydev, uint32 *pEna);
+
+/* Wake on Lan */
+int rtk_phylib_826xb_wol_reset(rtk_phydev *phydev);
+int rtk_phylib_826xb_wol_set(rtk_phydev *phydev, uint32 wol_opts);
+int rtk_phylib_826xb_wol_get(rtk_phydev *phydev, uint32 *pWol_opts);
+int rtk_phylib_826xb_wol_unicast_addr_set(rtk_phydev *phydev, uint8 *mac_addr);
+int rtk_phylib_826xb_wol_multicast_mask_add(rtk_phydev *phydev, uint32 offset);
+int rtk_phylib_826xb_wol_multicast_mask_reset(rtk_phydev *phydev);
+uint32 rtk_phylib_826xb_wol_multicast_mac2offset(uint8 *mac_addr);
+
+#endif /* __RTK_PHYLIB_RTL826XB_H */
diff --git a/sources/rtk-gp3000/src/hal/phy/type.h b/sources/rtk-gp3000/src/hal/phy/type.h
new file mode 100644
index 00000000..98d7e15e
--- /dev/null
+++ b/sources/rtk-gp3000/src/hal/phy/type.h
@@ -0,0 +1,117 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-only
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corp. All rights reserved.
+ */
+
+#ifndef __COMMON_TYPE_H__
+#define __COMMON_TYPE_H__
+
+/*
+ * Symbol Definition
+ */
+
+#define USING_RTSTK_PKT_AS_RAIL
+
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#ifndef ETHER_ADDR_LEN
+#define ETHER_ADDR_LEN 6
+#endif
+
+#ifndef IP6_ADDR_LEN
+#define IP6_ADDR_LEN    16
+#endif
+
+
+/*
+ * Data Type Declaration
+ */
+#ifndef uint64
+typedef unsigned long long  uint64;
+#endif
+
+#ifndef int64
+typedef signed long long    int64;
+#endif
+
+#ifndef uint32
+typedef unsigned int        uint32;
+#endif
+
+#ifndef int32
+typedef signed int          int32;
+#endif
+
+#ifndef uint16
+typedef unsigned short      uint16;
+#endif
+
+#ifndef int16
+typedef signed short        int16;
+#endif
+
+#ifndef uint8
+typedef unsigned char       uint8;
+#endif
+
+#ifndef int8
+typedef signed char         int8;
+#endif
+
+//#define CONFIG_SDK_WORDSIZE_64 /* not ready */
+#ifdef CONFIG_SDK_WORDSIZE_64
+  typedef long int                intptr;
+  typedef unsigned long int       uintptr;
+#else
+  typedef int                     intptr;
+  typedef unsigned int            uintptr;
+#endif
+
+
+#ifndef ipaddr_t
+typedef uint32  ipaddr_t;           /* ipv4 address type */
+#endif
+
+/* configuration mode type */
+typedef enum rtk_enable_e
+{
+    DISABLED = 0,
+    ENABLED,
+    RTK_ENABLE_END
+} rtk_enable_t;
+
+/* initial state of module */
+typedef enum init_state_e
+{
+    INIT_NOT_COMPLETED = 0,
+    INIT_COMPLETED,
+    INIT_STATE_END
+} init_state_t;
+
+/* ethernet address type */
+typedef struct  rtk_mac_s
+{
+    uint8 octet[ETHER_ADDR_LEN];
+} rtk_mac_t;
+
+typedef uint32  osal_time_t;
+typedef uint32  osal_usecs_t;
+
+/*
+ * Macro Definition
+ */
+
+#endif /* __COMMON_TYPE_H__ */
+