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@ -17,9 +17,9 @@ Page | Register | Bits | Feature | Documentation
0xa44 | 0x11 | 03:03 | UTP_DOWN_SPEED_ENABLE
0xa44 | 0x11 | 02:02 | 2PAIR_AUTO_DOWNSPEED
**Page** | **Register** | **Bits** | **unknown** |
0xb80 | 0x10 | 04:04 | PATCH_READY | patch step 2: wait for 1 to start patching
0xb80 | 0x10 | 04:04 | PATCH_READY | patch step 2: wait for 1 to start patching, go over to 0xa43:0x1b
**Page** | **Register** | **Bits** | **unknown** |
0xb82 | 0x10 | 04:04 | ENABLE_PATCH | patch step 1: set to 1 to start
0xb82 | 0x10 | 04:04 | ENABLE_PATCH | patch step 1: set to 1 to start, go over to 0xb80:0x10
These additional/internal registers are organized in pages of 8. Each page knows registers 0x10-0x17. Their "absoulte" address can be calucalted by the formula page * 8 + (register - 16). It seems as if they are for the whole chip package and only accessed via the first port.