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@ -1,5 +1,7 @@
RTL8218B Register Layout
Page | Register | Bits | MAC SerDes 0 - page 0 | Description
--- | --- | --- | --- | ---
0x404 | 0x10 | 15:15 | DIS_RENWAY |
@ -16,6 +18,16 @@ Page | Register | Bits | MAC SerDes 0 - page 0 | Description
0x404 | 0x10 | 02:02 | SDS_TX_DOWN |
0x404 | 0x10 | 01:01 | SDS_EN_RX |
0x404 | 0x10 | 00:00 | SDS_EN_TX |
**Page** | **Register** | **Bits** | **MAC SerDes 0 - page 3** | **Description**
0x404 | 0x13 | 15:15 | WR_SOFT_RSTB
0x404 | 0x13 | 14:14 | USE_25M_CLK
0x404 | 0x13 | 13:13 | MARK_CARR_EXT
0x404 | 0x13 | 12:12 | SEL_DEG
0x404 | 0x13 | 11:08 | REG_CALIB_OK_CNT
0x404 | 0x13 | 07:07 | EXT_PWR_CTL
0x404 | 0x13 | 06:06 | SOFT_RST
0x404 | 0x13 | 05:05 | CLR_SOFT_RSTB
0x404 | 0x13 | 04:00 | CMA_RQ
**Page** | **Register** | **Bits** | **MAC SerDes 0 - page 4** | **Description**
0x404 | 0x14 | 15:13 | CFG_FRC_SDS_MODE | 0x6 = QSGMII
0x404 | 0x14 | 12:12 | CFG_FRC_SDS_MODE_EN | Enable SerDes forced mode
@ -51,6 +63,16 @@ Page | Register | Bits | MAC SerDes 0 - page 0 | Description
0x424 | 0x10 | 02:02 | SDS_TX_DOWN |
0x424 | 0x10 | 01:01 | SDS_EN_RX |
0x424 | 0x10 | 00:00 | SDS_EN_TX |
**Page** | **Register** | **Bits** | **MAC SerDes 0 - page 3** | **Description**
0x404 | 0x13 | 15:15 | WR_SOFT_RSTB
0x404 | 0x13 | 14:14 | USE_25M_CLK
0x404 | 0x13 | 13:13 | MARK_CARR_EXT
0x404 | 0x13 | 12:12 | SEL_DEG
0x404 | 0x13 | 11:08 | REG_CALIB_OK_CNT
0x404 | 0x13 | 07:07 | EXT_PWR_CTL
0x404 | 0x13 | 06:06 | SOFT_RST
0x404 | 0x13 | 05:05 | CLR_SOFT_RSTB
0x404 | 0x13 | 04:00 | CMA_RQ
**Page** | **Register** | **Bits** | **MAC SerDes 1 - page 4** | **Description**
0x424 | 0x14 | 15:13 | CFG_FRC_SDS_MODE |
0x424 | 0x14 | 12:12 | CFG_FRC_SDS_MODE_EN |