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@ -9,11 +9,17 @@ Page | Register | Bits | Feature | Documentation
**Page** | **Register** | **Bits** | **unknown** |
0xa42 | 0x14 | 07:07 | 500M_EEE_ABILITY
**Page** | **Register** | **Bits** | **unknown** |
0xa43 | 0x1B | 15:00 | PATCH_ADDRESS | patch step 3, 5, 7, .. write address to be patched
0xa43 | 0x1C | 15:00 | PATCH_VALUE | patch step 4, 6, 8, ... write value to be patched at address
**Page** | **Register** | **Bits** | **unknown** |
0xa44 | 0x11 | 09:09 | RETRY_DOWN_SPEED_500
0xa44 | 0x11 | 05:05 | UTP_DOWN_SPEED | 0 = 100MBit
0xa44 | 0x11 | 03:03 | UTP_DOWN_SPEED_ENABLE
0xa44 | 0x11 | 02:02 | 2PAIR_AUTO_DOWNSPEED
**Page** | **Register** | **Bits** | **unknown** |
0xb80 | 0x10 | 04:04 | PATCH_READY | patch step 2: wait for 1 to start patching
**Page** | **Register** | **Bits** | **unknown** |
0xb82 | 0x10 | 04:04 | ENABLE_PATCH | patch step 1: set to 1 to start
These additional/internal registers are organized in pages of 8. Each page knows registers 0x10-0x17. Their "absoulte" address can be calucalted by the formula page * 8 + (register - 16). It seems as if they are for the whole chip package and only accessed via the first port.