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@ -30,7 +30,7 @@ Page | Register | Bits | Feature | Documentation
0x2C1 | 0x15 | 15:00 | PTP_TIME_SEC_H_RO 0x2C1 | 0x15 | 15:00 | PTP_TIME_SEC_H_RO
0x2C1 | 0x16 | 15:00 | PTP_TIME_CFG_1 0x2C1 | 0x16 | 15:00 | PTP_TIME_CFG_1
0x2C1 | 0x17 | 15:00 | PTP_TIME_INT_STS_P 0x2C1 | 0x17 | 15:00 | PTP_TIME_INT_STS_P
**Page** | **Register** | **Bits** | **MAC SerDes 0 - page 0** | **Absolute 0x2020** **Page** | **Register** | **Bits** | **MAC SerDes 0 - register 0** | **Absolute 0x2020**
0x404 | 0x10 | 15:15 | DIS_RENWAY | 0x404 | 0x10 | 15:15 | DIS_RENWAY |
0x404 | 0x10 | 14:14 | BYP_8B10B | 0x404 | 0x10 | 14:14 | BYP_8B10B |
0x404 | 0x10 | 13:12 | CDET | 0x404 | 0x10 | 13:12 | CDET |
@ -45,7 +45,7 @@ Page | Register | Bits | Feature | Documentation
0x404 | 0x10 | 02:02 | SDS_TX_DOWN | 0x404 | 0x10 | 02:02 | SDS_TX_DOWN |
0x404 | 0x10 | 01:01 | SDS_EN_RX | 0x404 | 0x10 | 01:01 | SDS_EN_RX |
0x404 | 0x10 | 00:00 | SDS_EN_TX | 0x404 | 0x10 | 00:00 | SDS_EN_TX |
**Page** | **Register** | **Bits** | **MAC SerDes 0 - page 3** | **Absolute 0x2023** **Page** | **Register** | **Bits** | **MAC SerDes 0 - register 3** | **Absolute 0x2023**
0x404 | 0x13 | 15:15 | WR_SOFT_RSTB 0x404 | 0x13 | 15:15 | WR_SOFT_RSTB
0x404 | 0x13 | 14:14 | USE_25M_CLK 0x404 | 0x13 | 14:14 | USE_25M_CLK
0x404 | 0x13 | 13:13 | MARK_CARR_EXT 0x404 | 0x13 | 13:13 | MARK_CARR_EXT
@ -55,7 +55,7 @@ Page | Register | Bits | Feature | Documentation
0x404 | 0x13 | 06:06 | SOFT_RST | Set to 1 then to 0 to run digital soft reset 0x404 | 0x13 | 06:06 | SOFT_RST | Set to 1 then to 0 to run digital soft reset
0x404 | 0x13 | 05:05 | CLR_SOFT_RSTB 0x404 | 0x13 | 05:05 | CLR_SOFT_RSTB
0x404 | 0x13 | 04:00 | CMA_RQ 0x404 | 0x13 | 04:00 | CMA_RQ
**Page** | **Register** | **Bits** | **MAC SerDes 0 - page 4** | **Absolute 0x2024** **Page** | **Register** | **Bits** | **MAC SerDes 0 - register 4** | **Absolute 0x2024**
0x404 | 0x14 | 15:13 | CFG_FRC_SDS_MODE | 0x6 = QSGMII 0x404 | 0x14 | 15:13 | CFG_FRC_SDS_MODE | 0x6 = QSGMII
0x404 | 0x14 | 12:12 | CFG_FRC_SDS_MODE_EN | Enable SerDes forced mode 0x404 | 0x14 | 12:12 | CFG_FRC_SDS_MODE_EN | Enable SerDes forced mode
0x404 | 0x14 | 11:08 | CFG_UPD_RXD | 0x404 | 0x14 | 11:08 | CFG_UPD_RXD |
@ -64,7 +64,7 @@ Page | Register | Bits | Feature | Documentation
0x404 | 0x14 | 02:02 | CFG_EN_LINK_FIB1G | 0x404 | 0x14 | 02:02 | CFG_EN_LINK_FIB1G |
0x404 | 0x14 | 01:01 | CFG_EN_LINK_SGM | 0x404 | 0x14 | 01:01 | CFG_EN_LINK_SGM |
0x404 | 0x14 | 00:00 | CFG_SGM_CK_SEL | 0x404 | 0x14 | 00:00 | CFG_SGM_CK_SEL |
**Page** | **Register** | **Bits** | **MAC SerDes 0 - page 7** | **Absolute 0x2027** **Page** | **Register** | **Bits** | **MAC SerDes 0 - register 7** | **Absolute 0x2027**
0x404 | 0x17 | 15:15 | CFG_8B10B_NO_CREXT | 0x404 | 0x17 | 15:15 | CFG_8B10B_NO_CREXT |
0x404 | 0x17 | 14:14 | CFG_NEG_CLKWR_A2D | 0x404 | 0x17 | 14:14 | CFG_NEG_CLKWR_A2D |
0x404 | 0x17 | 13:13 | CFG_MIIXF_TS1K | 0x404 | 0x17 | 13:13 | CFG_MIIXF_TS1K |
@ -75,11 +75,16 @@ Page | Register | Bits | Feature | Documentation
0x404 | 0x17 | 08:08 | CFG_MARK_TXSCR_ERR | 0x404 | 0x17 | 08:08 | CFG_MARK_TXSCR_ERR |
0x404 | 0x17 | 07:04 | BYP_START | 0x404 | 0x17 | 07:04 | BYP_START |
0x404 | 0x17 | 03:00 | BYP_END | 0x404 | 0x17 | 03:00 | BYP_END |
**Page** | **Register** | **Bits** | **MAC SerDes 0 - page unknown** | **Absolute 0x202c** **Page** | **Register** | **Bits** | **MAC SerDes 0 - register 12** | **Absolute 0x202c**
0x405 | 0x14 | 15:00 | | 0x405 | 0x14 | 15:08 | CFG_INB_TIMEOUT |
0x405 | 0x14 | 07:04 | ABILITY |
0x405 | 0x14 | 03:03 | RDM_ALGOR | Redundancy algorithm 0 = 16/20b, 1 = 32/40b
0x405 | 0x14 | 02:02 | SD_DET_ALGOR |
0x405 | 0x14 | 01:01 | AUTO_DET_ALGOR |
0x405 | 0x14 | 00:00 | SEND_NP_ON |
**Page** | **Register** | **Bits** | **MAC SerDes 0 - page unknown** | **Absolute 0x2120** **Page** | **Register** | **Bits** | **MAC SerDes 0 - page unknown** | **Absolute 0x2120**
0x40c | 0x11 | 15:00 | | This is some unknown PLL register - write 0x4000 to disable ring PLL 0x40c | 0x11 | 15:00 | | This is some unknown PLL register - write 0x4000 to disable ring PLL
**Page** | **Register** | **Bits** | **MAC SerDes 1 - page 0** | **Absolute 0x2120** **Page** | **Register** | **Bits** | **MAC SerDes 1 - register 0** | **Absolute 0x2120**
0x424 | 0x10 | 15:15 | DIS_RENWAY | 0x424 | 0x10 | 15:15 | DIS_RENWAY |
0x424 | 0x10 | 14:14 | BYP_8B10B | 0x424 | 0x10 | 14:14 | BYP_8B10B |
0x424 | 0x10 | 13:12 | CDET | 0x424 | 0x10 | 13:12 | CDET |
@ -94,7 +99,7 @@ Page | Register | Bits | Feature | Documentation
0x424 | 0x10 | 02:02 | SDS_TX_DOWN | 0x424 | 0x10 | 02:02 | SDS_TX_DOWN |
0x424 | 0x10 | 01:01 | SDS_EN_RX | 0x424 | 0x10 | 01:01 | SDS_EN_RX |
0x424 | 0x10 | 00:00 | SDS_EN_TX | 0x424 | 0x10 | 00:00 | SDS_EN_TX |
**Page** | **Register** | **Bits** | **MAC SerDes 1 - page 3** | **Absolute 0x2123** **Page** | **Register** | **Bits** | **MAC SerDes 1 - register 3** | **Absolute 0x2123**
0x424 | 0x13 | 15:15 | WR_SOFT_RSTB 0x424 | 0x13 | 15:15 | WR_SOFT_RSTB
0x424 | 0x13 | 14:14 | USE_25M_CLK 0x424 | 0x13 | 14:14 | USE_25M_CLK
0x424 | 0x13 | 13:13 | MARK_CARR_EXT 0x424 | 0x13 | 13:13 | MARK_CARR_EXT
@ -104,7 +109,7 @@ Page | Register | Bits | Feature | Documentation
0x424 | 0x13 | 06:06 | SOFT_RST 0x424 | 0x13 | 06:06 | SOFT_RST
0x424 | 0x13 | 05:05 | CLR_SOFT_RSTB 0x424 | 0x13 | 05:05 | CLR_SOFT_RSTB
0x424 | 0x13 | 04:00 | CMA_RQ 0x424 | 0x13 | 04:00 | CMA_RQ
**Page** | **Register** | **Bits** | **MAC SerDes 1 - page 4** | **Absolute 0x2124** **Page** | **Register** | **Bits** | **MAC SerDes 1 - register 4** | **Absolute 0x2124**
0x424 | 0x14 | 15:13 | CFG_FRC_SDS_MODE | 0x424 | 0x14 | 15:13 | CFG_FRC_SDS_MODE |
0x424 | 0x14 | 12:12 | CFG_FRC_SDS_MODE_EN | 0x424 | 0x14 | 12:12 | CFG_FRC_SDS_MODE_EN |
0x424 | 0x14 | 11:08 | CFG_UPD_RXD | 0x424 | 0x14 | 11:08 | CFG_UPD_RXD |
@ -113,7 +118,7 @@ Page | Register | Bits | Feature | Documentation
0x424 | 0x14 | 02:02 | CFG_EN_LINK_FIB1G | 0x424 | 0x14 | 02:02 | CFG_EN_LINK_FIB1G |
0x424 | 0x14 | 01:01 | CFG_EN_LINK_SGM | 0x424 | 0x14 | 01:01 | CFG_EN_LINK_SGM |
0x424 | 0x14 | 00:00 | CFG_SGM_CK_SEL | 0x424 | 0x14 | 00:00 | CFG_SGM_CK_SEL |
**Page** | **Register** | **Bits** | **MAC SerDes 1 - page 7** | **Absolute 0x2127** **Page** | **Register** | **Bits** | **MAC SerDes 1 - register 7** | **Absolute 0x2127**
0x424 | 0x17 | 15:15 | CFG_8B10B_NO_CREXT | 0x424 | 0x17 | 15:15 | CFG_8B10B_NO_CREXT |
0x424 | 0x17 | 14:14 | CFG_NEG_CLKWR_A2D | 0x424 | 0x17 | 14:14 | CFG_NEG_CLKWR_A2D |
0x424 | 0x17 | 13:13 | CFG_MIIXF_TS1K | 0x424 | 0x17 | 13:13 | CFG_MIIXF_TS1K |
@ -124,6 +129,13 @@ Page | Register | Bits | Feature | Documentation
0x424 | 0x17 | 08:08 | CFG_MARK_TXSCR_ERR | 0x424 | 0x17 | 08:08 | CFG_MARK_TXSCR_ERR |
0x424 | 0x17 | 07:04 | BYP_START | 0x424 | 0x17 | 07:04 | BYP_START |
0x424 | 0x17 | 03:00 | BYP_END | 0x424 | 0x17 | 03:00 | BYP_END |
**Page** | **Register** | **Bits** | **MAC SerDes 1 - register 12** | **Absolute 0x212c**
0x425 | 0x14 | 15:08 | CFG_INB_TIMEOUT |
0x425 | 0x14 | 07:04 | ABILITY |
0x425 | 0x14 | 03:03 | RDM_ALGOR | Redundancy algorithm 0 = 16/20b, 1 = 32/40b
0x425 | 0x14 | 02:02 | SD_DET_ALGOR |
0x425 | 0x14 | 01:01 | AUTO_DET_ALGOR |
0x425 | 0x14 | 00:00 | SEND_NP_ON |
**Page** | **Register** | **Bits** | **MAC SerDes 1 - page unknown** | **Absolute 0x2161** **Page** | **Register** | **Bits** | **MAC SerDes 1 - page unknown** | **Absolute 0x2161**
0x42c | 0x11 | 15:00 | | This is some unknown PLL register - write 0x4000 to disable ring PLL 0x42c | 0x11 | 15:00 | | This is some unknown PLL register - write 0x4000 to disable ring PLL
**Page** | **Register** | **Bits** | **MAC SerDes 1 - page unknown** | **Absolute 0x2162** **Page** | **Register** | **Bits** | **MAC SerDes 1 - page unknown** | **Absolute 0x2162**