From f994c26347489ab2b5d3fe1b2dca31a4c09724ab Mon Sep 17 00:00:00 2001 From: graham sanderson Date: Thu, 24 Jul 2025 09:58:19 -0500 Subject: [PATCH] add typedefs and rename dma_channel_config to be consistent --- .../hardware_dma/include/hardware/dma.h | 56 ++++++++++--------- 1 file changed, 31 insertions(+), 25 deletions(-) diff --git a/src/rp2_common/hardware_dma/include/hardware/dma.h b/src/rp2_common/hardware_dma/include/hardware/dma.h index 64c26702..bab2e50c 100644 --- a/src/rp2_common/hardware_dma/include/hardware/dma.h +++ b/src/rp2_common/hardware_dma/include/hardware/dma.h @@ -140,27 +140,33 @@ bool dma_channel_is_claimed(uint channel); * * Names indicate the number of bits. */ -enum dma_channel_transfer_size { +typedef enum dma_channel_transfer_size { DMA_SIZE_8 = 0, ///< Byte transfer (8 bits) DMA_SIZE_16 = 1, ///< Half word transfer (16 bits) DMA_SIZE_32 = 2 ///< Word transfer (32 bits) -}; +} dma_channel_transfer_size_t; /*! \brief Enumeration of types of updates that can be made to the DMA read or write address after each transfer * \ingroup hardware_dma */ -enum dma_address_update_type { +typedef enum dma_address_update_type { DMA_ADDRESS_UPDATE_NONE = 0, ///< The address remains the same after each transfer DMA_ADDRESS_UPDATE_INCREMENT = 1, ///< The address is incremented by the transfer size after each transfer #if !PICO_RP2040 DMA_ADDRESS_UPDATE_INCREMENT_BY_TWO = 2, ///< (RP2350 only) The address is incremented by twice the transfer size after each transfer DMA_ADDRESS_UPDATE_DECREMENT = 3, ///< (RP2350 only) The address is decremented by the transfer size after each transfer #endif -}; +} dma_address_update_type_t; +/*! \brief Opaque representation of a DMA channel configuration that can be later applied to a hardware DMA channel + * \ingroup channel_config + */ typedef struct { uint32_t ctrl; -} dma_channel_config; +} dma_channel_config_t; + +// backwards compatibility +typedef dma_channel_config_t dma_channel_config; #ifndef DMA_ADDRESS_UPDATE_TYPE_TO_DMA_CH_CTRL_READ_BITS #if PICO_RP2040 @@ -206,7 +212,7 @@ typedef struct { * Usually set to DMA_ADDRESS_UPDATE_NONE for peripheral to memory transfers * \sa channel_config_set_read_increment */ -static inline void channel_config_set_read_address_update_type(dma_channel_config *c, enum dma_address_update_type update_type) { +static inline void channel_config_set_read_address_update_type(dma_channel_config_t *c, dma_address_update_type_t update_type) { c->ctrl = (c->ctrl & ~DMA_CH_CTRL_ALL_ADDRESS_UPDATE_READ_BITS) | DMA_ADDRESS_UPDATE_TYPE_TO_DMA_CH_CTRL_READ_BITS(update_type); } @@ -219,7 +225,7 @@ static inline void channel_config_set_read_address_update_type(dma_channel_confi * Usually set to DMA_ADDRESS_UPDATE_NONE for memory to peripheral transfers * \sa channel_config_set_write_increment */ -static inline void channel_config_set_write_address_update_type(dma_channel_config *c, enum dma_address_update_type update_type) { +static inline void channel_config_set_write_address_update_type(dma_channel_config_t *c, dma_address_update_type_t update_type) { c->ctrl = (c->ctrl & ~DMA_CH_CTRL_ALL_ADDRESS_UPDATE_WRITE_BITS) | DMA_ADDRESS_UPDATE_TYPE_TO_DMA_CH_CTRL_WRITE_BITS(update_type); } @@ -237,7 +243,7 @@ static inline void channel_config_set_write_address_update_type(dma_channel_conf * Usually disabled for peripheral to memory transfers * \sa channel_config_set_read_address_update_type */ -static inline void channel_config_set_read_increment(dma_channel_config *c, bool incr) { +static inline void channel_config_set_read_increment(dma_channel_config_t *c, bool incr) { channel_config_set_read_address_update_type(c, incr ? DMA_ADDRESS_UPDATE_INCREMENT : DMA_ADDRESS_UPDATE_NONE); } @@ -254,7 +260,7 @@ static inline void channel_config_set_read_increment(dma_channel_config *c, bool * Usually disabled for memory to peripheral transfers * \sa channel_config_set_write_address_update_type */ -static inline void channel_config_set_write_increment(dma_channel_config *c, bool incr) { +static inline void channel_config_set_write_increment(dma_channel_config_t *c, bool incr) { channel_config_set_write_address_update_type(c, incr ? DMA_ADDRESS_UPDATE_INCREMENT : DMA_ADDRESS_UPDATE_NONE); } @@ -273,7 +279,7 @@ static inline void channel_config_set_write_increment(dma_channel_config *c, boo * \param c Pointer to channel configuration data * \param dreq Source (see description) */ -static inline void channel_config_set_dreq(dma_channel_config *c, uint dreq) { +static inline void channel_config_set_dreq(dma_channel_config_t *c, uint dreq) { assert(dreq <= DREQ_FORCE); c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS) | (dreq << DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB); } @@ -287,7 +293,7 @@ static inline void channel_config_set_dreq(dma_channel_config *c, uint dreq) { * \param c Pointer to channel configuration object * \param chain_to Channel to trigger when this channel completes. */ -static inline void channel_config_set_chain_to(dma_channel_config *c, uint chain_to) { +static inline void channel_config_set_chain_to(dma_channel_config_t *c, uint chain_to) { assert(chain_to <= NUM_DMA_CHANNELS); c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS) | (chain_to << DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB); } @@ -301,7 +307,7 @@ static inline void channel_config_set_chain_to(dma_channel_config *c, uint chain * \param c Pointer to channel configuration object * \param size See enum for possible values. */ -static inline void channel_config_set_transfer_data_size(dma_channel_config *c, enum dma_channel_transfer_size size) { +static inline void channel_config_set_transfer_data_size(dma_channel_config_t *c, dma_channel_transfer_size_t size) { assert(size == DMA_SIZE_8 || size == DMA_SIZE_16 || size == DMA_SIZE_32); c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS) | (((uint)size) << DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB); } @@ -321,7 +327,7 @@ static inline void channel_config_set_transfer_data_size(dma_channel_config *c, * \param size_bits 0 to disable wrapping. Otherwise the size in bits of the changing part of the address. * Effectively wraps the address on a (1 << size_bits) byte boundary. */ -static inline void channel_config_set_ring(dma_channel_config *c, bool write, uint size_bits) { +static inline void channel_config_set_ring(dma_channel_config_t *c, bool write, uint size_bits) { assert(size_bits < 32); c->ctrl = (c->ctrl & ~(DMA_CH0_CTRL_TRIG_RING_SIZE_BITS | DMA_CH0_CTRL_TRIG_RING_SEL_BITS)) | (size_bits << DMA_CH0_CTRL_TRIG_RING_SIZE_LSB) | @@ -337,7 +343,7 @@ static inline void channel_config_set_ring(dma_channel_config *c, bool write, ui * \param c Pointer to channel configuration object * \param bswap True to enable byte swapping */ -static inline void channel_config_set_bswap(dma_channel_config *c, bool bswap) { +static inline void channel_config_set_bswap(dma_channel_config_t *c, bool bswap) { c->ctrl = bswap ? (c->ctrl | DMA_CH0_CTRL_TRIG_BSWAP_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_BSWAP_BITS); } @@ -351,7 +357,7 @@ static inline void channel_config_set_bswap(dma_channel_config *c, bool bswap) { * \param c Pointer to channel configuration object * \param irq_quiet True to enable quiet mode, false to disable. */ -static inline void channel_config_set_irq_quiet(dma_channel_config *c, bool irq_quiet) { +static inline void channel_config_set_irq_quiet(dma_channel_config_t *c, bool irq_quiet) { c->ctrl = irq_quiet ? (c->ctrl | DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS); } @@ -369,7 +375,7 @@ static inline void channel_config_set_irq_quiet(dma_channel_config *c, bool irq_ * \param c Pointer to channel configuration object * \param high_priority True to enable high priority */ -static inline void channel_config_set_high_priority(dma_channel_config *c, bool high_priority) { +static inline void channel_config_set_high_priority(dma_channel_config_t *c, bool high_priority) { c->ctrl = high_priority ? (c->ctrl | DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS); } @@ -384,7 +390,7 @@ static inline void channel_config_set_high_priority(dma_channel_config *c, bool * \param enable True to enable the DMA channel. When enabled, the channel will respond to triggering events, and start transferring data. * */ -static inline void channel_config_set_enable(dma_channel_config *c, bool enable) { +static inline void channel_config_set_enable(dma_channel_config_t *c, bool enable) { c->ctrl = enable ? (c->ctrl | DMA_CH0_CTRL_TRIG_EN_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_EN_BITS); } @@ -396,7 +402,7 @@ static inline void channel_config_set_enable(dma_channel_config *c, bool enable) * \param c Pointer to channel configuration object * \param sniff_enable True to enable the Sniff HW access to this DMA channel. */ -static inline void channel_config_set_sniff_enable(dma_channel_config *c, bool sniff_enable) { +static inline void channel_config_set_sniff_enable(dma_channel_config_t *c, bool sniff_enable) { c->ctrl = sniff_enable ? (c->ctrl | DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS); } @@ -421,8 +427,8 @@ static inline void channel_config_set_sniff_enable(dma_channel_config *c, bool s * \param channel DMA channel * \return the default configuration which can then be modified. */ -static inline dma_channel_config dma_channel_get_default_config(uint channel) { - dma_channel_config c = {0}; +static inline dma_channel_config_t dma_channel_get_default_config(uint channel) { + dma_channel_config_t c = {0}; channel_config_set_read_increment(&c, true); channel_config_set_write_increment(&c, false); channel_config_set_dreq(&c, DREQ_FORCE); @@ -443,8 +449,8 @@ static inline dma_channel_config dma_channel_get_default_config(uint channel) { * \param channel DMA channel * \return The current configuration as read from the HW register (not cached) */ -static inline dma_channel_config dma_get_channel_config(uint channel) { - dma_channel_config c; +static inline dma_channel_config_t dma_get_channel_config(uint channel) { + dma_channel_config_t c; c.ctrl = dma_channel_hw_addr(channel)->ctrl_trig; return c; } @@ -455,7 +461,7 @@ static inline dma_channel_config dma_get_channel_config(uint channel) { * \param config Pointer to a config structure. * \return Register content */ -static inline uint32_t channel_config_get_ctrl_value(const dma_channel_config *config) { +static inline uint32_t channel_config_get_ctrl_value(const dma_channel_config_t *config) { return config->ctrl; } @@ -466,7 +472,7 @@ static inline uint32_t channel_config_get_ctrl_value(const dma_channel_config *c * \param config Pointer to a config structure with required configuration * \param trigger True to trigger the transfer immediately */ -static inline void dma_channel_set_config(uint channel, const dma_channel_config *config, bool trigger) { +static inline void dma_channel_set_config(uint channel, const dma_channel_config_t *config, bool trigger) { // Don't use CTRL_TRIG since we don't want to start a transfer if (!trigger) { dma_channel_hw_addr(channel)->al1_ctrl = channel_config_get_ctrl_value(config); @@ -630,7 +636,7 @@ static inline void dma_channel_set_trans_count(uint channel, uint32_t trans_coun * to pass for this argument * \param trigger True to start the transfer immediately */ -static inline void dma_channel_configure(uint channel, const dma_channel_config *config, volatile void *write_addr, +static inline void dma_channel_configure(uint channel, const dma_channel_config_t *config, volatile void *write_addr, const volatile void *read_addr, uint32_t encoded_transfer_count, bool trigger) { dma_channel_set_read_addr(channel, read_addr, false);