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fix errors in generated headers/SVD (#2599)
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This commit is contained in:
Graham Sanderson
GitHub
parent
3f6f0fc0ef
commit
c493a3a64d
16 changed files with 187 additions and 130 deletions
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@ -1759,7 +1759,7 @@ SPDX-License-Identifier: BSD-3-Clause
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<name>CLK_SYS_CTRL</name>
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<addressOffset>0x0000003c</addressOffset>
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<description>Clock control, can be changed on-the-fly (except for auxsrc)</description>
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<resetValue>0x00000000</resetValue>
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<resetValue>0x00000041</resetValue>
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<fields>
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<field>
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<name>AUXSRC</name>
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@ -43232,7 +43232,8 @@ SPDX-License-Identifier: BSD-3-Clause
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<fields>
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<field>
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<name>AUXCTRL</name>
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<description>* Bits 7:2: Reserved
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<description>* Bits 7:3: Reserved
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* Bit 2: Set to mask OTP power analogue power supply detection from resetting OTP controller and PSM
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* Bit 1: When clear, the LPOSC output is XORed into the TRNG ROSC output as an additional, uncorrelated entropy source. When set, this behaviour is disabled.
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@ -47936,9 +47937,9 @@ SPDX-License-Identifier: BSD-3-Clause
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<name>FREQ_RANGE</name>
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<description>Controls the number of delay stages in the ROSC ring
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LOW uses stages 0 to 7
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MEDIUM uses stages 2 to 7
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HIGH uses stages 4 to 7
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TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications
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MEDIUM uses stages 0 to 5
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HIGH uses stages 0 to 3
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TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications
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The clock output will not glitch when changing the range up one step at a time
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The clock output will glitch when changing the range down
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Note: the values here are gray coded which is why HIGH comes before TOOHIGH</description>
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@ -47976,7 +47977,7 @@ SPDX-License-Identifier: BSD-3-Clause
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2 bits set triples drive strength
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3 bits set quadruples drive strength
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For frequency randomisation set both DS0_RANDOM=1 & DS1_RANDOM=1</description>
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<resetValue>0x00000000</resetValue>
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<resetValue>0x00000088</resetValue>
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<fields>
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<field>
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<name>PASSWD</name>
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@ -49053,51 +49054,56 @@ SPDX-License-Identifier: BSD-3-Clause
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bit 0 = SRAM1
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0 = powered up
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1 = powered down
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When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set while the Power Manager determines what is required. If an invalid transition is requested the Power Manager will still register the request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ flag. It will then implement the power-up requests and ignore the power down requests. To do nothing would risk entering an unrecoverable lock-up state. Invalid requests are: any combination of power up and power down requests any request that results in swcore boing powered and xip unpowered If the request is to power down the switched-core domain then POWMAN_STATE_WAITING stays active until the processors halt. During this time the POWMAN_STATE_REQ field can be re-written to change or cancel the request. When the power state transition begins the POWMAN_STATE_WAITING_flag is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored until the transition completes.</description>
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When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set while the Power Manager determines what is required. If an invalid transition is requested the Power Manager will still register the request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ flag. It will then implement the power-up requests and ignore the power down requests. To do nothing would risk entering an unrecoverable lock-up state. Invalid requests are: any combination of power up and power down requests any request that results in swcore being powered and xip unpowered If the request is to power down the switched-core domain then POWMAN_STATE_WAITING stays active until the processors halt. During this time the POWMAN_STATE_REQ field can be re-written to change or cancel the request. When the power state transition begins the POWMAN_STATE_WAITING_flag is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored until the transition completes.</description>
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<resetValue>0x0000000f</resetValue>
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<fields>
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<field>
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<name>CHANGING</name>
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<description>Indicates a power state change is in progress</description>
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<bitRange>[13:13]</bitRange>
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<access>read-only</access>
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</field>
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<field>
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<name>WAITING</name>
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<description>Indicates the power manager has received a state change request and is waiting for other actions to complete before executing it</description>
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<bitRange>[12:12]</bitRange>
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<access>read-only</access>
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</field>
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<field>
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<name>BAD_HW_REQ</name>
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<description>Bad hardware initiated state request. Went back to state 0 (i.e. everything powered up)</description>
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<description>Invalid hardware initiated state request, power up requests actioned, power down requests ignored</description>
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<bitRange>[11:11]</bitRange>
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<access>read-only</access>
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</field>
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<field>
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<name>BAD_SW_REQ</name>
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<description>Bad software initiated state request. No action taken.</description>
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<description>Invalid software initiated state request ignored</description>
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<bitRange>[10:10]</bitRange>
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<access>read-only</access>
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</field>
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<field>
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<name>PWRUP_WHILE_WAITING</name>
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<description>Request ignored because of a pending pwrup request. See current_pwrup_req. Note this blocks powering up AND powering down.</description>
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<description>Indicates that a power state change request was ignored because of a pending power state change request</description>
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<bitRange>[9:9]</bitRange>
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<access>read-write</access>
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<modifiedWriteValues>oneToClear</modifiedWriteValues>
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</field>
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<field>
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<name>REQ_IGNORED</name>
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<description>Indicates that a software state change request was ignored because it clashed with an ongoing hardware or debugger request</description>
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<bitRange>[8:8]</bitRange>
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<access>read-write</access>
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<modifiedWriteValues>oneToClear</modifiedWriteValues>
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</field>
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<field>
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<name>REQ</name>
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<description>This is written by software or hardware to request a new power state</description>
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<bitRange>[7:4]</bitRange>
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<access>read-write</access>
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</field>
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<field>
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<name>CURRENT</name>
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<description>Indicates the current power state</description>
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<bitRange>[3:0]</bitRange>
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<access>read-only</access>
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</field>
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@ -77606,7 +77612,7 @@ SPDX-License-Identifier: BSD-3-Clause
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</field>
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<field>
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<name>SUSPENDED</name>
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<description>Bus in suspended state. Valid for device. Device will go into suspend if neither Keep Alive / SOF frames are enabled.</description>
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<description>Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled.</description>
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<bitRange>[4:4]</bitRange>
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<access>read-write</access>
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<modifiedWriteValues>oneToClear</modifiedWriteValues>
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@ -615,7 +615,7 @@
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// Description : Clock control, can be changed on-the-fly (except for auxsrc)
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#define CLOCKS_CLK_SYS_CTRL_OFFSET _u(0x0000003c)
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#define CLOCKS_CLK_SYS_CTRL_BITS _u(0x000000e1)
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#define CLOCKS_CLK_SYS_CTRL_RESET _u(0x00000000)
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#define CLOCKS_CLK_SYS_CTRL_RESET _u(0x00000041)
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// -----------------------------------------------------------------------------
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// Field : CLOCKS_CLK_SYS_CTRL_AUXSRC
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// Description : Selects the auxiliary clock source, will glitch when switching
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@ -625,7 +625,7 @@
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// 0x3 -> xosc_clksrc
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// 0x4 -> clksrc_gpin0
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// 0x5 -> clksrc_gpin1
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#define CLOCKS_CLK_SYS_CTRL_AUXSRC_RESET _u(0x0)
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#define CLOCKS_CLK_SYS_CTRL_AUXSRC_RESET _u(0x2)
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#define CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS _u(0x000000e0)
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#define CLOCKS_CLK_SYS_CTRL_AUXSRC_MSB _u(7)
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#define CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB _u(5)
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@ -642,7 +642,7 @@
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// fly
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// 0x0 -> clk_ref
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// 0x1 -> clksrc_clk_sys_aux
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#define CLOCKS_CLK_SYS_CTRL_SRC_RESET _u(0x0)
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#define CLOCKS_CLK_SYS_CTRL_SRC_RESET _u(0x1)
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#define CLOCKS_CLK_SYS_CTRL_SRC_BITS _u(0x00000001)
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#define CLOCKS_CLK_SYS_CTRL_SRC_MSB _u(0)
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#define CLOCKS_CLK_SYS_CTRL_SRC_LSB _u(0)
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@ -121,8 +121,8 @@ typedef enum dreq_num_rp2350 {
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DREQ_PWM_WRAP7 = 39, ///< Select PWM Counter 7's Wrap Value as DREQ
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DREQ_PWM_WRAP8 = 40, ///< Select PWM Counter 8's Wrap Value as DREQ
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DREQ_PWM_WRAP9 = 41, ///< Select PWM Counter 9's Wrap Value as DREQ
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DREQ_PWM_WRAP10 = 42, ///< Select PWM Counter 0's Wrap Value as DREQ
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DREQ_PWM_WRAP11 = 43, ///< Select PWM Counter 1's Wrap Value as DREQ
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DREQ_PWM_WRAP10 = 42, ///< Select PWM Counter 10's Wrap Value as DREQ
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DREQ_PWM_WRAP11 = 43, ///< Select PWM Counter 11's Wrap Value as DREQ
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DREQ_I2C0_TX = 44, ///< Select I2C0's TX FIFO as DREQ
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DREQ_I2C0_RX = 45, ///< Select I2C0's RX FIFO as DREQ
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DREQ_I2C1_TX = 46, ///< Select I2C1's TX FIFO as DREQ
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@ -135,8 +135,8 @@ typedef enum dreq_num_rp2350 {
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DREQ_CORESIGHT = 53, ///< Select CORESIGHT as DREQ
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DREQ_SHA256 = 54, ///< Select SHA256 as DREQ
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DREQ_DMA_TIMER0 = 59, ///< Select DMA_TIMER0 as DREQ
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DREQ_DMA_TIMER1 = 60, ///< Select DMA_TIMER0 as DREQ
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DREQ_DMA_TIMER2 = 61, ///< Select DMA_TIMER1 as DREQ
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DREQ_DMA_TIMER1 = 60, ///< Select DMA_TIMER1 as DREQ
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DREQ_DMA_TIMER2 = 61, ///< Select DMA_TIMER2 as DREQ
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DREQ_DMA_TIMER3 = 62, ///< Select DMA_TIMER3 as DREQ
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DREQ_FORCE = 63, ///< Select FORCE as DREQ
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DREQ_COUNT
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@ -37,8 +37,7 @@
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#define GLITCH_DETECTOR_ARM_VALUE_YES _u(0x0000)
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// =============================================================================
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// Register : GLITCH_DETECTOR_DISARM
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// Description : None
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// Forcibly disarm the glitch detectors, if they are armed by OTP.
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// Description : Forcibly disarm the glitch detectors, if they are armed by OTP.
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// Ignored if ARM is YES.
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//
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// This register is Secure read/write only.
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@ -142,8 +141,7 @@
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#define GLITCH_DETECTOR_SENSITIVITY_DET0_ACCESS "RW"
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// =============================================================================
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// Register : GLITCH_DETECTOR_LOCK
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// Description : None
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// Write any nonzero value to disable writes to ARM, DISARM,
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// Description : Write any nonzero value to disable writes to ARM, DISARM,
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// SENSITIVITY and LOCK. This register is Secure read/write only.
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#define GLITCH_DETECTOR_LOCK_OFFSET _u(0x0000000c)
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#define GLITCH_DETECTOR_LOCK_BITS _u(0x000000ff)
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@ -79,8 +79,8 @@ typedef enum irq_num_rp2350 {
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TIMER1_IRQ_1 = 5, ///< Select TIMER1's IRQ 1 output
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TIMER1_IRQ_2 = 6, ///< Select TIMER1's IRQ 2 output
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TIMER1_IRQ_3 = 7, ///< Select TIMER1's IRQ 3 output
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PWM_IRQ_WRAP_0 = 8, ///< Select PWM's IRQ_WRAP 0 output
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PWM_IRQ_WRAP_1 = 9, ///< Select PWM's IRQ_WRAP 1 output
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PWM_IRQ_WRAP_0 = 8, ///< Select PWM's WRAP_0 IRQ output
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PWM_IRQ_WRAP_1 = 9, ///< Select PWM's WRAP_1 IRQ output
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DMA_IRQ_0 = 10, ///< Select DMA's IRQ 0 output
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DMA_IRQ_1 = 11, ///< Select DMA's IRQ 1 output
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DMA_IRQ_2 = 12, ///< Select DMA's IRQ 2 output
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@ -96,27 +96,27 @@ typedef enum irq_num_rp2350 {
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IO_IRQ_BANK0_NS = 22, ///< Select IO_BANK0_NS's IRQ output
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IO_IRQ_QSPI = 23, ///< Select IO_QSPI's IRQ output
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IO_IRQ_QSPI_NS = 24, ///< Select IO_QSPI_NS's IRQ output
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SIO_IRQ_FIFO = 25, ///< Select SIO's IRQ_FIFO output
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SIO_IRQ_BELL = 26, ///< Select SIO's IRQ_BELL output
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SIO_IRQ_FIFO_NS = 27, ///< Select SIO_NS's IRQ_FIFO output
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SIO_IRQ_BELL_NS = 28, ///< Select SIO_NS's IRQ_BELL output
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SIO_IRQ_MTIMECMP = 29, ///< Select SIO_IRQ_MTIMECMP's IRQ output
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SIO_IRQ_FIFO = 25, ///< Select SIO's FIFO IRQ output
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SIO_IRQ_BELL = 26, ///< Select SIO's BELL IRQ output
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SIO_IRQ_FIFO_NS = 27, ///< Select SIO_NS's FIFO IRQ output
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SIO_IRQ_BELL_NS = 28, ///< Select SIO_NS's BELL IRQ output
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SIO_IRQ_MTIMECMP = 29, ///< Select SIO's MTIMECMP IRQ output
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CLOCKS_IRQ = 30, ///< Select CLOCKS's IRQ output
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SPI0_IRQ = 31, ///< Select SPI0's IRQ output
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SPI1_IRQ = 32, ///< Select SPI1's IRQ output
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UART0_IRQ = 33, ///< Select UART0's IRQ output
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UART1_IRQ = 34, ///< Select UART1's IRQ output
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ADC_IRQ_FIFO = 35, ///< Select ADC's IRQ_FIFO output
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ADC_IRQ_FIFO = 35, ///< Select ADC's FIFO IRQ output
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I2C0_IRQ = 36, ///< Select I2C0's IRQ output
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I2C1_IRQ = 37, ///< Select I2C1's IRQ output
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OTP_IRQ = 38, ///< Select OTP's IRQ output
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TRNG_IRQ = 39, ///< Select TRNG's IRQ output
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PROC0_IRQ_CTI = 40, ///< Select PROC0's IRQ_CTI output
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PROC1_IRQ_CTI = 41, ///< Select PROC1's IRQ_CTI output
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PROC0_IRQ_CTI = 40, ///< Select PROC0's CTI IRQ output
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PROC1_IRQ_CTI = 41, ///< Select PROC1's CTI IRQ output
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PLL_SYS_IRQ = 42, ///< Select PLL_SYS's IRQ output
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PLL_USB_IRQ = 43, ///< Select PLL_USB's IRQ output
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POWMAN_IRQ_POW = 44, ///< Select POWMAN's IRQ_POW output
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POWMAN_IRQ_TIMER = 45, ///< Select POWMAN's IRQ_TIMER output
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POWMAN_IRQ_POW = 44, ///< Select POWMAN's POW IRQ output
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POWMAN_IRQ_TIMER = 45, ///< Select POWMAN's TIMER IRQ output
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SPARE_IRQ_0 = 46, ///< Select SPARE IRQ 0
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SPARE_IRQ_1 = 47, ///< Select SPARE IRQ 1
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SPARE_IRQ_2 = 48, ///< Select SPARE IRQ 2
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@ -461,8 +461,7 @@
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// =============================================================================
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// Register : PIO_DBG_PADOUT
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// Description : Read to sample the pad output values PIO is currently driving
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// to the GPIOs. On RP2040 there are 30 GPIOs, so the two most
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// significant bits are hardwired to 0.
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// to the GPIOs.
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#define PIO_DBG_PADOUT_OFFSET _u(0x0000003c)
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#define PIO_DBG_PADOUT_BITS _u(0xffffffff)
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#define PIO_DBG_PADOUT_RESET _u(0x00000000)
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@ -472,8 +471,7 @@
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// =============================================================================
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// Register : PIO_DBG_PADOE
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// Description : Read to sample the pad output enables (direction) PIO is
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// currently driving to the GPIOs. On RP2040 there are 30 GPIOs,
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// so the two most significant bits are hardwired to 0.
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// currently driving to the GPIOs.
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#define PIO_DBG_PADOE_OFFSET _u(0x00000040)
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#define PIO_DBG_PADOE_BITS _u(0xffffffff)
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#define PIO_DBG_PADOE_RESET _u(0x00000000)
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@ -944,7 +944,7 @@
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// requests and ignore the power down requests. To do nothing
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// would risk entering an unrecoverable lock-up state. Invalid
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// requests are: any combination of power up and power down
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// requests any request that results in swcore boing powered and
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// requests any request that results in swcore being powered and
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// xip unpowered If the request is to power down the switched-core
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// domain then POWMAN_STATE_WAITING stays active until the
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// processors halt. During this time the POWMAN_STATE_REQ field
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@ -957,6 +957,7 @@
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#define POWMAN_STATE_RESET _u(0x0000000f)
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// -----------------------------------------------------------------------------
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// Field : POWMAN_STATE_CHANGING
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// Description : Indicates a power state change is in progress
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#define POWMAN_STATE_CHANGING_RESET _u(0x0)
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#define POWMAN_STATE_CHANGING_BITS _u(0x00002000)
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#define POWMAN_STATE_CHANGING_MSB _u(13)
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@ -964,6 +965,9 @@
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#define POWMAN_STATE_CHANGING_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : POWMAN_STATE_WAITING
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// Description : Indicates the power manager has received a state change request
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// and is waiting for other actions to complete before executing
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// it
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#define POWMAN_STATE_WAITING_RESET _u(0x0)
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#define POWMAN_STATE_WAITING_BITS _u(0x00001000)
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#define POWMAN_STATE_WAITING_MSB _u(12)
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@ -971,8 +975,8 @@
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#define POWMAN_STATE_WAITING_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : POWMAN_STATE_BAD_HW_REQ
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// Description : Bad hardware initiated state request. Went back to state 0
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// (i.e. everything powered up)
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// Description : Invalid hardware initiated state request, power up requests
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// actioned, power down requests ignored
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#define POWMAN_STATE_BAD_HW_REQ_RESET _u(0x0)
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#define POWMAN_STATE_BAD_HW_REQ_BITS _u(0x00000800)
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#define POWMAN_STATE_BAD_HW_REQ_MSB _u(11)
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@ -980,7 +984,7 @@
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#define POWMAN_STATE_BAD_HW_REQ_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : POWMAN_STATE_BAD_SW_REQ
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// Description : Bad software initiated state request. No action taken.
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// Description : Invalid software initiated state request ignored
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#define POWMAN_STATE_BAD_SW_REQ_RESET _u(0x0)
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#define POWMAN_STATE_BAD_SW_REQ_BITS _u(0x00000400)
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#define POWMAN_STATE_BAD_SW_REQ_MSB _u(10)
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@ -988,9 +992,8 @@
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#define POWMAN_STATE_BAD_SW_REQ_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : POWMAN_STATE_PWRUP_WHILE_WAITING
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// Description : Request ignored because of a pending pwrup request. See
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// current_pwrup_req. Note this blocks powering up AND powering
|
||||
// down.
|
||||
// Description : Indicates that a power state change request was ignored because
|
||||
// of a pending power state change request
|
||||
#define POWMAN_STATE_PWRUP_WHILE_WAITING_RESET _u(0x0)
|
||||
#define POWMAN_STATE_PWRUP_WHILE_WAITING_BITS _u(0x00000200)
|
||||
#define POWMAN_STATE_PWRUP_WHILE_WAITING_MSB _u(9)
|
||||
|
|
@ -998,6 +1001,8 @@
|
|||
#define POWMAN_STATE_PWRUP_WHILE_WAITING_ACCESS "WC"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : POWMAN_STATE_REQ_IGNORED
|
||||
// Description : Indicates that a software state change request was ignored
|
||||
// because it clashed with an ongoing hardware or debugger request
|
||||
#define POWMAN_STATE_REQ_IGNORED_RESET _u(0x0)
|
||||
#define POWMAN_STATE_REQ_IGNORED_BITS _u(0x00000100)
|
||||
#define POWMAN_STATE_REQ_IGNORED_MSB _u(8)
|
||||
|
|
@ -1005,6 +1010,8 @@
|
|||
#define POWMAN_STATE_REQ_IGNORED_ACCESS "WC"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : POWMAN_STATE_REQ
|
||||
// Description : This is written by software or hardware to request a new power
|
||||
// state
|
||||
#define POWMAN_STATE_REQ_RESET _u(0x0)
|
||||
#define POWMAN_STATE_REQ_BITS _u(0x000000f0)
|
||||
#define POWMAN_STATE_REQ_MSB _u(7)
|
||||
|
|
@ -1012,6 +1019,7 @@
|
|||
#define POWMAN_STATE_REQ_ACCESS "RW"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : POWMAN_STATE_CURRENT
|
||||
// Description : Indicates the current power state
|
||||
#define POWMAN_STATE_CURRENT_RESET _u(0xf)
|
||||
#define POWMAN_STATE_CURRENT_BITS _u(0x0000000f)
|
||||
#define POWMAN_STATE_CURRENT_MSB _u(3)
|
||||
|
|
@ -1019,8 +1027,7 @@
|
|||
#define POWMAN_STATE_CURRENT_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : POWMAN_POW_FASTDIV
|
||||
// Description : None
|
||||
// divides the POWMAN clock to provide a tick for the delay module
|
||||
// Description : divides the POWMAN clock to provide a tick for the delay module
|
||||
// and state machines
|
||||
// when clk_pow is running from the slow clock it is not divided
|
||||
// when clk_pow is running from the fast clock it is divided by
|
||||
|
|
@ -1187,6 +1194,10 @@
|
|||
#define POWMAN_EXT_TIME_REF_SOURCE_SEL_MSB _u(1)
|
||||
#define POWMAN_EXT_TIME_REF_SOURCE_SEL_LSB _u(0)
|
||||
#define POWMAN_EXT_TIME_REF_SOURCE_SEL_ACCESS "RW"
|
||||
#define POWMAN_EXT_TIME_REF_SOURCE_SEL_VALUE_GPIO12 _u(0x0)
|
||||
#define POWMAN_EXT_TIME_REF_SOURCE_SEL_VALUE_GPIO20 _u(0x1)
|
||||
#define POWMAN_EXT_TIME_REF_SOURCE_SEL_VALUE_GPIO14 _u(0x2)
|
||||
#define POWMAN_EXT_TIME_REF_SOURCE_SEL_VALUE_GPIO22 _u(0x3)
|
||||
// =============================================================================
|
||||
// Register : POWMAN_LPOSC_FREQ_KHZ_INT
|
||||
// Description : Informs the AON Timer of the integer component of the clock
|
||||
|
|
@ -1241,8 +1252,7 @@
|
|||
#define POWMAN_XOSC_FREQ_KHZ_FRAC_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : POWMAN_SET_TIME_63TO48
|
||||
// Description : None
|
||||
// For setting the time, do not use for reading the time, use
|
||||
// Description : For setting the time, do not use for reading the time, use
|
||||
// POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field
|
||||
// must only be written when POWMAN_TIMER_RUN=0
|
||||
#define POWMAN_SET_TIME_63TO48_OFFSET _u(0x00000060)
|
||||
|
|
@ -1253,8 +1263,7 @@
|
|||
#define POWMAN_SET_TIME_63TO48_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : POWMAN_SET_TIME_47TO32
|
||||
// Description : None
|
||||
// For setting the time, do not use for reading the time, use
|
||||
// Description : For setting the time, do not use for reading the time, use
|
||||
// POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field
|
||||
// must only be written when POWMAN_TIMER_RUN=0
|
||||
#define POWMAN_SET_TIME_47TO32_OFFSET _u(0x00000064)
|
||||
|
|
@ -1265,8 +1274,7 @@
|
|||
#define POWMAN_SET_TIME_47TO32_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : POWMAN_SET_TIME_31TO16
|
||||
// Description : None
|
||||
// For setting the time, do not use for reading the time, use
|
||||
// Description : For setting the time, do not use for reading the time, use
|
||||
// POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field
|
||||
// must only be written when POWMAN_TIMER_RUN=0
|
||||
#define POWMAN_SET_TIME_31TO16_OFFSET _u(0x00000068)
|
||||
|
|
@ -1277,8 +1285,7 @@
|
|||
#define POWMAN_SET_TIME_31TO16_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : POWMAN_SET_TIME_15TO0
|
||||
// Description : None
|
||||
// For setting the time, do not use for reading the time, use
|
||||
// Description : For setting the time, do not use for reading the time, use
|
||||
// POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field
|
||||
// must only be written when POWMAN_TIMER_RUN=0
|
||||
#define POWMAN_SET_TIME_15TO0_OFFSET _u(0x0000006c)
|
||||
|
|
@ -1289,8 +1296,7 @@
|
|||
#define POWMAN_SET_TIME_15TO0_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : POWMAN_READ_TIME_UPPER
|
||||
// Description : None
|
||||
// For reading bits 63:32 of the timer. When reading all 64 bits
|
||||
// Description : For reading bits 63:32 of the timer. When reading all 64 bits
|
||||
// it is possible for the LOWER count to rollover during the read.
|
||||
// It is recommended to read UPPER, then LOWER, then re-read UPPER
|
||||
// and, if it has changed, re-read LOWER.
|
||||
|
|
@ -1302,8 +1308,7 @@
|
|||
#define POWMAN_READ_TIME_UPPER_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : POWMAN_READ_TIME_LOWER
|
||||
// Description : None
|
||||
// For reading bits 31:0 of the timer.
|
||||
// Description : For reading bits 31:0 of the timer.
|
||||
#define POWMAN_READ_TIME_LOWER_OFFSET _u(0x00000074)
|
||||
#define POWMAN_READ_TIME_LOWER_BITS _u(0xffffffff)
|
||||
#define POWMAN_READ_TIME_LOWER_RESET _u(0x00000000)
|
||||
|
|
@ -1312,8 +1317,7 @@
|
|||
#define POWMAN_READ_TIME_LOWER_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : POWMAN_ALARM_TIME_63TO48
|
||||
// Description : None
|
||||
// This field must only be written when POWMAN_ALARM_ENAB=0
|
||||
// Description : This field must only be written when POWMAN_ALARM_ENAB=0
|
||||
#define POWMAN_ALARM_TIME_63TO48_OFFSET _u(0x00000078)
|
||||
#define POWMAN_ALARM_TIME_63TO48_BITS _u(0x0000ffff)
|
||||
#define POWMAN_ALARM_TIME_63TO48_RESET _u(0x00000000)
|
||||
|
|
@ -1322,8 +1326,7 @@
|
|||
#define POWMAN_ALARM_TIME_63TO48_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : POWMAN_ALARM_TIME_47TO32
|
||||
// Description : None
|
||||
// This field must only be written when POWMAN_ALARM_ENAB=0
|
||||
// Description : This field must only be written when POWMAN_ALARM_ENAB=0
|
||||
#define POWMAN_ALARM_TIME_47TO32_OFFSET _u(0x0000007c)
|
||||
#define POWMAN_ALARM_TIME_47TO32_BITS _u(0x0000ffff)
|
||||
#define POWMAN_ALARM_TIME_47TO32_RESET _u(0x00000000)
|
||||
|
|
@ -1332,8 +1335,7 @@
|
|||
#define POWMAN_ALARM_TIME_47TO32_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : POWMAN_ALARM_TIME_31TO16
|
||||
// Description : None
|
||||
// This field must only be written when POWMAN_ALARM_ENAB=0
|
||||
// Description : This field must only be written when POWMAN_ALARM_ENAB=0
|
||||
#define POWMAN_ALARM_TIME_31TO16_OFFSET _u(0x00000080)
|
||||
#define POWMAN_ALARM_TIME_31TO16_BITS _u(0x0000ffff)
|
||||
#define POWMAN_ALARM_TIME_31TO16_RESET _u(0x00000000)
|
||||
|
|
@ -1342,8 +1344,7 @@
|
|||
#define POWMAN_ALARM_TIME_31TO16_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : POWMAN_ALARM_TIME_15TO0
|
||||
// Description : None
|
||||
// This field must only be written when POWMAN_ALARM_ENAB=0
|
||||
// Description : This field must only be written when POWMAN_ALARM_ENAB=0
|
||||
#define POWMAN_ALARM_TIME_15TO0_OFFSET _u(0x00000084)
|
||||
#define POWMAN_ALARM_TIME_15TO0_BITS _u(0x0000ffff)
|
||||
#define POWMAN_ALARM_TIME_15TO0_RESET _u(0x00000000)
|
||||
|
|
|
|||
|
|
@ -39,9 +39,9 @@
|
|||
// Field : ROSC_CTRL_FREQ_RANGE
|
||||
// Description : Controls the number of delay stages in the ROSC ring
|
||||
// LOW uses stages 0 to 7
|
||||
// MEDIUM uses stages 2 to 7
|
||||
// HIGH uses stages 4 to 7
|
||||
// TOOHIGH uses stages 6 to 7 and should not be used because its
|
||||
// MEDIUM uses stages 0 to 5
|
||||
// HIGH uses stages 0 to 3
|
||||
// TOOHIGH uses stages 0 to 1 and should not be used because its
|
||||
// frequency exceeds design specifications
|
||||
// The clock output will not glitch when changing the range up one
|
||||
// step at a time
|
||||
|
|
@ -77,7 +77,7 @@
|
|||
// DS1_RANDOM=1
|
||||
#define ROSC_FREQA_OFFSET _u(0x00000004)
|
||||
#define ROSC_FREQA_BITS _u(0xffff77ff)
|
||||
#define ROSC_FREQA_RESET _u(0x00000000)
|
||||
#define ROSC_FREQA_RESET _u(0x00000088)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : ROSC_FREQA_PASSWD
|
||||
// Description : Set to 0x9696 to apply the settings
|
||||
|
|
@ -108,7 +108,7 @@
|
|||
// -----------------------------------------------------------------------------
|
||||
// Field : ROSC_FREQA_DS1_RANDOM
|
||||
// Description : Randomises the stage 1 drive strength
|
||||
#define ROSC_FREQA_DS1_RANDOM_RESET _u(0x0)
|
||||
#define ROSC_FREQA_DS1_RANDOM_RESET _u(0x1)
|
||||
#define ROSC_FREQA_DS1_RANDOM_BITS _u(0x00000080)
|
||||
#define ROSC_FREQA_DS1_RANDOM_MSB _u(7)
|
||||
#define ROSC_FREQA_DS1_RANDOM_LSB _u(7)
|
||||
|
|
@ -124,7 +124,7 @@
|
|||
// -----------------------------------------------------------------------------
|
||||
// Field : ROSC_FREQA_DS0_RANDOM
|
||||
// Description : Randomises the stage 0 drive strength
|
||||
#define ROSC_FREQA_DS0_RANDOM_RESET _u(0x0)
|
||||
#define ROSC_FREQA_DS0_RANDOM_RESET _u(0x1)
|
||||
#define ROSC_FREQA_DS0_RANDOM_BITS _u(0x00000008)
|
||||
#define ROSC_FREQA_DS0_RANDOM_MSB _u(3)
|
||||
#define ROSC_FREQA_DS0_RANDOM_LSB _u(3)
|
||||
|
|
@ -206,7 +206,7 @@
|
|||
// On power-up this field is initialised to WAKE
|
||||
// An invalid write will also select WAKE
|
||||
// Warning: setup the irq before selecting dormant mode
|
||||
// 0x636f6d61 -> dormant
|
||||
// 0x636f6d61 -> DORMANT
|
||||
// 0x77616b65 -> WAKE
|
||||
#define ROSC_DORMANT_OFFSET _u(0x00000010)
|
||||
#define ROSC_DORMANT_BITS _u(0xffffffff)
|
||||
|
|
|
|||
|
|
@ -86,7 +86,7 @@
|
|||
// In addition the following custom extensions are configured:
|
||||
// Xh3bm, Xh3power, Xh3irq, Xh3pmpm
|
||||
#define RVCSR_MISA_OFFSET _u(0x00000301)
|
||||
#define RVCSR_MISA_BITS _u(0xc0901107)
|
||||
#define RVCSR_MISA_BITS _u(0xc0b511bf)
|
||||
#define RVCSR_MISA_RESET _u(0x40901105)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RVCSR_MISA_MXL
|
||||
|
|
@ -106,6 +106,14 @@
|
|||
#define RVCSR_MISA_X_LSB _u(23)
|
||||
#define RVCSR_MISA_X_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RVCSR_MISA_V
|
||||
// Description : Vector extension (not implemented).
|
||||
#define RVCSR_MISA_V_RESET _u(0x0)
|
||||
#define RVCSR_MISA_V_BITS _u(0x00200000)
|
||||
#define RVCSR_MISA_V_MSB _u(21)
|
||||
#define RVCSR_MISA_V_LSB _u(21)
|
||||
#define RVCSR_MISA_V_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RVCSR_MISA_U
|
||||
// Description : Value of 1 indicates U-mode is implemented.
|
||||
#define RVCSR_MISA_U_RESET _u(0x1)
|
||||
|
|
@ -114,6 +122,22 @@
|
|||
#define RVCSR_MISA_U_LSB _u(20)
|
||||
#define RVCSR_MISA_U_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RVCSR_MISA_S
|
||||
// Description : Supervisor extension (not implemented).
|
||||
#define RVCSR_MISA_S_RESET _u(0x0)
|
||||
#define RVCSR_MISA_S_BITS _u(0x00040000)
|
||||
#define RVCSR_MISA_S_MSB _u(18)
|
||||
#define RVCSR_MISA_S_LSB _u(18)
|
||||
#define RVCSR_MISA_S_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RVCSR_MISA_Q
|
||||
// Description : Quad-precision floating point extension (not implemented).
|
||||
#define RVCSR_MISA_Q_RESET _u(0x0)
|
||||
#define RVCSR_MISA_Q_BITS _u(0x00010000)
|
||||
#define RVCSR_MISA_Q_MSB _u(16)
|
||||
#define RVCSR_MISA_Q_LSB _u(16)
|
||||
#define RVCSR_MISA_Q_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RVCSR_MISA_M
|
||||
// Description : Value of 1 indicates the M extension (integer multiply/divide)
|
||||
// is implemented.
|
||||
|
|
@ -132,6 +156,39 @@
|
|||
#define RVCSR_MISA_I_LSB _u(8)
|
||||
#define RVCSR_MISA_I_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RVCSR_MISA_H
|
||||
// Description : Hypervisor extension (not implemented, I agree it would be
|
||||
// pretty cool on a microcontroller through).
|
||||
#define RVCSR_MISA_H_RESET _u(0x0)
|
||||
#define RVCSR_MISA_H_BITS _u(0x00000080)
|
||||
#define RVCSR_MISA_H_MSB _u(7)
|
||||
#define RVCSR_MISA_H_LSB _u(7)
|
||||
#define RVCSR_MISA_H_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RVCSR_MISA_F
|
||||
// Description : Single-precision floating point extension (not implemented).
|
||||
#define RVCSR_MISA_F_RESET _u(0x0)
|
||||
#define RVCSR_MISA_F_BITS _u(0x00000020)
|
||||
#define RVCSR_MISA_F_MSB _u(5)
|
||||
#define RVCSR_MISA_F_LSB _u(5)
|
||||
#define RVCSR_MISA_F_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RVCSR_MISA_E
|
||||
// Description : RV32E/64E base ISA (not implemented).
|
||||
#define RVCSR_MISA_E_RESET _u(0x0)
|
||||
#define RVCSR_MISA_E_BITS _u(0x00000010)
|
||||
#define RVCSR_MISA_E_MSB _u(4)
|
||||
#define RVCSR_MISA_E_LSB _u(4)
|
||||
#define RVCSR_MISA_E_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RVCSR_MISA_D
|
||||
// Description : Double-precision floating point extension (not implemented).
|
||||
#define RVCSR_MISA_D_RESET _u(0x0)
|
||||
#define RVCSR_MISA_D_BITS _u(0x00000008)
|
||||
#define RVCSR_MISA_D_MSB _u(3)
|
||||
#define RVCSR_MISA_D_LSB _u(3)
|
||||
#define RVCSR_MISA_D_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RVCSR_MISA_C
|
||||
// Description : Value of 1 indicates the C extension (compressed instructions)
|
||||
// is implemented.
|
||||
|
|
@ -207,7 +264,7 @@
|
|||
// Description : Timer interrupt enable. The processor transfers to the timer
|
||||
// interrupt vector when `mie.mtie`, `mip.mtip` and `mstatus.mie`
|
||||
// are all 1, unless a software or external interrupt request is
|
||||
// also valid at this time.
|
||||
// also both pending and enabled at this time.
|
||||
#define RVCSR_MIE_MTIE_RESET _u(0x0)
|
||||
#define RVCSR_MIE_MTIE_BITS _u(0x00000080)
|
||||
#define RVCSR_MIE_MTIE_MSB _u(7)
|
||||
|
|
@ -216,9 +273,9 @@
|
|||
// -----------------------------------------------------------------------------
|
||||
// Field : RVCSR_MIE_MSIE
|
||||
// Description : Software interrupt enable. The processor transfers to the
|
||||
// software interrupt vector `mie.msie`, `mip.msip` and
|
||||
// software interrupt vector when `mie.msie`, `mip.msip` and
|
||||
// `mstatus.mie` are all 1, unless an external interrupt request
|
||||
// is also valid at this time.
|
||||
// is also both pending and enabled at this time.
|
||||
#define RVCSR_MIE_MSIE_RESET _u(0x0)
|
||||
#define RVCSR_MIE_MSIE_BITS _u(0x00000008)
|
||||
#define RVCSR_MIE_MSIE_MSB _u(3)
|
||||
|
|
@ -336,7 +393,7 @@
|
|||
#define RVCSR_MENVCFGH_RESET _u(0x00000000)
|
||||
#define RVCSR_MENVCFGH_MSB _u(31)
|
||||
#define RVCSR_MENVCFGH_LSB _u(0)
|
||||
#define RVCSR_MENVCFGH_ACCESS "RW"
|
||||
#define RVCSR_MENVCFGH_ACCESS "-"
|
||||
// =============================================================================
|
||||
// Register : RVCSR_MCOUNTINHIBIT
|
||||
// Description : Count inhibit register for `mcycle`/`minstret`
|
||||
|
|
@ -732,7 +789,7 @@
|
|||
// Description : Timer interrupt pending. The processor transfers to the timer
|
||||
// interrupt vector when `mie.mtie`, `mip.mtip` and `mstatus.mie`
|
||||
// are all 1, unless a software or external interrupt request is
|
||||
// also valid at this time.
|
||||
// also both pending and enabled at this time.
|
||||
#define RVCSR_MIP_MTIP_RESET _u(0x0)
|
||||
#define RVCSR_MIP_MTIP_BITS _u(0x00000080)
|
||||
#define RVCSR_MIP_MTIP_MSB _u(7)
|
||||
|
|
@ -741,9 +798,9 @@
|
|||
// -----------------------------------------------------------------------------
|
||||
// Field : RVCSR_MIP_MSIP
|
||||
// Description : Software interrupt pending. The processor transfers to the
|
||||
// software interrupt vector `mie.msie`, `mip.msip` and
|
||||
// software interrupt vector when `mie.msie`, `mip.msip` and
|
||||
// `mstatus.mie` are all 1, unless an external interrupt request
|
||||
// is also valid at this time.
|
||||
// is also both pending and enabled at this time.
|
||||
#define RVCSR_MIP_MSIP_RESET _u(0x0)
|
||||
#define RVCSR_MIP_MSIP_BITS _u(0x00000008)
|
||||
#define RVCSR_MIP_MSIP_MSB _u(3)
|
||||
|
|
@ -3099,14 +3156,18 @@
|
|||
#define RVCSR_MVENDORID_RESET _u(0x00000000)
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RVCSR_MVENDORID_BANK
|
||||
#define RVCSR_MVENDORID_BANK_RESET "-"
|
||||
// Description : Value of 9 indicates 9 continuation codes, which is JEP106 bank
|
||||
// 10.
|
||||
#define RVCSR_MVENDORID_BANK_RESET _u(0x0000009)
|
||||
#define RVCSR_MVENDORID_BANK_BITS _u(0xffffff80)
|
||||
#define RVCSR_MVENDORID_BANK_MSB _u(31)
|
||||
#define RVCSR_MVENDORID_BANK_LSB _u(7)
|
||||
#define RVCSR_MVENDORID_BANK_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : RVCSR_MVENDORID_OFFSET
|
||||
#define RVCSR_MVENDORID_OFFSET_RESET "-"
|
||||
// Description : ID 0x13 in bank 10 is the JEP106 ID for Raspberry Pi Ltd, the
|
||||
// vendor of RP2350.
|
||||
#define RVCSR_MVENDORID_OFFSET_RESET _u(0x13)
|
||||
#define RVCSR_MVENDORID_OFFSET_BITS _u(0x0000007f)
|
||||
#define RVCSR_MVENDORID_OFFSET_MSB _u(6)
|
||||
#define RVCSR_MVENDORID_OFFSET_LSB _u(0)
|
||||
|
|
@ -3122,10 +3183,11 @@
|
|||
#define RVCSR_MARCHID_ACCESS "RO"
|
||||
// =============================================================================
|
||||
// Register : RVCSR_MIMPID
|
||||
// Description : Implementation ID
|
||||
// Description : Implementation ID. On RP2350 this reads as 0x86fc4e3f, which is
|
||||
// release v1.0-rc1 of Hazard3.
|
||||
#define RVCSR_MIMPID_OFFSET _u(0x00000f13)
|
||||
#define RVCSR_MIMPID_BITS _u(0xffffffff)
|
||||
#define RVCSR_MIMPID_RESET "-"
|
||||
#define RVCSR_MIMPID_RESET _u(0x86fc4e3f)
|
||||
#define RVCSR_MIMPID_MSB _u(31)
|
||||
#define RVCSR_MIMPID_LSB _u(0)
|
||||
#define RVCSR_MIMPID_ACCESS "RO"
|
||||
|
|
|
|||
|
|
@ -255,7 +255,10 @@
|
|||
// =============================================================================
|
||||
// Register : SYSCFG_AUXCTRL
|
||||
// Description : Auxiliary system control register
|
||||
// * Bits 7:2: Reserved
|
||||
// * Bits 7:3: Reserved
|
||||
//
|
||||
// * Bit 2: Set to mask OTP power analogue power supply detection
|
||||
// from resetting OTP controller and PSM
|
||||
//
|
||||
// * Bit 1: When clear, the LPOSC output is XORed into the TRNG
|
||||
// ROSC output as an additional, uncorrelated entropy source. When
|
||||
|
|
|
|||
|
|
@ -36,8 +36,7 @@
|
|||
#define TICKS_PROC0_CTRL_ENABLE_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : TICKS_PROC0_CYCLES
|
||||
// Description : None
|
||||
// Total number of clk_tick cycles before the next tick.
|
||||
// Description : Total number of clk_tick cycles before the next tick.
|
||||
#define TICKS_PROC0_CYCLES_OFFSET _u(0x00000004)
|
||||
#define TICKS_PROC0_CYCLES_BITS _u(0x000001ff)
|
||||
#define TICKS_PROC0_CYCLES_RESET _u(0x00000000)
|
||||
|
|
@ -46,8 +45,7 @@
|
|||
#define TICKS_PROC0_CYCLES_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : TICKS_PROC0_COUNT
|
||||
// Description : None
|
||||
// Count down timer: the remaining number clk_tick cycles before
|
||||
// Description : Count down timer: the remaining number clk_tick cycles before
|
||||
// the next tick is generated.
|
||||
#define TICKS_PROC0_COUNT_OFFSET _u(0x00000008)
|
||||
#define TICKS_PROC0_COUNT_BITS _u(0x000001ff)
|
||||
|
|
@ -79,8 +77,7 @@
|
|||
#define TICKS_PROC1_CTRL_ENABLE_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : TICKS_PROC1_CYCLES
|
||||
// Description : None
|
||||
// Total number of clk_tick cycles before the next tick.
|
||||
// Description : Total number of clk_tick cycles before the next tick.
|
||||
#define TICKS_PROC1_CYCLES_OFFSET _u(0x00000010)
|
||||
#define TICKS_PROC1_CYCLES_BITS _u(0x000001ff)
|
||||
#define TICKS_PROC1_CYCLES_RESET _u(0x00000000)
|
||||
|
|
@ -89,8 +86,7 @@
|
|||
#define TICKS_PROC1_CYCLES_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : TICKS_PROC1_COUNT
|
||||
// Description : None
|
||||
// Count down timer: the remaining number clk_tick cycles before
|
||||
// Description : Count down timer: the remaining number clk_tick cycles before
|
||||
// the next tick is generated.
|
||||
#define TICKS_PROC1_COUNT_OFFSET _u(0x00000014)
|
||||
#define TICKS_PROC1_COUNT_BITS _u(0x000001ff)
|
||||
|
|
@ -122,8 +118,7 @@
|
|||
#define TICKS_TIMER0_CTRL_ENABLE_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : TICKS_TIMER0_CYCLES
|
||||
// Description : None
|
||||
// Total number of clk_tick cycles before the next tick.
|
||||
// Description : Total number of clk_tick cycles before the next tick.
|
||||
#define TICKS_TIMER0_CYCLES_OFFSET _u(0x0000001c)
|
||||
#define TICKS_TIMER0_CYCLES_BITS _u(0x000001ff)
|
||||
#define TICKS_TIMER0_CYCLES_RESET _u(0x00000000)
|
||||
|
|
@ -132,8 +127,7 @@
|
|||
#define TICKS_TIMER0_CYCLES_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : TICKS_TIMER0_COUNT
|
||||
// Description : None
|
||||
// Count down timer: the remaining number clk_tick cycles before
|
||||
// Description : Count down timer: the remaining number clk_tick cycles before
|
||||
// the next tick is generated.
|
||||
#define TICKS_TIMER0_COUNT_OFFSET _u(0x00000020)
|
||||
#define TICKS_TIMER0_COUNT_BITS _u(0x000001ff)
|
||||
|
|
@ -165,8 +159,7 @@
|
|||
#define TICKS_TIMER1_CTRL_ENABLE_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : TICKS_TIMER1_CYCLES
|
||||
// Description : None
|
||||
// Total number of clk_tick cycles before the next tick.
|
||||
// Description : Total number of clk_tick cycles before the next tick.
|
||||
#define TICKS_TIMER1_CYCLES_OFFSET _u(0x00000028)
|
||||
#define TICKS_TIMER1_CYCLES_BITS _u(0x000001ff)
|
||||
#define TICKS_TIMER1_CYCLES_RESET _u(0x00000000)
|
||||
|
|
@ -175,8 +168,7 @@
|
|||
#define TICKS_TIMER1_CYCLES_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : TICKS_TIMER1_COUNT
|
||||
// Description : None
|
||||
// Count down timer: the remaining number clk_tick cycles before
|
||||
// Description : Count down timer: the remaining number clk_tick cycles before
|
||||
// the next tick is generated.
|
||||
#define TICKS_TIMER1_COUNT_OFFSET _u(0x0000002c)
|
||||
#define TICKS_TIMER1_COUNT_BITS _u(0x000001ff)
|
||||
|
|
@ -208,8 +200,7 @@
|
|||
#define TICKS_WATCHDOG_CTRL_ENABLE_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : TICKS_WATCHDOG_CYCLES
|
||||
// Description : None
|
||||
// Total number of clk_tick cycles before the next tick.
|
||||
// Description : Total number of clk_tick cycles before the next tick.
|
||||
#define TICKS_WATCHDOG_CYCLES_OFFSET _u(0x00000034)
|
||||
#define TICKS_WATCHDOG_CYCLES_BITS _u(0x000001ff)
|
||||
#define TICKS_WATCHDOG_CYCLES_RESET _u(0x00000000)
|
||||
|
|
@ -218,8 +209,7 @@
|
|||
#define TICKS_WATCHDOG_CYCLES_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : TICKS_WATCHDOG_COUNT
|
||||
// Description : None
|
||||
// Count down timer: the remaining number clk_tick cycles before
|
||||
// Description : Count down timer: the remaining number clk_tick cycles before
|
||||
// the next tick is generated.
|
||||
#define TICKS_WATCHDOG_COUNT_OFFSET _u(0x00000038)
|
||||
#define TICKS_WATCHDOG_COUNT_BITS _u(0x000001ff)
|
||||
|
|
@ -251,8 +241,7 @@
|
|||
#define TICKS_RISCV_CTRL_ENABLE_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : TICKS_RISCV_CYCLES
|
||||
// Description : None
|
||||
// Total number of clk_tick cycles before the next tick.
|
||||
// Description : Total number of clk_tick cycles before the next tick.
|
||||
#define TICKS_RISCV_CYCLES_OFFSET _u(0x00000040)
|
||||
#define TICKS_RISCV_CYCLES_BITS _u(0x000001ff)
|
||||
#define TICKS_RISCV_CYCLES_RESET _u(0x00000000)
|
||||
|
|
@ -261,8 +250,7 @@
|
|||
#define TICKS_RISCV_CYCLES_ACCESS "RW"
|
||||
// =============================================================================
|
||||
// Register : TICKS_RISCV_COUNT
|
||||
// Description : None
|
||||
// Count down timer: the remaining number clk_tick cycles before
|
||||
// Description : Count down timer: the remaining number clk_tick cycles before
|
||||
// the next tick is generated.
|
||||
#define TICKS_RISCV_COUNT_OFFSET _u(0x00000044)
|
||||
#define TICKS_RISCV_COUNT_BITS _u(0x000001ff)
|
||||
|
|
|
|||
|
|
@ -1082,13 +1082,14 @@
|
|||
#define USB_SIE_STATUS_SPEED_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : USB_SIE_STATUS_SUSPENDED
|
||||
// Description : Bus in suspended state. Valid for device. Device will go into
|
||||
// suspend if neither Keep Alive / SOF frames are enabled.
|
||||
// Description : Bus in suspended state. Valid for device and host. Host and
|
||||
// device will go into suspend if neither Keep Alive / SOF frames
|
||||
// are enabled.
|
||||
#define USB_SIE_STATUS_SUSPENDED_RESET _u(0x0)
|
||||
#define USB_SIE_STATUS_SUSPENDED_BITS _u(0x00000010)
|
||||
#define USB_SIE_STATUS_SUSPENDED_MSB _u(4)
|
||||
#define USB_SIE_STATUS_SUSPENDED_LSB _u(4)
|
||||
#define USB_SIE_STATUS_SUSPENDED_ACCESS "WC"
|
||||
#define USB_SIE_STATUS_SUSPENDED_ACCESS "RO"
|
||||
// -----------------------------------------------------------------------------
|
||||
// Field : USB_SIE_STATUS_LINE_STATE
|
||||
// Description : USB bus line state
|
||||
|
|
|
|||
|
|
@ -137,14 +137,14 @@ typedef struct {
|
|||
|
||||
_REG_(POWMAN_STATE_OFFSET) // POWMAN_STATE
|
||||
// This register controls the power state of the 4 power domains
|
||||
// 0x00002000 [13] CHANGING (0)
|
||||
// 0x00001000 [12] WAITING (0)
|
||||
// 0x00000800 [11] BAD_HW_REQ (0) Bad hardware initiated state request
|
||||
// 0x00000400 [10] BAD_SW_REQ (0) Bad software initiated state request
|
||||
// 0x00000200 [9] PWRUP_WHILE_WAITING (0) Request ignored because of a pending pwrup request
|
||||
// 0x00000100 [8] REQ_IGNORED (0)
|
||||
// 0x000000f0 [7:4] REQ (0x0)
|
||||
// 0x0000000f [3:0] CURRENT (0xf)
|
||||
// 0x00002000 [13] CHANGING (0) Indicates a power state change is in progress
|
||||
// 0x00001000 [12] WAITING (0) Indicates the power manager has received a state change...
|
||||
// 0x00000800 [11] BAD_HW_REQ (0) Invalid hardware initiated state request, power up...
|
||||
// 0x00000400 [10] BAD_SW_REQ (0) Invalid software initiated state request ignored
|
||||
// 0x00000200 [9] PWRUP_WHILE_WAITING (0) Indicates that a power state change request was ignored...
|
||||
// 0x00000100 [8] REQ_IGNORED (0) Indicates that a software state change request was...
|
||||
// 0x000000f0 [7:4] REQ (0x0) This is written by software or hardware to request a new...
|
||||
// 0x0000000f [3:0] CURRENT (0xf) Indicates the current power state
|
||||
io_rw_32 state;
|
||||
|
||||
_REG_(POWMAN_POW_FASTDIV_OFFSET) // POWMAN_POW_FASTDIV
|
||||
|
|
|
|||
|
|
@ -35,9 +35,9 @@ typedef struct {
|
|||
// 0xffff0000 [31:16] PASSWD (0x0000) Set to 0x9696 to apply the settings +
|
||||
// 0x00007000 [14:12] DS3 (0x0) Stage 3 drive strength
|
||||
// 0x00000700 [10:8] DS2 (0x0) Stage 2 drive strength
|
||||
// 0x00000080 [7] DS1_RANDOM (0) Randomises the stage 1 drive strength
|
||||
// 0x00000080 [7] DS1_RANDOM (1) Randomises the stage 1 drive strength
|
||||
// 0x00000070 [6:4] DS1 (0x0) Stage 1 drive strength
|
||||
// 0x00000008 [3] DS0_RANDOM (0) Randomises the stage 0 drive strength
|
||||
// 0x00000008 [3] DS0_RANDOM (1) Randomises the stage 0 drive strength
|
||||
// 0x00000007 [2:0] DS0 (0x0) Stage 0 drive strength
|
||||
io_rw_32 freqa;
|
||||
|
||||
|
|
|
|||
|
|
@ -72,7 +72,7 @@ typedef struct {
|
|||
|
||||
_REG_(SYSCFG_AUXCTRL_OFFSET) // SYSCFG_AUXCTRL
|
||||
// Auxiliary system control register
|
||||
// 0x000000ff [7:0] AUXCTRL (0x00) * Bits 7:2: Reserved
|
||||
// 0x000000ff [7:0] AUXCTRL (0x00) * Bits 7:3: Reserved
|
||||
io_rw_32 auxctrl;
|
||||
} syscfg_hw_t;
|
||||
|
||||
|
|
|
|||
|
|
@ -4,10 +4,10 @@
|
|||
* @file src/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include/RP2350.h
|
||||
* @brief CMSIS HeaderFile
|
||||
* @version 0.1
|
||||
* @date Thu Aug 8 04:04:02 2024
|
||||
* @note Generated by SVDConv V3.3.47
|
||||
* from File 'src/rp2_common/cmsis/../../rp2350/hardware_regs/RP2350.svd',
|
||||
* last modified on Thu Aug 8 03:59:33 2024
|
||||
* @date Mon Jul 28 11:37:41 2025
|
||||
* @note Generated by SVDConv V3.3.45
|
||||
* from File 'src/rp2350/hardware_regs/RP2350.svd',
|
||||
* last modified on Mon Jul 28 11:35:05 2025
|
||||
*/
|
||||
|
||||
|
||||
|
|
@ -2028,7 +2028,7 @@ typedef struct { /*!< POWMAN Structure
|
|||
ignore the power down requests. To do nothing would risk
|
||||
entering an unrecoverable lock-up state. Invalid requests
|
||||
are: any combination of power up and power down requests
|
||||
any request that results in swcore boing powered and xip
|
||||
any request that results in swcore being powered and xip
|
||||
unpowered If the request is to power down the switched-core
|
||||
domain then POWMAN_STATE_WAITING stays active until the
|
||||
processors halt. During this time the POWMAN_STATE_REQ
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue