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Change div_int_frac methods to be suffixed by the number of bits of fraction e.g. div_int_frac8 (#1926)
This commit is contained in:
Graham Sanderson
GitHub
parent
f9eb48bd91
commit
06b7c1cf9e
7 changed files with 139 additions and 59 deletions
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@ -228,7 +228,7 @@ void clocks_enable_resus(resus_callback_t resus_callback) {
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clocks_hw->resus.ctrl = CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_BITS | timeout;
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}
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void clock_gpio_init_int_frac(uint gpio, uint src, uint32_t div_int, uint8_t div_frac) {
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void clock_gpio_init_int_frac16(uint gpio, uint src, uint32_t div_int, uint16_t div_frac16) {
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// Bit messy but it's as much code to loop through a lookup
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// table. The sources for each gpout generators are the same
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// so just call with the sources from GP0
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@ -245,10 +245,17 @@ void clock_gpio_init_int_frac(uint gpio, uint src, uint32_t div_int, uint8_t div
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invalid_params_if(HARDWARE_CLOCKS, true);
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}
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invalid_params_if(HARDWARE_CLOCKS, div_int >> (CLOCKS_CLK_GPOUT0_DIV_INT_MSB - CLOCKS_CLK_GPOUT0_DIV_INT_LSB + 1));
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// Set up the gpclk generator
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clocks_hw->clk[gpclk].ctrl = (src << CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB) |
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CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS;
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clocks_hw->clk[gpclk].div = (div_int << CLOCKS_CLK_GPOUT0_DIV_INT_LSB) | div_frac;
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#if CLOCKS_CLK_GPOUT0_DIV_FRAC_MSB - CLOCKS_CLK_GPOUT0_DIV_FRAC_LSB == 15
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clocks_hw->clk[gpclk].div = (div_int << CLOCKS_CLK_GPOUT0_DIV_INT_LSB) | (div_frac16 << CLOCKS_CLK_GPOUT0_DIV_FRAC_LSB);
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#elif CLOCKS_CLK_GPOUT0_DIV_FRAC_MSB - CLOCKS_CLK_GPOUT0_DIV_FRAC_LSB == 7
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clocks_hw->clk[gpclk].div = (div_int << CLOCKS_CLK_GPOUT0_DIV_INT_LSB) | ((div_frac16>>8u) << CLOCKS_CLK_GPOUT0_DIV_FRAC_LSB);
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#else
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#error unsupported number of fractional bits
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#endif
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// Set gpio pin to gpclock function
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gpio_set_function(gpio, GPIO_FUNC_GPCK);
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@ -353,10 +353,29 @@ void clocks_enable_resus(resus_callback_t resus_callback);
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*
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* \param gpio The GPIO pin to output the clock to. Valid GPIOs are: 21, 23, 24, 25. These GPIOs are connected to the GPOUT0-3 clock generators.
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* \param src The source clock. See the register field CLOCKS_CLK_GPOUT0_CTRL_AUXSRC for a full list. The list is the same for each GPOUT clock generator.
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* \param div_int The integer part of the value to divide the source clock by. This is useful to not overwhelm the GPIO pin with a fast clock. this is in range of 1..2^24-1.
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* \param div_frac The fractional part of the value to divide the source clock by. This is in range of 0..255 (/256).
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* \param div_int The integer part of the value to divide the source clock by. This is useful to not overwhelm the GPIO pin with a fast clock. This is in range of 1..2^24-1 on RP2040
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* and 1..2^16-1 on RP2350
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* \param div_frac16 The fractional part of the value to divide the source clock by. This is in range of 0..65535 (/65536).
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*/
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void clock_gpio_init_int_frac(uint gpio, uint src, uint32_t div_int, uint8_t div_frac);
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void clock_gpio_init_int_frac16(uint gpio, uint src, uint32_t div_int, uint16_t div_frac16);
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/*! \brief Output an optionally divided clock to the specified gpio pin.
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* \ingroup hardware_clocks
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*
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* \param gpio The GPIO pin to output the clock to. Valid GPIOs are: 21, 23, 24, 25. These GPIOs are connected to the GPOUT0-3 clock generators.
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* \param src The source clock. See the register field CLOCKS_CLK_GPOUT0_CTRL_AUXSRC for a full list. The list is the same for each GPOUT clock generator.
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* \param div_int The integer part of the value to divide the source clock by. This is useful to not overwhelm the GPIO pin with a fast clock. This is in range of 1..2^24-1 on RP2040
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* and 1..2^16-1 on RP2350
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* \param div_frac8 The fractional part of the value to divide the source clock by. This is in range of 0..255 (/256).
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*/
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static inline void clock_gpio_init_int_frac8(uint gpio, uint src, uint32_t div_int, uint8_t div_frac8) {
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return clock_gpio_init_int_frac16(gpio, src, div_int, (uint16_t)(div_frac8 << 8u));
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}
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// backwards compatibility
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static inline void clock_gpio_init_int_frac(uint gpio, uint src, uint32_t div_int, uint8_t div_frac8) {
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return clock_gpio_init_int_frac8(gpio, src, div_int, div_frac8);
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}
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/*! \brief Output an optionally divided clock to the specified gpio pin.
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* \ingroup hardware_clocks
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@ -368,8 +387,15 @@ void clock_gpio_init_int_frac(uint gpio, uint src, uint32_t div_int, uint8_t div
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static inline void clock_gpio_init(uint gpio, uint src, float div)
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{
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uint div_int = (uint)div;
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uint8_t frac = (uint8_t)((div - (float)div_int) * (1u << CLOCKS_CLK_GPOUT0_DIV_INT_LSB));
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clock_gpio_init_int_frac(gpio, src, div_int, frac);
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#if CLOCKS_CLK_GPOUT0_DIV_FRAC_MSB - CLOCKS_CLK_GPOUT0_DIV_FRAC_LSB == 15
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uint16_t frac = (uint16_t)((div - (float)div_int) * (1u << 16));
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clock_gpio_init_int_frac16(gpio, src, div_int, frac);
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#elif CLOCKS_CLK_GPOUT0_DIV_FRAC_MSB - CLOCKS_CLK_GPOUT0_DIV_FRAC_LSB == 7
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uint8_t frac = (uint8_t)((div - (float)div_int) * (1u << 8));
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clock_gpio_init_int_frac8(gpio, src, div_int, frac);
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#else
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#error unsupported number of fractional bits
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#endif
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}
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/*! \brief Configure a clock to come from a gpio input
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@ -468,26 +468,44 @@ static inline void sm_config_set_sideset(pio_sm_config *c, uint bit_count, bool
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*
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* \param c Pointer to the configuration structure to modify
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* \param div_int Integer part of the divisor
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* \param div_frac Fractional part in 1/256ths
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* \param div_frac8 Fractional part in 1/256ths
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* \sa sm_config_set_clkdiv()
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*/
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static inline void sm_config_set_clkdiv_int_frac(pio_sm_config *c, uint16_t div_int, uint8_t div_frac) {
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invalid_params_if(HARDWARE_PIO, div_int == 0 && div_frac != 0);
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static inline void sm_config_set_clkdiv_int_frac8(pio_sm_config *c, uint32_t div_int, uint8_t div_frac8) {
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static_assert(PIO_SM0_CLKDIV_INT_MSB - PIO_SM0_CLKDIV_INT_LSB == 15, "");
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invalid_params_if(HARDWARE_PIO, div_int >> 16);
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invalid_params_if(HARDWARE_PIO, div_int == 0 && div_frac8 != 0);
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static_assert(PIO_SM0_CLKDIV_FRAC_MSB - PIO_SM0_CLKDIV_FRAC_LSB == 7, "");
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c->clkdiv =
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(((uint)div_frac) << PIO_SM0_CLKDIV_FRAC_LSB) |
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(((uint)div_frac8) << PIO_SM0_CLKDIV_FRAC_LSB) |
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(((uint)div_int) << PIO_SM0_CLKDIV_INT_LSB);
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}
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static inline void pio_calculate_clkdiv_from_float(float div, uint16_t *div_int, uint8_t *div_frac) {
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// backwards compatibility
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static inline void sm_config_set_clkdiv_int_frac(pio_sm_config *c, uint16_t div_int, uint8_t div_frac8) {
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sm_config_set_clkdiv_int_frac8(c, div_int, div_frac8);
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}
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static inline void pio_calculate_clkdiv8_from_float(float div, uint32_t *div_int, uint8_t *div_frac8) {
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valid_params_if(HARDWARE_PIO, div >= 1 && div <= 65536);
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*div_int = (uint16_t)div;
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// not a strictly necessary check, but if this changes, then this method should
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// probably no longer be used in favor of one with a larger fraction
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static_assert(PIO_SM0_CLKDIV_FRAC_MSB - PIO_SM0_CLKDIV_FRAC_LSB == 7, "");
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if (*div_int == 0) {
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*div_frac = 0;
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*div_frac8 = 0;
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} else {
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*div_frac = (uint8_t)((div - (float)*div_int) * (1u << 8u));
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*div_frac8 = (uint8_t)((div - (float)*div_int) * (1u << 8u));
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}
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}
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// backwards compatibility
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static inline void pio_calculate_clkdiv_from_float(float div, uint16_t *div_int16, uint8_t *div_frac8) {
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uint32_t div_int;
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pio_calculate_clkdiv8_from_float(div, &div_int, div_frac8);
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*div_int16 = (uint16_t) div_int;
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}
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/*! \brief Set the state machine clock divider (from a floating point value) in a state machine configuration
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* \ingroup sm_config
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*
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@ -504,10 +522,10 @@ static inline void pio_calculate_clkdiv_from_float(float div, uint16_t *div_int,
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* although it will depend on the use case.
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*/
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static inline void sm_config_set_clkdiv(pio_sm_config *c, float div) {
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uint16_t div_int;
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uint8_t div_frac;
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pio_calculate_clkdiv_from_float(div, &div_int, &div_frac);
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sm_config_set_clkdiv_int_frac(c, div_int, div_frac);
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uint32_t div_int;
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uint8_t div_frac8;
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pio_calculate_clkdiv8_from_float(div, &div_int, &div_frac8);
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sm_config_set_clkdiv_int_frac8(c, div_int, div_frac8);
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}
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/*! \brief Set the wrap addresses in a state machine configuration
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@ -664,7 +682,7 @@ static inline pio_sm_config pio_get_default_sm_config(void) {
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#if PICO_PIO_USE_GPIO_BASE
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c.pinhi = -1;
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#endif
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sm_config_set_clkdiv_int_frac(&c, 1, 0);
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sm_config_set_clkdiv_int_frac8(&c, 1, 0);
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sm_config_set_wrap(&c, 0, 31);
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sm_config_set_in_shift(&c, true, false, 32);
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sm_config_set_out_shift(&c, true, false, 32);
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@ -1643,17 +1661,25 @@ void pio_sm_drain_tx_fifo(PIO pio, uint sm);
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* \param pio The PIO instance; e.g. \ref pio0 or \ref pio1
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* \param sm State machine index (0..3)
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* \param div_int the integer part of the clock divider
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* \param div_frac the fractional part of the clock divider in 1/256s
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* \param div_frac8 the fractional part of the clock divider in 1/256s
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*/
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static inline void pio_sm_set_clkdiv_int_frac(PIO pio, uint sm, uint16_t div_int, uint8_t div_frac) {
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static inline void pio_sm_set_clkdiv_int_frac8(PIO pio, uint sm, uint32_t div_int, uint8_t div_frac8) {
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check_pio_param(pio);
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check_sm_param(sm);
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invalid_params_if(HARDWARE_PIO, div_int == 0 && div_frac != 0);
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static_assert(PIO_SM0_CLKDIV_INT_MSB - PIO_SM0_CLKDIV_INT_LSB == 15, "");
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invalid_params_if(HARDWARE_PIO, div_int >> 16);
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invalid_params_if(HARDWARE_PIO, div_int == 0 && div_frac8 != 0);
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static_assert(PIO_SM0_CLKDIV_FRAC_MSB - PIO_SM0_CLKDIV_FRAC_LSB == 7, "");
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pio->sm[sm].clkdiv =
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(((uint)div_frac) << PIO_SM0_CLKDIV_FRAC_LSB) |
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(((uint)div_frac8) << PIO_SM0_CLKDIV_FRAC_LSB) |
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(((uint)div_int) << PIO_SM0_CLKDIV_INT_LSB);
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}
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// backwards compatibility
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static inline void pio_sm_set_clkdiv_int_frac(PIO pio, uint sm, uint16_t div_int, uint8_t div_frac8) {
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pio_sm_set_clkdiv_int_frac8(pio, sm, div_int, div_frac8);
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}
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/*! \brief set the current clock divider for a state machine
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* \ingroup hardware_pio
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*
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@ -1664,10 +1690,10 @@ static inline void pio_sm_set_clkdiv_int_frac(PIO pio, uint sm, uint16_t div_int
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static inline void pio_sm_set_clkdiv(PIO pio, uint sm, float div) {
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check_pio_param(pio);
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check_sm_param(sm);
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uint16_t div_int;
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uint8_t div_frac;
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pio_calculate_clkdiv_from_float(div, &div_int, &div_frac);
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pio_sm_set_clkdiv_int_frac(pio, sm, div_int, div_frac);
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uint32_t div_int;
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uint8_t div_frac8;
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pio_calculate_clkdiv8_from_float(div, &div_int, &div_frac8);
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pio_sm_set_clkdiv_int_frac8(pio, sm, div_int, div_frac8);
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}
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/*! \brief Clear a state machine's TX and RX FIFOs
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@ -162,32 +162,38 @@ static inline void pwm_config_set_clkdiv(pwm_config *c, float div) {
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* \ingroup hardware_pwm
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*
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* \param c PWM configuration struct to modify
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* \param integer 8 bit integer part of the clock divider. Must be greater than or equal to 1.
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* \param fract 4 bit fractional part of the clock divider
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* \param div_int 8 bit integer part of the clock divider. Must be greater than or equal to 1.
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* \param div_frac4 4 bit fractional part of the clock divider
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*
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* If the divide mode is free-running, the PWM counter runs at clk_sys / div.
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* Otherwise, the divider reduces the rate of events seen on the B pin input (level or edge)
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* before passing them on to the PWM counter.
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*/
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static inline void pwm_config_set_clkdiv_int_frac(pwm_config *c, uint8_t integer, uint8_t fract) {
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valid_params_if(HARDWARE_PWM, integer >= 1);
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valid_params_if(HARDWARE_PWM, fract < 16);
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c->div = (((uint)integer) << PWM_CH0_DIV_INT_LSB) | (((uint)fract) << PWM_CH0_DIV_FRAC_LSB);
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static inline void pwm_config_set_clkdiv_int_frac4(pwm_config *c, uint32_t div_int, uint8_t div_frac4) {
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static_assert(PWM_CH0_DIV_INT_MSB - PWM_CH0_DIV_INT_LSB == 7, "");
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valid_params_if(HARDWARE_PWM, div_int >= 1 && div_int < 256);
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static_assert(PWM_CH0_DIV_FRAC_MSB - PWM_CH0_DIV_FRAC_LSB == 3, "");
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valid_params_if(HARDWARE_PWM, div_frac4 < 16);
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c->div = (((uint)div_int) << PWM_CH0_DIV_INT_LSB) | (((uint)div_frac4) << PWM_CH0_DIV_FRAC_LSB);
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}
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// backwards compatibility
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static inline void pwm_config_set_clkdiv_int_frac(pwm_config *c, uint8_t div_int, uint8_t div_frac4) {
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pwm_config_set_clkdiv_int_frac4(c, div_int, div_frac4);
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}
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/** \brief Set PWM clock divider in a PWM configuration
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* \ingroup hardware_pwm
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*
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* \param c PWM configuration struct to modify
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* \param div Integer value to reduce counting rate by. Must be greater than or equal to 1.
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* \param div_int Integer value to reduce counting rate by. Must be greater than or equal to 1 and less than 256.
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*
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* If the divide mode is free-running, the PWM counter runs at clk_sys / div.
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* Otherwise, the divider reduces the rate of events seen on the B pin input (level or edge)
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* before passing them on to the PWM counter.
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*/
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static inline void pwm_config_set_clkdiv_int(pwm_config *c, uint div) {
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valid_params_if(HARDWARE_PWM, div >= 1 && div < 256);
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pwm_config_set_clkdiv_int_frac(c, (uint8_t)div, 0);
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static inline void pwm_config_set_clkdiv_int(pwm_config *c, uint32_t div_int) {
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pwm_config_set_clkdiv_int_frac4(c, div_int, 0);
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}
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/** \brief Set PWM counting mode in a PWM configuration
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@ -427,14 +433,20 @@ static inline void pwm_retard_count(uint slice_num) {
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* Set the clock divider. Counter increment will be on sysclock divided by this value, taking into account the gating.
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*
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* \param slice_num PWM slice number
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* \param integer 8 bit integer part of the clock divider
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* \param fract 4 bit fractional part of the clock divider
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* \param div_int 8 bit integer part of the clock divider
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* \param div_frac4 4 bit fractional part of the clock divider
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*/
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static inline void pwm_set_clkdiv_int_frac(uint slice_num, uint8_t integer, uint8_t fract) {
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static inline void pwm_set_clkdiv_int_frac4(uint slice_num, uint8_t div_int, uint8_t div_frac4) {
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check_slice_num_param(slice_num);
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valid_params_if(HARDWARE_PWM, integer >= 1);
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valid_params_if(HARDWARE_PWM, fract < 16);
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pwm_hw->slice[slice_num].div = (((uint)integer) << PWM_CH0_DIV_INT_LSB) | (((uint)fract) << PWM_CH0_DIV_FRAC_LSB);
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valid_params_if(HARDWARE_PWM, div_int >= 1);
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static_assert(PWM_CH0_DIV_FRAC_MSB - PWM_CH0_DIV_FRAC_LSB == 3, "");
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valid_params_if(HARDWARE_PWM, div_frac4 < 16);
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pwm_hw->slice[slice_num].div = (((uint)div_int) << PWM_CH0_DIV_INT_LSB) | (((uint)div_frac4) << PWM_CH0_DIV_FRAC_LSB);
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}
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// backwards compatibility
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static inline void pwm_set_clkdiv_int_frac(uint slice_num, uint8_t div_int, uint8_t div_frac4) {
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pwm_set_clkdiv_int_frac4(slice_num, div_int, div_frac4);
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}
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/** \brief Set PWM clock divider
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@ -450,7 +462,7 @@ static inline void pwm_set_clkdiv(uint slice_num, float divider) {
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valid_params_if(HARDWARE_PWM, divider >= 1.f && divider < 256.f);
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uint8_t i = (uint8_t)divider;
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uint8_t f = (uint8_t)((divider - i) * (0x01 << 4));
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pwm_set_clkdiv_int_frac(slice_num, i, f);
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pwm_set_clkdiv_int_frac4(slice_num, i, f);
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}
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/** \brief Set PWM output polarity
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@ -84,9 +84,9 @@ if (EXISTS ${PICO_CYW43_DRIVER_PATH}/${CYW43_DRIVER_TEST_FILE})
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# PICO_CMAKE_CONFIG: CYW43_PIO_CLOCK_DIV_INT, integer component of pio clock divider used for cyw43 comms, type=int, default=2, group=pico_cyw43_driver
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target_compile_definitions(cyw43_driver_picow INTERFACE CYW43_PIO_CLOCK_DIV_INT=${CYW43_PIO_CLOCK_DIV_INT})
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endif()
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||||
if (CYW43_PIO_CLOCK_DIV_FRAC)
|
||||
# PICO_CMAKE_CONFIG: CYW43_PIO_CLOCK_DIV_FRAC, fractional component of pio clock divider used for cyw43 comms, type=int, default=0, group=pico_cyw43_driver
|
||||
target_compile_definitions(cyw43_driver_picow INTERFACE CYW43_PIO_CLOCK_DIV_FRAC=${CYW43_PIO_CLOCK_DIV_FRAC})
|
||||
if (CYW43_PIO_CLOCK_DIV_FRAC8)
|
||||
# PICO_CMAKE_CONFIG: CYW43_PIO_CLOCK_DIV_FRAC, fractional component of pio clock divider used for cyw43 comms in range 0-255, type=int, default=0, group=pico_cyw43_driver
|
||||
target_compile_definitions(cyw43_driver_picow INTERFACE CYW43_PIO_CLOCK_DIV_FRAC8=${CYW43_PIO_CLOCK_DIV_FRAC8})
|
||||
endif()
|
||||
if (CYW43_PIO_CLOCK_DIV_DYNAMIC)
|
||||
# PICO_CMAKE_CONFIG: CYW43_PIO_CLOCK_DIV_DYNAMIC, flag used to enable dynamic pio clock divider API, type=bool, default=false, group=pico_cyw43_driver
|
||||
|
|
|
|||
|
|
@ -43,14 +43,14 @@ static_assert((CYW43_PIN_WL_DATA_OUT < 32 && CYW43_PIN_WL_DATA_IN < 32 && CYW43_
|
|||
|
||||
#if !CYW43_PIO_CLOCK_DIV_DYNAMIC
|
||||
#define cyw43_pio_clock_div_int CYW43_PIO_CLOCK_DIV_INT
|
||||
#define cyw43_pio_clock_div_frac CYW43_PIO_CLOCK_DIV_FRAC
|
||||
#define cyw43_pio_clock_div_frac8 CYW43_PIO_CLOCK_DIV_FRAC8
|
||||
#else
|
||||
static uint16_t cyw43_pio_clock_div_int = CYW43_PIO_CLOCK_DIV_INT;
|
||||
static uint8_t cyw43_pio_clock_div_frac = CYW43_PIO_CLOCK_DIV_FRAC;
|
||||
static uint32_t cyw43_pio_clock_div_int = CYW43_PIO_CLOCK_DIV_INT;
|
||||
static uint8_t cyw43_pio_clock_div_frac8 = CYW43_PIO_CLOCK_DIV_FRAC8;
|
||||
|
||||
void cyw43_set_pio_clock_divisor(uint16_t clock_div_int, uint8_t clock_div_frac) {
|
||||
void cyw43_set_pio_clkdiv_int_frac8(uint32_t clock_div_int, uint8_t clock_div_frac8) {
|
||||
cyw43_pio_clock_div_int = clock_div_int;
|
||||
cyw43_pio_clock_div_frac = clock_div_frac;
|
||||
cyw43_pio_clock_div_frac8 = clock_div_frac8;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -114,7 +114,7 @@ int cyw43_spi_init(cyw43_int_t *self) {
|
|||
}
|
||||
pio_sm_config config = SPI_PROGRAM_GET_DEFAULT_CONFIG_FUNC(bus_data->pio_offset);
|
||||
|
||||
sm_config_set_clkdiv_int_frac(&config, cyw43_pio_clock_div_int, cyw43_pio_clock_div_frac);
|
||||
sm_config_set_clkdiv_int_frac8(&config, cyw43_pio_clock_div_int, cyw43_pio_clock_div_frac8);
|
||||
hw_write_masked(&pads_bank0_hw->io[CYW43_PIN_WL_CLOCK],
|
||||
(uint)PADS_DRIVE_STRENGTH << PADS_BANK0_GPIO0_DRIVE_LSB,
|
||||
PADS_BANK0_GPIO0_DRIVE_BITS
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ void cyw43_driver_deinit(struct async_context *context);
|
|||
#define CYW43_PIO_CLOCK_DIV_DYNAMIC 0
|
||||
#endif
|
||||
|
||||
// PICO_CONFIG: CYW43_PIO_CLOCK_DIV_INT, Integer part of the clock divider for communication with the wireless chip, type=bool, default=2, group=pico_cyw43_driver
|
||||
// PICO_CONFIG: CYW43_PIO_CLOCK_DIV_INT, Integer part of the clock divider for communication with the wireless chip, type=int, default=2, group=pico_cyw43_driver
|
||||
#ifndef CYW43_PIO_CLOCK_DIV_INT
|
||||
// backwards compatibility using old define
|
||||
#ifdef CYW43_PIO_CLOCK_DIV
|
||||
|
|
@ -58,9 +58,13 @@ void cyw43_driver_deinit(struct async_context *context);
|
|||
#endif
|
||||
#endif
|
||||
|
||||
// PICO_CONFIG: CYW43_PIO_CLOCK_DIV_FRAC, Fractional part of the clock divider for communication with the wireless chip, type=bool, default=0, group=pico_cyw43_driver
|
||||
#ifndef CYW43_PIO_CLOCK_DIV_FRAC
|
||||
#define CYW43_PIO_CLOCK_DIV_FRAC 0
|
||||
// PICO_CONFIG: CYW43_PIO_CLOCK_DIV_FRAC8, Fractional part of the clock divider for communication with the wireless chip 0-255, type=int, min=0, max=255, default=0, group=pico_cyw43_driver
|
||||
#ifndef CYW43_PIO_CLOCK_DIV_FRAC8
|
||||
#ifdef CYW43_PIO_CLOCK_DIV_FRAC
|
||||
#define CYW43_PIO_CLOCK_DIV_FRAC8 CYW43_PIO_CLOCK_DIV_FRAC
|
||||
#else
|
||||
#define CYW43_PIO_CLOCK_DIV_FRAC8 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
// PICO_CONFIG: CYW43_PIN_WL_DYNAMIC, flag to indicate if cyw43 SPI pins can be changed at runtime, type=bool, advanced=true, group=pico_cyw43_driver
|
||||
|
|
@ -86,9 +90,14 @@ void cyw43_driver_deinit(struct async_context *context);
|
|||
* This function is only available if \ref CYW43_PIO_CLOCK_DIV_DYNAMIC is true
|
||||
*
|
||||
* \param clock_div_int Integer part of the divisor
|
||||
* \param clock_div_frac Fractional part in 1/256ths
|
||||
* \param clock_div_frac8 Fractional part in 1/256ths
|
||||
*/
|
||||
void cyw43_set_pio_clock_divisor(uint16_t clock_div_int, uint8_t clock_div_frac);
|
||||
void cyw43_set_pio_clkdiv_int_frac8(uint32_t clock_div_int, uint8_t clock_div_frac8);
|
||||
|
||||
// backwards compatibility
|
||||
static inline void cyw43_set_pio_clock_divisor(uint16_t clock_div_int, uint8_t clock_div_frac8) {
|
||||
return cyw43_set_pio_clkdiv_int_frac8(clock_div_int, clock_div_frac8);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if CYW43_PIN_WL_DYNAMIC
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue