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3adb820779
The RTL931x has next to its SPI flash controller a SPI master interface. It is connected to * SPI_CS#[1,0]: AH22 , AK22 (aka: GPIO 12, 11) * SPI_CLK: AL23 (aka: GPIO 8) * SPI_MISO: AM23 (aka: GPIO 9) * SPI_MOSI: AL22 (aka: GPIO 10) It is not the same as the SPI flash controller which uses pins: * SPI_CS#[1,0]: B24, A24 * SPI_SCLK: A23 * SPI_SDI/SIO0: B21 * SPO_SDO_SIO1: B21 * SPI_SIO2: A22 * SPI_SIO3: B22 * SPI_RSTN: B23 As shown above, the SPI master controller shares its pin with GPIO 8, 9, 10, 11, 12. In some upcoming devices (like the Plasma Cloud PSX28/ESX28), they will be used for SFP cage signaling. These pins must therefore be switched manually to the GPIO mode. The SPI_CTRL0 register provides all necessary configuration to enforce the GPIO mode of the pins. And until more requirements (and a correct driver) for the SPI master controller arise, it is therefore possible to use pinctrl-single to configure it using the devicetree. Previously the ethernet driver did configure the SPI master controller for 31.25 MHz. It is unknown for which kind of device this was originally made and what was actually connected there. But this manual write to the register conflicts potentially with the write of the pinctrl driver to the same register. Luckily, we don't need this SPI speed configuration in the ethernet driver. Still, to allow this device an easy migration, the `spi0-31mhz` configuration was already prepared. Signed-off-by: Sven Eckelmann <se@simonwunderlich.de> Link: https://github.com/openwrt/openwrt/pull/20263 Signed-off-by: Robert Marko <robimarko@gmail.com> |
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| .. | ||
| base-files | ||
| dts | ||
| files/firmware/rtl838x_phy | ||
| files-6.12 | ||
| image | ||
| patches-6.12 | ||
| profiles | ||
| rtl838x | ||
| rtl839x | ||
| rtl930x | ||
| rtl930x_nand | ||
| rtl931x | ||
| rtl931x_nand | ||
| Makefile | ||