mirror of
https://git.openwrt.org/openwrt/openwrt.git
synced 2026-03-14 23:09:45 +01:00
bce8432bbd
Sync the DTS with the version sent upstream, clock bindings also. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
796 lines
16 KiB
Text
796 lines
16 KiB
Text
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
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/*
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* Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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#include "lan9691.dtsi"
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/ {
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model = "Microchip EV23X71A";
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compatible = "microchip,ev23x71a", "microchip,lan9696", "microchip,lan9691";
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aliases {
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serial0 = &usart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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gpio-restart {
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compatible = "gpio-restart";
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gpios = <&gpio 60 GPIO_ACTIVE_LOW>;
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open-source;
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priority = <200>;
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};
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i2c-mux {
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compatible = "i2c-mux-gpio";
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#address-cells = <1>;
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#size-cells = <0>;
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i2c-parent = <&i2c3>;
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idle-state = <0x8>;
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mux-gpios = <&sgpio_out 0 1 GPIO_ACTIVE_HIGH>,
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<&sgpio_out 0 2 GPIO_ACTIVE_HIGH>,
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<&sgpio_out 0 3 GPIO_ACTIVE_HIGH>;
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settle-time-us = <100>;
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i2c_sfp0: i2c@0 {
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reg = <0x0>;
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};
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i2c_sfp1: i2c@1 {
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reg = <0x1>;
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};
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i2c_sfp2: i2c@2 {
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reg = <0x2>;
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};
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i2c_sfp3: i2c@3 {
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reg = <0x3>;
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};
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i2c_poe: i2c@7 {
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reg = <0x7>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led-status {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_STATUS;
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gpios = <&gpio 61 GPIO_ACTIVE_LOW>;
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};
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led-sfp1-green {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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function-enumerator = <0>;
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gpios = <&sgpio_out 6 0 GPIO_ACTIVE_LOW>;
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default-state = "off";
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};
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led-sfp1-yellow {
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color = <LED_COLOR_ID_YELLOW>;
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function = LED_FUNCTION_LAN;
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function-enumerator = <0>;
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gpios = <&sgpio_out 6 1 GPIO_ACTIVE_LOW>;
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default-state = "off";
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};
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led-sfp2-green {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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function-enumerator = <1>;
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gpios = <&sgpio_out 7 0 GPIO_ACTIVE_LOW>;
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default-state = "off";
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};
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led-sfp2-yellow {
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color = <LED_COLOR_ID_YELLOW>;
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function = LED_FUNCTION_LAN;
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function-enumerator = <1>;
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gpios = <&sgpio_out 7 1 GPIO_ACTIVE_LOW>;
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default-state = "off";
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};
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led-sfp3-green {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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function-enumerator = <2>;
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gpios = <&sgpio_out 8 0 GPIO_ACTIVE_LOW>;
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default-state = "off";
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};
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led-sfp3-yellow {
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color = <LED_COLOR_ID_YELLOW>;
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function = LED_FUNCTION_LAN;
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function-enumerator = <2>;
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gpios = <&sgpio_out 8 1 GPIO_ACTIVE_LOW>;
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default-state = "off";
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};
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led-sfp4-green {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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function-enumerator = <3>;
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gpios = <&sgpio_out 9 0 GPIO_ACTIVE_LOW>;
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default-state = "off";
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};
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led-sfp4-yellow {
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color = <LED_COLOR_ID_YELLOW>;
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function = LED_FUNCTION_LAN;
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function-enumerator = <3>;
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gpios = <&sgpio_out 9 1 GPIO_ACTIVE_LOW>;
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default-state = "off";
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};
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};
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mux-controller {
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compatible = "gpio-mux";
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#mux-control-cells = <0>;
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mux-gpios = <&sgpio_out 1 2 GPIO_ACTIVE_LOW>,
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<&sgpio_out 1 3 GPIO_ACTIVE_LOW>;
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};
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sfp0: sfp0 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c_sfp0>;
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tx-disable-gpios = <&sgpio_out 6 2 GPIO_ACTIVE_HIGH>;
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los-gpios = <&sgpio_in 6 0 GPIO_ACTIVE_HIGH>;
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mod-def0-gpios = <&sgpio_in 6 1 GPIO_ACTIVE_LOW>;
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tx-fault-gpios = <&sgpio_in 6 2 GPIO_ACTIVE_HIGH>;
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};
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sfp1: sfp1 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c_sfp1>;
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tx-disable-gpios = <&sgpio_out 7 2 GPIO_ACTIVE_HIGH>;
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los-gpios = <&sgpio_in 7 0 GPIO_ACTIVE_HIGH>;
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mod-def0-gpios = <&sgpio_in 7 1 GPIO_ACTIVE_LOW>;
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tx-fault-gpios = <&sgpio_in 7 2 GPIO_ACTIVE_HIGH>;
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};
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sfp2: sfp2 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c_sfp2>;
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tx-disable-gpios = <&sgpio_out 8 2 GPIO_ACTIVE_HIGH>;
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los-gpios = <&sgpio_in 8 0 GPIO_ACTIVE_HIGH>;
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mod-def0-gpios = <&sgpio_in 8 1 GPIO_ACTIVE_LOW>;
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tx-fault-gpios = <&sgpio_in 8 2 GPIO_ACTIVE_HIGH>;
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};
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sfp3: sfp3 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c_sfp3>;
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tx-disable-gpios = <&sgpio_out 9 2 GPIO_ACTIVE_HIGH>;
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los-gpios = <&sgpio_in 9 0 GPIO_ACTIVE_HIGH>;
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mod-def0-gpios = <&sgpio_in 9 1 GPIO_ACTIVE_LOW>;
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tx-fault-gpios = <&sgpio_in 9 2 GPIO_ACTIVE_HIGH>;
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};
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};
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&gpio {
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emmc_sd_pins: emmc-sd-pins {
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/* eMMC_SD - CMD, CLK, D0, D1, D2, D3, D4, D5, D6, D7, RSTN */
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pins = "GPIO_14", "GPIO_15", "GPIO_16", "GPIO_17",
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"GPIO_18", "GPIO_19", "GPIO_20", "GPIO_21",
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"GPIO_22", "GPIO_23", "GPIO_24";
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function = "emmc_sd";
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};
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fan_pins: fan-pins {
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pins = "GPIO_25", "GPIO_26";
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function = "fan";
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};
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fc0_pins: fc0-pins {
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pins = "GPIO_3", "GPIO_4";
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function = "fc";
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};
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fc2_pins: fc2-pins {
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pins = "GPIO_64", "GPIO_65", "GPIO_66";
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function = "fc";
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};
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fc3_pins: fc3-pins {
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pins = "GPIO_55", "GPIO_56";
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function = "fc";
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};
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mdio_pins: mdio-pins {
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pins = "GPIO_9", "GPIO_10";
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function = "miim";
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};
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mdio_irq_pins: mdio-irq-pins {
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pins = "GPIO_11";
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function = "miim_irq";
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};
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sgpio_pins: sgpio-pins {
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/* SCK, D0, D1, LD */
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pins = "GPIO_5", "GPIO_6", "GPIO_7", "GPIO_8";
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function = "sgpio_a";
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};
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usb_ulpi_pins: usb-ulpi-pins {
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pins = "GPIO_30", "GPIO_31", "GPIO_32", "GPIO_33",
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"GPIO_34", "GPIO_35", "GPIO_36", "GPIO_37",
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"GPIO_38", "GPIO_39", "GPIO_40", "GPIO_41";
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function = "usb_ulpi";
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};
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usb_rst_pins: usb-rst-pins {
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pins = "GPIO_12";
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function = "usb2phy_rst";
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};
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usb_over_pins: usb-over-pins {
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pins = "GPIO_13";
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function = "usb_over_detect";
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};
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usb_power_pins: usb-power-pins {
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pins = "GPIO_1";
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function = "usb_power";
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};
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ptp_out_pins: ptp-out-pins {
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pins = "GPIO_58";
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function = "ptpsync_4";
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};
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ptp_ext_pins: ptp-ext-pins {
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pins = "GPIO_59";
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function = "ptpsync_5";
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};
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};
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&flx0 {
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atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
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status = "okay";
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};
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&flx2 {
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atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
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status = "okay";
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};
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&flx3 {
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atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
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status = "okay";
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};
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&i2c3 {
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pinctrl-0 = <&fc3_pins>;
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pinctrl-names = "default";
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i2c-analog-filter;
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i2c-digital-filter;
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i2c-digital-filter-width-ns = <35>;
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i2c-sda-hold-time-ns = <1500>;
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status = "okay";
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};
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&mdio0 {
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pinctrl-0 = <&mdio_pins>, <&mdio_irq_pins>;
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pinctrl-names = "default";
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reset-gpios = <&gpio 62 GPIO_ACTIVE_LOW>;
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status = "okay";
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phy3: phy@3 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <3>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&gpio>;
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};
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phy4: phy@4 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <4>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&gpio>;
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};
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phy5: phy@5 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <5>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&gpio>;
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};
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phy6: phy@6 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <6>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&gpio>;
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};
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phy7: phy@7 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <7>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&gpio>;
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};
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phy8: phy@8 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <8>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&gpio>;
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};
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phy9: phy@9 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <9>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&gpio>;
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};
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phy10: phy@10 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <10>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&gpio>;
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};
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phy11: phy@11 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <11>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&gpio>;
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};
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phy12: phy@12 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <12>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&gpio>;
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};
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phy13: phy@13 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <13>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&gpio>;
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};
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phy14: phy@14 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <14>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&gpio>;
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};
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phy15: phy@15 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <15>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&gpio>;
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};
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phy16: phy@16 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <16>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&gpio>;
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};
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phy17: phy@17 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <17>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&gpio>;
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};
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phy18: phy@18 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <18>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&gpio>;
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};
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phy19: phy@19 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <19>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&gpio>;
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};
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phy20: phy@20 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <20>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&gpio>;
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};
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phy21: phy@21 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <21>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&gpio>;
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};
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phy22: phy@22 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <22>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&gpio>;
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};
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phy23: phy@23 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <23>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&gpio>;
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};
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phy24: phy@24 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <24>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&gpio>;
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};
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phy25: phy@25 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <25>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&gpio>;
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};
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phy26: phy@26 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <26>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&gpio>;
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};
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phy27: phy@27 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <27>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&gpio>;
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};
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};
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&otp {
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nvmem-layout {
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compatible = "microchip,otp-layout";
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base_mac_address: base-mac-address {
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#nvmem-cell-cells = <1>;
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};
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};
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};
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&qspi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <100000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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m25p,fast-read;
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};
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};
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&sdmmc0 {
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pinctrl-0 = <&emmc_sd_pins>;
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pinctrl-names = "default";
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max-frequency = <100000000>;
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bus-width = <8>;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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non-removable;
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disable-wp;
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status = "okay";
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};
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&serdes {
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status = "okay";
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};
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&sgpio {
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pinctrl-0 = <&sgpio_pins>;
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pinctrl-names = "default";
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microchip,sgpio-port-ranges = <0 1>, <6 9>;
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status = "okay";
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gpio@0 {
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ngpios = <128>;
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};
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gpio@1 {
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ngpios = <128>;
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};
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};
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&spi2 {
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pinctrl-0 = <&fc2_pins>;
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pinctrl-names = "default";
|
|
cs-gpios = <&gpio 63 GPIO_ACTIVE_LOW>;
|
|
status = "okay";
|
|
};
|
|
|
|
&switch {
|
|
pinctrl-0 = <&ptp_out_pins>, <&ptp_ext_pins>;
|
|
pinctrl-names = "default";
|
|
nvmem-cells = <&base_mac_address 0>;
|
|
nvmem-cell-names = "mac-address";
|
|
status = "okay";
|
|
|
|
ethernet-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port0: port@0 {
|
|
reg = <0>;
|
|
phy-handle = <&phy4>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 0>;
|
|
microchip,bandwidth = <1000>;
|
|
};
|
|
|
|
port1: port@1 {
|
|
reg = <1>;
|
|
phy-handle = <&phy5>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 0>;
|
|
microchip,bandwidth = <1000>;
|
|
};
|
|
|
|
port2: port@2 {
|
|
reg = <2>;
|
|
phy-handle = <&phy6>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 0>;
|
|
microchip,bandwidth = <1000>;
|
|
};
|
|
|
|
port3: port@3 {
|
|
reg = <3>;
|
|
phy-handle = <&phy7>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 0>;
|
|
microchip,bandwidth = <1000>;
|
|
};
|
|
|
|
port4: port@4 {
|
|
reg = <4>;
|
|
phy-handle = <&phy8>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 1>;
|
|
microchip,bandwidth = <1000>;
|
|
};
|
|
|
|
port5: port@5 {
|
|
reg = <5>;
|
|
phy-handle = <&phy9>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 1>;
|
|
microchip,bandwidth = <1000>;
|
|
};
|
|
|
|
port6: port@6 {
|
|
reg = <6>;
|
|
phy-handle = <&phy10>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 1>;
|
|
microchip,bandwidth = <1000>;
|
|
};
|
|
|
|
port7: port@7 {
|
|
reg = <7>;
|
|
phy-handle = <&phy11>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 1>;
|
|
microchip,bandwidth = <1000>;
|
|
};
|
|
|
|
port8: port@8 {
|
|
reg = <8>;
|
|
phy-handle = <&phy12>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 2>;
|
|
microchip,bandwidth = <1000>;
|
|
};
|
|
|
|
port9: port@9 {
|
|
reg = <9>;
|
|
phy-handle = <&phy13>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 2>;
|
|
microchip,bandwidth = <1000>;
|
|
};
|
|
|
|
port10: port@10 {
|
|
reg = <10>;
|
|
phy-handle = <&phy14>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 2>;
|
|
microchip,bandwidth = <1000>;
|
|
};
|
|
|
|
port11: port@11 {
|
|
reg = <11>;
|
|
phy-handle = <&phy15>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 2>;
|
|
microchip,bandwidth = <1000>;
|
|
};
|
|
|
|
port12: port@12 {
|
|
reg = <12>;
|
|
phy-handle = <&phy16>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 3>;
|
|
microchip,bandwidth = <1000>;
|
|
};
|
|
|
|
port13: port@13 {
|
|
reg = <13>;
|
|
phy-handle = <&phy17>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 3>;
|
|
microchip,bandwidth = <1000>;
|
|
};
|
|
|
|
port14: port@14 {
|
|
reg = <14>;
|
|
phy-handle = <&phy18>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 3>;
|
|
microchip,bandwidth = <1000>;
|
|
};
|
|
|
|
port15: port@15 {
|
|
reg = <15>;
|
|
phy-handle = <&phy19>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 3>;
|
|
microchip,bandwidth = <1000>;
|
|
};
|
|
|
|
port16: port@16 {
|
|
reg = <16>;
|
|
phy-handle = <&phy20>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 4>;
|
|
microchip,bandwidth = <1000>;
|
|
};
|
|
|
|
port17: port@17 {
|
|
reg = <17>;
|
|
phy-handle = <&phy21>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 4>;
|
|
microchip,bandwidth = <1000>;
|
|
};
|
|
|
|
port18: port@18 {
|
|
reg = <18>;
|
|
phy-handle = <&phy22>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 4>;
|
|
microchip,bandwidth = <1000>;
|
|
};
|
|
|
|
port19: port@19 {
|
|
reg = <19>;
|
|
phy-handle = <&phy23>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 4>;
|
|
microchip,bandwidth = <1000>;
|
|
};
|
|
|
|
port20: port@20 {
|
|
reg = <20>;
|
|
phy-handle = <&phy24>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 5>;
|
|
microchip,bandwidth = <1000>;
|
|
};
|
|
|
|
port21: port@21 {
|
|
reg = <21>;
|
|
phy-handle = <&phy25>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 5>;
|
|
microchip,bandwidth = <1000>;
|
|
};
|
|
|
|
port22: port@22 {
|
|
reg = <22>;
|
|
phy-handle = <&phy26>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 5>;
|
|
microchip,bandwidth = <1000>;
|
|
};
|
|
|
|
port23: port@23 {
|
|
reg = <23>;
|
|
phy-handle = <&phy27>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 5>;
|
|
microchip,bandwidth = <1000>;
|
|
};
|
|
|
|
port24: port@24 {
|
|
reg = <24>;
|
|
phys = <&serdes 6>;
|
|
phy-mode = "10gbase-r";
|
|
sfp = <&sfp0>;
|
|
managed = "in-band-status";
|
|
microchip,bandwidth = <10000>;
|
|
microchip,sd-sgpio = <24>;
|
|
};
|
|
|
|
port25: port@25 {
|
|
reg = <25>;
|
|
phys = <&serdes 7>;
|
|
phy-mode = "10gbase-r";
|
|
sfp = <&sfp1>;
|
|
managed = "in-band-status";
|
|
microchip,bandwidth = <10000>;
|
|
microchip,sd-sgpio = <28>;
|
|
};
|
|
|
|
port26: port@26 {
|
|
reg = <26>;
|
|
phys = <&serdes 8>;
|
|
phy-mode = "10gbase-r";
|
|
sfp = <&sfp2>;
|
|
managed = "in-band-status";
|
|
microchip,bandwidth = <10000>;
|
|
microchip,sd-sgpio = <32>;
|
|
};
|
|
|
|
port27: port@27 {
|
|
reg = <27>;
|
|
phys = <&serdes 9>;
|
|
phy-mode = "10gbase-r";
|
|
sfp = <&sfp3>;
|
|
managed = "in-band-status";
|
|
microchip,bandwidth = <10000>;
|
|
microchip,sd-sgpio = <36>;
|
|
};
|
|
|
|
port29: port@29 {
|
|
reg = <29>;
|
|
phys = <&serdes 11>;
|
|
phy-handle = <&phy3>;
|
|
phy-mode = "rgmii-id";
|
|
microchip,bandwidth = <1000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&tmon {
|
|
pinctrl-0 = <&fan_pins>;
|
|
pinctrl-names = "default";
|
|
};
|
|
|
|
&usart0 {
|
|
pinctrl-0 = <&fc0_pins>;
|
|
pinctrl-names = "default";
|
|
status = "okay";
|
|
};
|
|
|
|
&usb {
|
|
pinctrl-0 = <&usb_ulpi_pins>, <&usb_rst_pins>, <&usb_over_pins>, <&usb_power_pins>;
|
|
pinctrl-names = "default";
|
|
status = "okay";
|
|
};
|