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8c14f33bb4
The original PCS driver did not use the .pcs_validate() in phylink_pcs_ops. The patches for 1000/2500base-x and 10g modes were taken from this old driver, and thus did not bother with .pcs_validate(). Thus, even though these modes are supported, phylink would not enable them. To fix these, list these modes in .pcs_validate(). Also list them in ipq_pcs_clk_rate_get(). While the latter does not appear to change behavior, it does change the clock rates listed under /sys/kernel/debug/clk Co-developed-by: Mantas Pucka <mantas@8devices.com> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Link: https://github.com/openwrt/openwrt/pull/18435 Signed-off-by: Robert Marko <robimarko@gmail.com> |
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