openwrt/target/linux/realtek
Markus Stockhausen 0839c5c9f2
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realtek: pcs: revive dead ports after RTL8382M start
SerDes attached ports that are connected during switch
boot might not be able to transmit any data after SerDes
setup. Especially ports that passed traffic before (e.g.
for tftp initramfs boot) seem to be affected. Ports that
are connected later do not show this issue.

It turns out that the old SerDes setup never really worked
on RTL8382 and the pcs refactoring (with dynamic SerDes
start and stop) totally changed the order of network bringup
in contrast to Realtek SDK.

Fix this by restaring the switch queue whenever a SerDes
goes up for the first time.

Fixes: e956adf ("realtek: rtl838x: setup SDS in PCS driver")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21956
Signed-off-by: Robert Marko <robimarko@gmail.com>
2026-02-12 16:58:46 +01:00
..
base-files realtek: avoid redundant configuration of MAC addresses 2026-02-10 01:39:52 +01:00
dts realtek: add support for Xikestor SKS8300-12E2T2X 2026-02-07 19:37:49 +01:00
files-6.12 realtek: pcs: revive dead ports after RTL8382M start 2026-02-12 16:58:46 +01:00
image realtek: add support for Xikestor SKS8300-12E2T2X 2026-02-07 19:37:49 +01:00
patches-6.12 realtek: phy: rename and relocate module 2026-02-09 09:59:25 +01:00
profiles target: use SPDX license identifiers on Makefiles 2021-02-10 15:47:18 +01:00
rtl838x realtek: phy: rename and relocate module 2026-02-09 09:59:25 +01:00
rtl839x realtek: phy: rename and relocate module 2026-02-09 09:59:25 +01:00
rtl930x realtek: phy: rename and relocate module 2026-02-09 09:59:25 +01:00
rtl930x_nand realtek: phy: rename and relocate module 2026-02-09 09:59:25 +01:00
rtl931x realtek: phy: rename and relocate module 2026-02-09 09:59:25 +01:00
rtl931x_nand realtek: phy: rename and relocate module 2026-02-09 09:59:25 +01:00
Makefile realtek: add NAND targets for RTL93xx 2025-08-10 11:46:52 +02:00