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88a404a2d1
Add a new microchipsw target aimed add supporting Microchip switch SoC-s. Start by supporting LAN969x SoC-s as the first subtarget. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
137 lines
5.2 KiB
Diff
137 lines
5.2 KiB
Diff
From c9d1b0b54258ba13b567dd116ead3c7c30cba7d8 Mon Sep 17 00:00:00 2001
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From: Daniel Machon <daniel.machon@microchip.com>
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Date: Fri, 3 Oct 2025 14:35:59 +0200
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Subject: [PATCH] net: sparx5/lan969x: fix flooding configuration on bridge
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join/leave
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The sparx5 driver programs UC/MC/BC flooding in sparx5_update_fwd() by
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unconditionally applying bridge_fwd_mask to all flood PGIDs. Any bridge
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topology change that triggers sparx5_update_fwd() (for example enslaving
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another port) therefore reinstalls flooding in hardware for already
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bridged ports, regardless of their per-port flood flags.
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This results in clobbering of the flood masks, and desynchronization
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between software and hardware: the bridge still reports “flood off” for
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the port, but hardware has flooding enabled due to unconditional PGID
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reprogramming.
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Steps to reproduce:
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$ ip link add br0 type bridge
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$ ip link set br0 up
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$ ip link set eth0 master br0
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$ ip link set eth0 up
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$ bridge link set dev eth0 flood off
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$ ip link set eth1 master br0
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$ ip link set eth1 up
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At this point, flooding is silently re-enabled for eth0. Software still
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shows “flood off” for eth0, but hardware has flooding enabled.
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To fix this, flooding is now set explicitly during bridge join/leave,
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through sparx5_port_attr_bridge_flags():
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On bridge join, UC/MC/BC flooding is enabled by default.
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On bridge leave, UC/MC/BC flooding is disabled.
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sparx5_update_fwd() no longer touches the flood PGIDs, clobbering
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the flood masks, and desynchronizing software and hardware.
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Initialization of the flooding PGIDs have been moved to
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sparx5_start(). This is required as flooding PGIDs defaults to
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0x3fffffff in hardware and the initialization was previously handled
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in sparx5_update_fwd(), which was removed.
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With this change, user-configured flooding flags persist across bridge
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updates and are no longer overridden by sparx5_update_fwd().
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Fixes: d6fce5141929 ("net: sparx5: add switching support")
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Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
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Reviewed-by: Simon Horman <horms@kernel.org>
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Link: https://patch.msgid.link/20251003-fix-flood-fwd-v1-1-48eb478b2904@microchip.com
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Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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---
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drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 5 +++++
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.../net/ethernet/microchip/sparx5/sparx5_switchdev.c | 12 ++++++++++++
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drivers/net/ethernet/microchip/sparx5/sparx5_vlan.c | 10 ----------
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3 files changed, 17 insertions(+), 10 deletions(-)
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--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c
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+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c
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@@ -709,6 +709,11 @@ static int sparx5_start(struct sparx5 *s
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/* Init masks */
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sparx5_update_fwd(sparx5);
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+ /* Init flood masks */
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+ for (int pgid = sparx5_get_pgid(sparx5, PGID_UC_FLOOD);
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+ pgid <= sparx5_get_pgid(sparx5, PGID_BCAST); pgid++)
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+ sparx5_pgid_clear(sparx5, pgid);
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+
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/* CPU copy CPU pgids */
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spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), sparx5,
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ANA_AC_PGID_MISC_CFG(sparx5_get_pgid(sparx5, PGID_CPU)));
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--- a/drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c
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+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c
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@@ -176,6 +176,7 @@ static int sparx5_port_bridge_join(struc
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struct net_device *bridge,
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struct netlink_ext_ack *extack)
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{
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+ struct switchdev_brport_flags flags = {0};
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struct sparx5 *sparx5 = port->sparx5;
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struct net_device *ndev = port->ndev;
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int err;
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@@ -205,6 +206,11 @@ static int sparx5_port_bridge_join(struc
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*/
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__dev_mc_unsync(ndev, sparx5_mc_unsync);
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+ /* Enable uc/mc/bc flooding */
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+ flags.mask = BR_FLOOD | BR_MCAST_FLOOD | BR_BCAST_FLOOD;
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+ flags.val = flags.mask;
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+ sparx5_port_attr_bridge_flags(port, flags);
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+
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return 0;
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err_switchdev_offload:
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@@ -215,6 +221,7 @@ err_switchdev_offload:
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static void sparx5_port_bridge_leave(struct sparx5_port *port,
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struct net_device *bridge)
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{
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+ struct switchdev_brport_flags flags = {0};
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struct sparx5 *sparx5 = port->sparx5;
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switchdev_bridge_port_unoffload(port->ndev, NULL, NULL, NULL);
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@@ -234,6 +241,11 @@ static void sparx5_port_bridge_leave(str
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/* Port enters in host more therefore restore mc list */
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__dev_mc_sync(port->ndev, sparx5_mc_sync, sparx5_mc_unsync);
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+
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+ /* Disable uc/mc/bc flooding */
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+ flags.mask = BR_FLOOD | BR_MCAST_FLOOD | BR_BCAST_FLOOD;
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+ flags.val = 0;
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+ sparx5_port_attr_bridge_flags(port, flags);
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}
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static int sparx5_port_changeupper(struct net_device *dev,
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--- a/drivers/net/ethernet/microchip/sparx5/sparx5_vlan.c
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+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_vlan.c
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@@ -167,16 +167,6 @@ void sparx5_update_fwd(struct sparx5 *sp
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/* Divide up fwd mask in 32 bit words */
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bitmap_to_arr32(mask, sparx5->bridge_fwd_mask, SPX5_PORTS);
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- /* Update flood masks */
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- for (port = sparx5_get_pgid(sparx5, PGID_UC_FLOOD);
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- port <= sparx5_get_pgid(sparx5, PGID_BCAST); port++) {
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- spx5_wr(mask[0], sparx5, ANA_AC_PGID_CFG(port));
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- if (is_sparx5(sparx5)) {
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- spx5_wr(mask[1], sparx5, ANA_AC_PGID_CFG1(port));
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- spx5_wr(mask[2], sparx5, ANA_AC_PGID_CFG2(port));
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- }
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- }
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-
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/* Update SRC masks */
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for (port = 0; port < sparx5->data->consts->n_ports; port++) {
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if (test_bit(port, sparx5->bridge_fwd_mask)) {
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