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88a404a2d1
Add a new microchipsw target aimed add supporting Microchip switch SoC-s. Start by supporting LAN969x SoC-s as the first subtarget. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
57 lines
1.7 KiB
Diff
57 lines
1.7 KiB
Diff
From f157bc4635178eccb282031d7c2ba2867bd3274c Mon Sep 17 00:00:00 2001
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From: Varshini Rajendran <varshini.rajendran@microchip.com>
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Date: Mon, 8 Sep 2025 09:44:20 +0530
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Subject: [PATCH 111/112] spi: atmel-quadspi: Add support for sama7d65 QSPI
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Add support for sama7d65 QSPI controller and define its caps.
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Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
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Link: https://patch.msgid.link/20250908-microchip-qspi-v2-5-8f3d69fdd5c9@microchip.com
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Signed-off-by: Mark Brown <broonie@kernel.org>
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---
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drivers/spi/atmel-quadspi.c | 27 +++++++++++++++++++++++++++
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1 file changed, 27 insertions(+)
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--- a/drivers/spi/atmel-quadspi.c
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+++ b/drivers/spi/atmel-quadspi.c
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@@ -1615,6 +1615,24 @@ static const struct atmel_qspi_caps atme
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.has_dllon = false,
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};
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+static const struct atmel_qspi_caps atmel_sama7d65_ospi_caps = {
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+ .max_speed_hz = SAMA7G5_QSPI0_MAX_SPEED_HZ,
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+ .has_gclk = true,
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+ .octal = true,
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+ .has_dma = true,
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+ .has_2xgclk = true,
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+ .has_padcalib = true,
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+ .has_dllon = false,
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+};
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+
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+static const struct atmel_qspi_caps atmel_sama7d65_qspi_caps = {
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+ .max_speed_hz = SAMA7G5_QSPI1_SDR_MAX_SPEED_HZ,
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+ .has_gclk = true,
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+ .has_dma = true,
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+ .has_2xgclk = true,
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+ .has_dllon = false,
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+};
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+
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static const struct atmel_qspi_caps atmel_sama7g5_ospi_caps = {
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.max_speed_hz = SAMA7G5_QSPI0_MAX_SPEED_HZ,
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.has_gclk = true,
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@@ -1652,6 +1670,15 @@ static const struct of_device_id atmel_q
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.compatible = "microchip,sam9x7-ospi",
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.data = &atmel_sam9x7_ospi_caps,
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},
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+ {
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+ .compatible = "microchip,sama7d65-ospi",
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+ .data = &atmel_sama7d65_ospi_caps,
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+ },
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+ {
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+ .compatible = "microchip,sama7d65-qspi",
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+ .data = &atmel_sama7d65_qspi_caps,
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+ },
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+
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{ /* sentinel */ }
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};
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