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88a404a2d1
Add a new microchipsw target aimed add supporting Microchip switch SoC-s. Start by supporting LAN969x SoC-s as the first subtarget. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
34 lines
1.4 KiB
Diff
34 lines
1.4 KiB
Diff
From 9a39bca30a65f571fae33ac9c76e67ebca44b2a4 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Bence=20Cs=C3=B3k=C3=A1s?= <csokas.bence@prolan.hu>
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Date: Mon, 3 Feb 2025 16:12:49 +0100
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Subject: [PATCH 102/112] spi: atmel-quadspi: Fix warning in doc-comment
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The doc-comment for `struct atmel_qspi_pcal` had a typo in one of the
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struct members' name, causing a warning with the `W=1` option.
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Fixes: 5af42209a4d2 ("spi: atmel-quadspi: Add support for sama7g5 QSPI")
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Reported-by: kernel test robot <lkp@intel.com>
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Closes: https://lore.kernel.org/oe-kbuild-all/202501311707.Ltj0qXse-lkp@intel.com/
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Signed-off-by: Bence Csókás <csokas.bence@prolan.hu>
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Link: https://patch.msgid.link/20250203151249.79876-2-csokas.bence@prolan.hu
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Signed-off-by: Mark Brown <broonie@kernel.org>
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---
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drivers/spi/atmel-quadspi.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/drivers/spi/atmel-quadspi.c
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+++ b/drivers/spi/atmel-quadspi.c
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@@ -235,8 +235,8 @@
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/**
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* struct atmel_qspi_pcal - Pad Calibration Clock Division
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* @pclk_rate: peripheral clock rate.
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- * @pclkdiv: calibration clock division. The clock applied to the calibration
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- * cell is divided by pclkdiv + 1.
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+ * @pclk_div: calibration clock division. The clock applied to the calibration
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+ * cell is divided by pclk_div + 1.
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*/
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struct atmel_qspi_pcal {
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u32 pclk_rate;
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