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88a404a2d1
Add a new microchipsw target aimed add supporting Microchip switch SoC-s. Start by supporting LAN969x SoC-s as the first subtarget. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
37 lines
1.5 KiB
Diff
37 lines
1.5 KiB
Diff
From 3695a85ef07bf3ac9a2ecc458a4c199b5ab755b1 Mon Sep 17 00:00:00 2001
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From: Daniel Machon <daniel.machon@microchip.com>
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Date: Fri, 20 Dec 2024 14:48:45 +0100
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Subject: [PATCH 73/82] net: sparx5: verify RGMII speeds
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When doing a port config, we verify the port speed against the PHY mode
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and supported speeds of that PHY mode. Add checks for the four RGMII phy
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modes: RGMII, RGMII_ID, RGMII_TXID and RGMII_RXID.
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Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
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Reviewed-by: Horatiu Vultur <horatiu.vultur@microchip.com>
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Tested-by: Robert Marko <robert.marko@sartura.hr>
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Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
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Link: https://patch.msgid.link/20241220-sparx5-lan969x-switch-driver-4-v5-6-fa8ba5dff732@microchip.com
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/ethernet/microchip/sparx5/sparx5_port.c | 9 +++++++++
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1 file changed, 9 insertions(+)
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--- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c
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+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c
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@@ -257,6 +257,15 @@ static int sparx5_port_verify_speed(stru
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conf->speed != SPEED_25000))
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return sparx5_port_error(port, conf, SPX5_PERR_SPEED);
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break;
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+ case PHY_INTERFACE_MODE_RGMII:
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+ case PHY_INTERFACE_MODE_RGMII_ID:
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+ case PHY_INTERFACE_MODE_RGMII_TXID:
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+ case PHY_INTERFACE_MODE_RGMII_RXID:
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+ if (conf->speed != SPEED_1000 &&
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+ conf->speed != SPEED_100 &&
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+ conf->speed != SPEED_10)
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+ return sparx5_port_error(port, conf, SPX5_PERR_SPEED);
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+ break;
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default:
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return sparx5_port_error(port, conf, SPX5_PERR_IFTYPE);
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}
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