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88a404a2d1
Add a new microchipsw target aimed add supporting Microchip switch SoC-s. Start by supporting LAN969x SoC-s as the first subtarget. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
42 lines
1.7 KiB
Diff
42 lines
1.7 KiB
Diff
From e647f95a65d299fbb58ef8d44795abab3bc63d41 Mon Sep 17 00:00:00 2001
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From: Daniel Machon <daniel.machon@microchip.com>
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Date: Thu, 5 Dec 2024 14:54:27 +0100
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Subject: [PATCH 67/82] net: sparx5: fix default value of monitor ports
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When doing port mirroring, the physical port to send the frame to, is
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written to the FRMC_PORT_VAL field of the QFWD_FRAME_COPY_CFG register.
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This field is 7 bits wide on sparx5 and 6 bits wide on lan969x, and has
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a default value of 65 and 30, respectively (the number of front ports).
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On mirror deletion, we set the default value of the monitor port to
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65 for this field, in case no more ports exists for the mirror. Needless
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to say, this will not fit the 6 bits on lan969x.
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Fix this by correctly using the n_ports constant instead.
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Fixes: 3f9e46347a46 ("net: sparx5: use SPX5_CONST for constants which already have a symbol")
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Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/ethernet/microchip/sparx5/sparx5_mirror.c | 3 +--
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1 file changed, 1 insertion(+), 2 deletions(-)
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--- a/drivers/net/ethernet/microchip/sparx5/sparx5_mirror.c
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+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_mirror.c
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@@ -12,7 +12,6 @@
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#define SPX5_MIRROR_DISABLED 0
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#define SPX5_MIRROR_EGRESS 1
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#define SPX5_MIRROR_INGRESS 2
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-#define SPX5_MIRROR_MONITOR_PORT_DEFAULT 65
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#define SPX5_QFWD_MP_OFFSET 9 /* Mirror port offset in the QFWD register */
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/* Convert from bool ingress/egress to mirror direction */
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@@ -200,7 +199,7 @@ void sparx5_mirror_del(struct sparx5_mal
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sparx5_mirror_monitor_set(sparx5,
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mirror_idx,
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- SPX5_MIRROR_MONITOR_PORT_DEFAULT);
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+ sparx5->data->consts->n_ports);
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}
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void sparx5_mirror_stats(struct sparx5_mall_entry *entry,
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