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88a404a2d1
Add a new microchipsw target aimed add supporting Microchip switch SoC-s. Start by supporting LAN969x SoC-s as the first subtarget. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
175 lines
6.3 KiB
Diff
175 lines
6.3 KiB
Diff
From ec933122868bb205d8cdecc2049c49f811d32397 Mon Sep 17 00:00:00 2001
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From: Daniel Machon <daniel.machon@microchip.com>
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Date: Mon, 9 Sep 2024 17:14:49 +0200
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Subject: [PATCH 15/25] phy: lan969x-serdes: add support for lan969x serdes
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driver
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Add support for lan969x SERDES driver. Lan969x has ten 10G SERDES'es
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which share the same features and data rates as the Sparx5 SERDES'es.
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Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
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Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
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Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-9-d695bcb57b84@microchip.com
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Signed-off-by: Vinod Koul <vkoul@kernel.org>
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---
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drivers/phy/microchip/sparx5_serdes.c | 88 +++++++++++++++++++++++++++
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drivers/phy/microchip/sparx5_serdes.h | 2 +
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2 files changed, 90 insertions(+)
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--- a/drivers/phy/microchip/sparx5_serdes.c
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+++ b/drivers/phy/microchip/sparx5_serdes.c
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@@ -25,6 +25,8 @@
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#define SPX5_SERDES_25G_START 25
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#define SPX5_SERDES_6G10G_CNT SPX5_SERDES_25G_START
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+#define LAN969X_SERDES_10G_CNT 10
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+
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/* Optimal power settings from GUC */
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#define SPX5_SERDES_QUIET_MODE_VAL 0x01ef4e0c
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@@ -36,6 +38,13 @@ const unsigned int sparx5_serdes_tsize[T
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[TC_SD_LANE] = 25,
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};
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+const unsigned int lan969x_serdes_tsize[TSIZE_LAST] = {
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+ [TC_SD10G_LANE] = 10,
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+ [TC_SD_CMU] = 6,
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+ [TC_SD_CMU_CFG] = 6,
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+ [TC_SD_LANE] = 10,
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+};
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+
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/* Pointer to the register target size table */
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const unsigned int *tsize;
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@@ -1096,6 +1105,24 @@ static int sparx5_serdes_cmu_get(enum sp
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return sparx5_serdes_cmu_map[mode][sd_index];
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}
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+/* Map of 6G/10G serdes mode and index to CMU index. */
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+static const int
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+lan969x_serdes_cmu_map[SPX5_SD10G28_CMU_MAX][LAN969X_SERDES_10G_CNT] = {
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+ [SPX5_SD10G28_CMU_MAIN] = { 2, 2, 2, 2, 2,
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+ 2, 2, 2, 5, 5 },
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+ [SPX5_SD10G28_CMU_AUX1] = { 0, 0, 3, 3, 3,
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+ 3, 3, 3, 3, 3 },
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+ [SPX5_SD10G28_CMU_AUX2] = { 1, 1, 1, 1, 4,
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+ 4, 4, 4, 4, 4 },
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+ [SPX5_SD10G28_CMU_NONE] = { 1, 1, 1, 1, 4,
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+ 4, 4, 4, 4, 4 },
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+};
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+
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+static int lan969x_serdes_cmu_get(enum sparx5_10g28cmu_mode mode, int sd_index)
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+{
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+ return lan969x_serdes_cmu_map[mode][sd_index];
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+}
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+
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static void sparx5_serdes_cmu_power_off(struct sparx5_serdes_private *priv)
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{
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void __iomem *cmu_inst, *cmu_cfg_inst;
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@@ -2184,6 +2211,10 @@ static int sparx5_serdes_clock_config(st
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{
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struct sparx5_serdes_private *priv = macro->priv;
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+ /* Clock is auto-detected in 100Base-FX mode on lan969x */
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+ if (priv->data->type == SPX5_TARGET_LAN969X)
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+ return 0;
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+
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if (macro->serdesmode == SPX5_SD_MODE_100FX) {
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u32 freq = priv->coreclock == 250000000 ? 2 :
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priv->coreclock == 500000000 ? 1 : 0;
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@@ -2395,6 +2426,12 @@ static void sparx5_serdes_type_set(struc
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}
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}
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+static void lan969x_serdes_type_set(struct sparx5_serdes_macro *macro, int sidx)
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+{
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+ macro->serdestype = SPX5_SDT_10G;
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+ macro->stpidx = macro->sidx;
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+}
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+
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static int sparx5_phy_create(struct sparx5_serdes_private *priv,
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int idx, struct phy **phy)
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{
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@@ -2519,6 +2556,41 @@ static struct sparx5_serdes_io_resource
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{ TARGET_SD_LANE_25G + 7, 0x5c8000 }, /* 0x610dd0000: sd_lane_25g_32 */
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};
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+static const struct sparx5_serdes_io_resource lan969x_serdes_iomap[] = {
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+ { TARGET_SD_CMU, 0x0 }, /* 0xe3410000 */
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+ { TARGET_SD_CMU + 1, 0x8000 }, /* 0xe3418000 */
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+ { TARGET_SD_CMU + 2, 0x10000 }, /* 0xe3420000 */
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+ { TARGET_SD_CMU + 3, 0x18000 }, /* 0xe3428000 */
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+ { TARGET_SD_CMU + 4, 0x20000 }, /* 0xe3430000 */
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+ { TARGET_SD_CMU + 5, 0x28000 }, /* 0xe3438000 */
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+ { TARGET_SD_CMU_CFG, 0x30000 }, /* 0xe3440000 */
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+ { TARGET_SD_CMU_CFG + 1, 0x38000 }, /* 0xe3448000 */
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+ { TARGET_SD_CMU_CFG + 2, 0x40000 }, /* 0xe3450000 */
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+ { TARGET_SD_CMU_CFG + 3, 0x48000 }, /* 0xe3458000 */
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+ { TARGET_SD_CMU_CFG + 4, 0x50000 }, /* 0xe3460000 */
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+ { TARGET_SD_CMU_CFG + 5, 0x58000 }, /* 0xe3468000 */
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+ { TARGET_SD10G_LANE, 0x60000 }, /* 0xe3470000 */
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+ { TARGET_SD10G_LANE + 1, 0x68000 }, /* 0xe3478000 */
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+ { TARGET_SD10G_LANE + 2, 0x70000 }, /* 0xe3480000 */
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+ { TARGET_SD10G_LANE + 3, 0x78000 }, /* 0xe3488000 */
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+ { TARGET_SD10G_LANE + 4, 0x80000 }, /* 0xe3490000 */
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+ { TARGET_SD10G_LANE + 5, 0x88000 }, /* 0xe3498000 */
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+ { TARGET_SD10G_LANE + 6, 0x90000 }, /* 0xe34a0000 */
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+ { TARGET_SD10G_LANE + 7, 0x98000 }, /* 0xe34a8000 */
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+ { TARGET_SD10G_LANE + 8, 0xa0000 }, /* 0xe34b0000 */
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+ { TARGET_SD10G_LANE + 9, 0xa8000 }, /* 0xe34b8000 */
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+ { TARGET_SD_LANE, 0x100000 }, /* 0xe3510000 */
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+ { TARGET_SD_LANE + 1, 0x108000 }, /* 0xe3518000 */
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+ { TARGET_SD_LANE + 2, 0x110000 }, /* 0xe3520000 */
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+ { TARGET_SD_LANE + 3, 0x118000 }, /* 0xe3528000 */
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+ { TARGET_SD_LANE + 4, 0x120000 }, /* 0xe3530000 */
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+ { TARGET_SD_LANE + 5, 0x128000 }, /* 0xe3538000 */
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+ { TARGET_SD_LANE + 6, 0x130000 }, /* 0xe3540000 */
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+ { TARGET_SD_LANE + 7, 0x138000 }, /* 0xe3548000 */
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+ { TARGET_SD_LANE + 8, 0x140000 }, /* 0xe3550000 */
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+ { TARGET_SD_LANE + 9, 0x148000 }, /* 0xe3558000 */
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+};
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+
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static const struct sparx5_serdes_match_data sparx5_desc = {
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.type = SPX5_TARGET_SPARX5,
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.iomap = sparx5_serdes_iomap,
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@@ -2534,6 +2606,21 @@ static const struct sparx5_serdes_match_
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},
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};
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+static const struct sparx5_serdes_match_data lan969x_desc = {
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+ .type = SPX5_TARGET_LAN969X,
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+ .iomap = lan969x_serdes_iomap,
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+ .iomap_size = ARRAY_SIZE(lan969x_serdes_iomap),
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+ .tsize = lan969x_serdes_tsize,
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+ .consts = {
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+ .sd_max = 10,
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+ .cmu_max = 6,
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+ },
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+ .ops = {
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+ .serdes_type_set = &lan969x_serdes_type_set,
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+ .serdes_cmu_get = &lan969x_serdes_cmu_get,
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+ }
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+};
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+
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/* Client lookup function, uses serdes index */
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static struct phy *sparx5_serdes_xlate(struct device *dev,
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const struct of_phandle_args *args)
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@@ -2635,6 +2722,7 @@ static int sparx5_serdes_probe(struct pl
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static const struct of_device_id sparx5_serdes_match[] = {
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{ .compatible = "microchip,sparx5-serdes", .data = &sparx5_desc },
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+ { .compatible = "microchip,lan9691-serdes", .data = &lan969x_desc },
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{ }
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};
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MODULE_DEVICE_TABLE(of, sparx5_serdes_match);
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--- a/drivers/phy/microchip/sparx5_serdes.h
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+++ b/drivers/phy/microchip/sparx5_serdes.h
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@@ -36,6 +36,8 @@ enum sparx5_10g28cmu_mode {
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enum sparx5_target {
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SPX5_TARGET_SPARX5,
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+ SPX5_TARGET_LAN969X,
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+
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};
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struct sparx5_serdes_macro {
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