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23c0145963
On RTL930x, each SerDes pair shares a set of PLLs with different capabilities (LC PLL: 1G/2.5G/10G, ring PLL: 1G/2.5G). In principle, this allows any combination of speeds on a SerDes pair. However, it creates a special case when trying to configure a SerDes for 10G while the LC PLL is already in use at a slower speed for the neighbor SerDes. The current implementation just gives up in that case. Instead, free up the LC PLL by reconfiguring the neighbor SerDes to the ring PLL. Signed-off-by: Jan Hoffmann <jan@3e8.eu> Link: https://github.com/openwrt/openwrt/pull/20568 Signed-off-by: Robert Marko <robimarko@gmail.com> |
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| .. | ||
| base-files | ||
| dts | ||
| files/firmware/rtl838x_phy | ||
| files-6.12 | ||
| image | ||
| patches-6.12 | ||
| profiles | ||
| rtl838x | ||
| rtl839x | ||
| rtl930x | ||
| rtl930x_nand | ||
| rtl931x | ||
| rtl931x_nand | ||
| Makefile | ||