mirror of
https://git.openwrt.org/openwrt/openwrt.git
synced 2025-12-10 06:24:40 +01:00
5205c0c426
Microchip EV23X71A is a LAN9696 based EVB. Specifications: * CPU: Microchip LAN9696 switch SoC * DRAM: 1GB DDR4 * Storage: * 2MB QSPI NOR * 4GB eMMC * Networking: * 24 x 10/100/1000 RJ45 via LAN8814 Quad PHY-s over QSGMII * 4 x 100/1000/2500/5000/10000 SFP+ ports * 1 x 10/100/1000 management RJ45 via LAN8840 PHY over RGMII (U-Boot too) * USB: 1 x USB2.0 Type-A * Management via USB-C (MCP2200): * UART @ 115200 baud * GPIO-s for bootstrap, reset and clock selection * DIP switch for boostrap configuration * LED-s: * 2 per networking port (Green and Yellow) * Green status LED * Yellow reset LED * Hard reset button * Power: * 12V DC barrel jack * 48/56V DC screw terminal * Selectable via toggle switch * PTP support: * Sync-E DPLL ZL30732B to generate the board required clocks * Two SMAs for PTP and two for Station clock inputs and outputs * Two ITU-T G.8275-compliant RS-422 interfaces for PTP applications * External PoE: * Option for PoE add-on, like EV14Y36A (IEEE 802.3af/at/bt Type 4 standard com-pliant) * Option for external CPU control via SPI and PCIe Installation instructions: 1. Connect to UART via the USB-C port 2. Connect the management port 3. Boot and interrupt U-Boot 4. TFTP the OpenWrt initramfs image and boot it 5. SCP the OpenWrt eMMC GPT image to a running OpenWrt initramfs to /tmp openwrt-microchipsw-lan969x-microchip_ev23x71a-squashfs-emmc-gpt.img.gz And decompress it via: gzip -d /tmp/openwrt-microchipsw-lan969x-microchip_ev23x71a-squashfs-emmc-gpt.img.gz 6. Wipe eMMC with: dd if=/dev/zero of=/dev/mmcblk0 bs=1M 7. Flash OpenWrt eMMC image with: dd if=/tmp/openwrt-microchipsw-lan969x-microchip_ev23x71a-squashfs-emmc-gpt.img of=/dev/mmcblk0 After a restart OpenWrt will boot, and then regular sysupgrade can be used for upgrades. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
787 lines
15 KiB
Text
787 lines
15 KiB
Text
/dts-v1/;
|
|
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/leds/common.h>
|
|
#include "lan969x.dtsi"
|
|
|
|
/ {
|
|
model = "Microchip EV23X71A";
|
|
compatible = "microchip,ev23x71a", "microchip,lan969x";
|
|
|
|
aliases {
|
|
serial0 = &usart0;
|
|
led-boot = &led_status;
|
|
led-failsafe = &led_status;
|
|
led-running = &led_status;
|
|
led-upgrade = &led_status;
|
|
};
|
|
|
|
chosen {
|
|
stdout-path = "serial0:115200n8";
|
|
};
|
|
|
|
gpio-restart {
|
|
compatible = "gpio-restart";
|
|
gpios = <&gpio 60 GPIO_ACTIVE_LOW>;
|
|
open-source;
|
|
priority = <200>;
|
|
};
|
|
|
|
i2c-mux {
|
|
compatible = "i2c-mux-gpio";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
i2c-parent = <&i2c3>;
|
|
|
|
mux-gpios = <&sgpio_out 0 1 GPIO_ACTIVE_HIGH
|
|
&sgpio_out 0 2 GPIO_ACTIVE_HIGH
|
|
&sgpio_out 0 3 GPIO_ACTIVE_HIGH>;
|
|
idle-state = <0x8>;
|
|
|
|
i2c_sfp0: i2c@0 {
|
|
reg = <0x0>;
|
|
};
|
|
|
|
i2c_sfp1: i2c@1 {
|
|
reg = <0x1>;
|
|
};
|
|
|
|
i2c_sfp2: i2c@2 {
|
|
reg = <0x2>;
|
|
};
|
|
|
|
i2c_sfp3: i2c@3 {
|
|
reg = <0x3>;
|
|
};
|
|
|
|
i2c_poe: i2c@7 {
|
|
reg = <0x7>;
|
|
};
|
|
};
|
|
|
|
leds {
|
|
compatible = "gpio-leds";
|
|
|
|
led_status: led-status {
|
|
color = <LED_COLOR_ID_GREEN>;
|
|
function = LED_FUNCTION_STATUS;
|
|
gpios = <&gpio 61 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
led-sfp1-green {
|
|
color = <LED_COLOR_ID_GREEN>;
|
|
function = LED_FUNCTION_LAN;
|
|
function-enumerator = <0>;
|
|
gpios = <&sgpio_out 6 0 GPIO_ACTIVE_LOW>;
|
|
default-state = "off";
|
|
};
|
|
|
|
led-sfp1-yellow {
|
|
color = <LED_COLOR_ID_YELLOW>;
|
|
function = LED_FUNCTION_LAN;
|
|
function-enumerator = <0>;
|
|
gpios = <&sgpio_out 6 1 GPIO_ACTIVE_LOW>;
|
|
default-state = "off";
|
|
};
|
|
|
|
led-sfp2-green {
|
|
color = <LED_COLOR_ID_GREEN>;
|
|
function = LED_FUNCTION_LAN;
|
|
function-enumerator = <1>;
|
|
gpios = <&sgpio_out 7 0 GPIO_ACTIVE_LOW>;
|
|
default-state = "off";
|
|
};
|
|
|
|
led-sfp2-yellow {
|
|
color = <LED_COLOR_ID_YELLOW>;
|
|
function = LED_FUNCTION_LAN;
|
|
function-enumerator = <1>;
|
|
gpios = <&sgpio_out 7 1 GPIO_ACTIVE_LOW>;
|
|
default-state = "off";
|
|
};
|
|
|
|
led-sfp3-green {
|
|
color = <LED_COLOR_ID_GREEN>;
|
|
function = LED_FUNCTION_LAN;
|
|
function-enumerator = <2>;
|
|
gpios = <&sgpio_out 8 0 GPIO_ACTIVE_LOW>;
|
|
default-state = "off";
|
|
};
|
|
|
|
led-sfp3-yellow {
|
|
color = <LED_COLOR_ID_YELLOW>;
|
|
function = LED_FUNCTION_LAN;
|
|
function-enumerator = <2>;
|
|
gpios = <&sgpio_out 8 1 GPIO_ACTIVE_LOW>;
|
|
default-state = "off";
|
|
};
|
|
|
|
led-sfp4-green {
|
|
color = <LED_COLOR_ID_GREEN>;
|
|
function = LED_FUNCTION_LAN;
|
|
function-enumerator = <3>;
|
|
gpios = <&sgpio_out 9 0 GPIO_ACTIVE_LOW>;
|
|
default-state = "off";
|
|
};
|
|
|
|
led-sfp4-yellow {
|
|
color = <LED_COLOR_ID_YELLOW>;
|
|
function = LED_FUNCTION_LAN;
|
|
function-enumerator = <3>;
|
|
gpios = <&sgpio_out 9 1 GPIO_ACTIVE_LOW>;
|
|
default-state = "off";
|
|
};
|
|
};
|
|
|
|
mux-controller {
|
|
compatible = "gpio-mux";
|
|
#mux-control-cells = <0>;
|
|
|
|
mux-gpios = <&sgpio_out 1 2 GPIO_ACTIVE_LOW>,
|
|
<&sgpio_out 1 3 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
sfp0: sfp0 {
|
|
compatible = "sff,sfp";
|
|
i2c-bus = <&i2c_sfp0>;
|
|
tx-disable-gpios = <&sgpio_out 6 2 GPIO_ACTIVE_HIGH>;
|
|
los-gpios = <&sgpio_in 6 0 GPIO_ACTIVE_HIGH>;
|
|
mod-def0-gpios = <&sgpio_in 6 1 GPIO_ACTIVE_LOW>;
|
|
tx-fault-gpios = <&sgpio_in 6 2 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
sfp1: sfp1 {
|
|
compatible = "sff,sfp";
|
|
i2c-bus = <&i2c_sfp1>;
|
|
tx-disable-gpios = <&sgpio_out 7 2 GPIO_ACTIVE_HIGH>;
|
|
los-gpios = <&sgpio_in 7 0 GPIO_ACTIVE_HIGH>;
|
|
mod-def0-gpios = <&sgpio_in 7 1 GPIO_ACTIVE_LOW>;
|
|
tx-fault-gpios = <&sgpio_in 7 2 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
sfp2: sfp2 {
|
|
compatible = "sff,sfp";
|
|
i2c-bus = <&i2c_sfp2>;
|
|
tx-disable-gpios = <&sgpio_out 8 2 GPIO_ACTIVE_HIGH>;
|
|
los-gpios = <&sgpio_in 8 0 GPIO_ACTIVE_HIGH>;
|
|
mod-def0-gpios = <&sgpio_in 8 1 GPIO_ACTIVE_LOW>;
|
|
tx-fault-gpios = <&sgpio_in 8 2 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
sfp3: sfp3 {
|
|
compatible = "sff,sfp";
|
|
i2c-bus = <&i2c_sfp3>;
|
|
tx-disable-gpios = <&sgpio_out 9 2 GPIO_ACTIVE_HIGH>;
|
|
los-gpios = <&sgpio_in 9 0 GPIO_ACTIVE_HIGH>;
|
|
mod-def0-gpios = <&sgpio_in 9 1 GPIO_ACTIVE_LOW>;
|
|
tx-fault-gpios = <&sgpio_in 9 2 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
};
|
|
|
|
&flx0 {
|
|
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
|
|
status = "okay";
|
|
};
|
|
|
|
&usart0 {
|
|
pinctrl-0 = <&fc0_pins>;
|
|
pinctrl-names = "default";
|
|
status = "okay";
|
|
};
|
|
|
|
&flx2 {
|
|
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
|
|
status = "okay";
|
|
};
|
|
|
|
&spi2 {
|
|
pinctrl-0 = <&fc2_pins>;
|
|
pinctrl-names = "default";
|
|
cs-gpios = <&gpio 63 GPIO_ACTIVE_LOW>;
|
|
status = "okay";
|
|
};
|
|
|
|
&flx3 {
|
|
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
|
|
status = "okay";
|
|
};
|
|
|
|
&i2c3 {
|
|
pinctrl-0 = <&fc3_pins>;
|
|
pinctrl-names = "default";
|
|
i2c-analog-filter;
|
|
i2c-digital-filter;
|
|
i2c-digital-filter-width-ns = <35>;
|
|
i2c-sda-hold-time-ns = <1500>;
|
|
status = "okay";
|
|
};
|
|
|
|
&gpio {
|
|
emmc_sd_pins: emmc-sd-pins {
|
|
/* eMMC_SD - CMD, CLK, D0, D1, D2, D3, D4, D5, D6, D7, RSTN */
|
|
pins = "GPIO_14", "GPIO_15", "GPIO_16", "GPIO_17",
|
|
"GPIO_18", "GPIO_19", "GPIO_20", "GPIO_21",
|
|
"GPIO_22", "GPIO_23", "GPIO_24";
|
|
function = "emmc_sd";
|
|
};
|
|
|
|
fan_pins: fan-pins {
|
|
pins = "GPIO_25", "GPIO_26";
|
|
function = "fan";
|
|
};
|
|
|
|
fc0_pins: fc0-pins {
|
|
pins = "GPIO_3", "GPIO_4";
|
|
function = "fc";
|
|
};
|
|
|
|
fc2_pins: fc2-pins {
|
|
pins = "GPIO_64", "GPIO_65", "GPIO_66";
|
|
function = "fc";
|
|
};
|
|
|
|
fc3_pins: fc3-pins {
|
|
pins = "GPIO_55", "GPIO_56";
|
|
function = "fc";
|
|
};
|
|
|
|
mdio_pins: mdio-pins {
|
|
pins = "GPIO_9", "GPIO_10";
|
|
function = "miim";
|
|
};
|
|
|
|
mdio_irq_pins: mdio-irq-pins {
|
|
pins = "GPIO_11";
|
|
function = "miim_irq";
|
|
};
|
|
|
|
sgpio_pins: sgpio-pins {
|
|
/* SCK, D0, D1, LD */
|
|
pins = "GPIO_5", "GPIO_6", "GPIO_7", "GPIO_8";
|
|
function = "sgpio_a";
|
|
};
|
|
|
|
usb_ulpi_pins: usb-ulpi-pins {
|
|
pins = "GPIO_30", "GPIO_31", "GPIO_32", "GPIO_33",
|
|
"GPIO_34", "GPIO_35", "GPIO_36", "GPIO_37",
|
|
"GPIO_38", "GPIO_39", "GPIO_40", "GPIO_41";
|
|
function = "usb_ulpi";
|
|
};
|
|
|
|
usb_rst_pins: usb-rst-pins {
|
|
pins = "GPIO_12";
|
|
function = "usb2phy_rst";
|
|
};
|
|
|
|
usb_over_pins: usb-over-pins {
|
|
pins = "GPIO_13";
|
|
function = "usb_over_detect";
|
|
};
|
|
|
|
usb_power_pins: usb-power-pins {
|
|
pins = "GPIO_1";
|
|
function = "usb_power";
|
|
};
|
|
|
|
ptp_out_pins: ptp-out-pins {
|
|
pins = "GPIO_58";
|
|
function = "ptpsync_4";
|
|
};
|
|
|
|
ptp_ext_pins: ptp-ext-pins {
|
|
pins = "GPIO_59";
|
|
function = "ptpsync_5";
|
|
};
|
|
};
|
|
|
|
&qspi0 {
|
|
status = "okay";
|
|
|
|
flash@0 {
|
|
compatible = "jedec,spi-nor";
|
|
reg = <0>;
|
|
spi-max-frequency = <100000000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
spi-tx-bus-width = <1>;
|
|
spi-rx-bus-width = <4>;
|
|
m25p,fast-read;
|
|
};
|
|
};
|
|
|
|
&sdmmc0 {
|
|
pinctrl-0 = <&emmc_sd_pins>;
|
|
pinctrl-names = "default";
|
|
max-frequency = <100000000>;
|
|
bus-width = <8>;
|
|
mmc-ddr-1_8v;
|
|
mmc-hs200-1_8v;
|
|
non-removable;
|
|
disable-wp;
|
|
status = "okay";
|
|
};
|
|
|
|
&tmon {
|
|
pinctrl-0 = <&fan_pins>;
|
|
pinctrl-names = "default";
|
|
};
|
|
|
|
&mdio0 {
|
|
pinctrl-0 = <&mdio_pins>, <&mdio_irq_pins>;
|
|
pinctrl-names = "default";
|
|
reset-gpios = <&gpio 62 GPIO_ACTIVE_LOW>;
|
|
status = "okay";
|
|
|
|
phy3: phy@3 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <3>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-parent = <&gpio>;
|
|
};
|
|
|
|
phy4: phy@4 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <4>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-parent = <&gpio>;
|
|
};
|
|
|
|
phy5: phy@5 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <5>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-parent = <&gpio>;
|
|
};
|
|
|
|
phy6: phy@6 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <6>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-parent = <&gpio>;
|
|
};
|
|
|
|
phy7: phy@7 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <7>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-parent = <&gpio>;
|
|
};
|
|
|
|
phy8: phy@8 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <8>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-parent = <&gpio>;
|
|
};
|
|
|
|
phy9: phy@9 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <9>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-parent = <&gpio>;
|
|
};
|
|
|
|
phy10: phy@10 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <10>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-parent = <&gpio>;
|
|
};
|
|
|
|
phy11: phy@11 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <11>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-parent = <&gpio>;
|
|
};
|
|
|
|
phy12: phy@12 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <12>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-parent = <&gpio>;
|
|
};
|
|
|
|
phy13: phy@13 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <13>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-parent = <&gpio>;
|
|
};
|
|
|
|
phy14: phy@14 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <14>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-parent = <&gpio>;
|
|
};
|
|
|
|
phy15: phy@15 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <15>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-parent = <&gpio>;
|
|
};
|
|
|
|
phy16: phy@16 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <16>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-parent = <&gpio>;
|
|
};
|
|
|
|
phy17: phy@17 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <17>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-parent = <&gpio>;
|
|
};
|
|
|
|
phy18: phy@18 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <18>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-parent = <&gpio>;
|
|
};
|
|
|
|
phy19: phy@19 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <19>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-parent = <&gpio>;
|
|
};
|
|
|
|
phy20: phy@20 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <20>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-parent = <&gpio>;
|
|
};
|
|
|
|
phy21: phy@21 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <21>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-parent = <&gpio>;
|
|
};
|
|
|
|
phy22: phy@22 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <22>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-parent = <&gpio>;
|
|
};
|
|
|
|
phy23: phy@23 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <23>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-parent = <&gpio>;
|
|
};
|
|
|
|
phy24: phy@24 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <24>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-parent = <&gpio>;
|
|
};
|
|
|
|
phy25: phy@25 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <25>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-parent = <&gpio>;
|
|
};
|
|
|
|
phy26: phy@26 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <26>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-parent = <&gpio>;
|
|
};
|
|
|
|
phy27: phy@27 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <27>;
|
|
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-parent = <&gpio>;
|
|
};
|
|
};
|
|
|
|
&serdes {
|
|
status = "okay";
|
|
};
|
|
|
|
&sgpio {
|
|
pinctrl-0 = <&sgpio_pins>;
|
|
pinctrl-names = "default";
|
|
|
|
microchip,sgpio-port-ranges = <0 1>, <6 9>;
|
|
status = "okay";
|
|
|
|
gpio@0 {
|
|
ngpios = <128>;
|
|
};
|
|
gpio@1 {
|
|
ngpios = <128>;
|
|
};
|
|
};
|
|
|
|
&switch {
|
|
pinctrl-0 = <&ptp_out_pins>, <&ptp_ext_pins>;
|
|
pinctrl-names = "default";
|
|
|
|
status = "okay";
|
|
ethernet-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port0: port@0 {
|
|
reg = <0>;
|
|
microchip,bandwidth = <1000>;
|
|
phy-handle = <&phy4>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 0>;
|
|
};
|
|
|
|
port1: port@1 {
|
|
reg = <1>;
|
|
microchip,bandwidth = <1000>;
|
|
phy-handle = <&phy5>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 0>;
|
|
};
|
|
|
|
port2: port@2 {
|
|
reg = <2>;
|
|
microchip,bandwidth = <1000>;
|
|
phy-handle = <&phy6>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 0>;
|
|
};
|
|
|
|
port3: port@3 {
|
|
reg = <3>;
|
|
microchip,bandwidth = <1000>;
|
|
phy-handle = <&phy7>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 0>;
|
|
};
|
|
|
|
port4: port@4 {
|
|
reg = <4>;
|
|
microchip,bandwidth = <1000>;
|
|
phy-handle = <&phy8>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 1>;
|
|
};
|
|
|
|
port5: port@5 {
|
|
reg = <5>;
|
|
microchip,bandwidth = <1000>;
|
|
phy-handle = <&phy9>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 1>;
|
|
};
|
|
|
|
port6: port@6 {
|
|
reg = <6>;
|
|
microchip,bandwidth = <1000>;
|
|
phy-handle = <&phy10>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 1>;
|
|
};
|
|
|
|
port7: port@7 {
|
|
reg = <7>;
|
|
microchip,bandwidth = <1000>;
|
|
phy-handle = <&phy11>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 1>;
|
|
};
|
|
|
|
port8: port@8 {
|
|
reg = <8>;
|
|
microchip,bandwidth = <1000>;
|
|
phy-handle = <&phy12>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 2>;
|
|
};
|
|
|
|
port9: port@9 {
|
|
reg = <9>;
|
|
microchip,bandwidth = <1000>;
|
|
phy-handle = <&phy13>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 2>;
|
|
};
|
|
|
|
port10: port@10 {
|
|
reg = <10>;
|
|
microchip,bandwidth = <1000>;
|
|
phy-handle = <&phy14>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 2>;
|
|
};
|
|
|
|
port11: port@11 {
|
|
reg = <11>;
|
|
microchip,bandwidth = <1000>;
|
|
phy-handle = <&phy15>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 2>;
|
|
};
|
|
|
|
port12: port@12 {
|
|
reg = <12>;
|
|
microchip,bandwidth = <1000>;
|
|
phy-handle = <&phy16>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 3>;
|
|
};
|
|
|
|
port13: port@13 {
|
|
reg = <13>;
|
|
microchip,bandwidth = <1000>;
|
|
phy-handle = <&phy17>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 3>;
|
|
};
|
|
|
|
port14: port@14 {
|
|
reg = <14>;
|
|
microchip,bandwidth = <1000>;
|
|
phy-handle = <&phy18>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 3>;
|
|
};
|
|
|
|
port15: port@15 {
|
|
reg = <15>;
|
|
microchip,bandwidth = <1000>;
|
|
phy-handle = <&phy19>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 3>;
|
|
};
|
|
|
|
port16: port@16 {
|
|
reg = <16>;
|
|
microchip,bandwidth = <1000>;
|
|
phy-handle = <&phy20>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 4>;
|
|
};
|
|
|
|
port17: port@17 {
|
|
reg = <17>;
|
|
microchip,bandwidth = <1000>;
|
|
phy-handle = <&phy21>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 4>;
|
|
};
|
|
|
|
port18: port@18 {
|
|
reg = <18>;
|
|
microchip,bandwidth = <1000>;
|
|
phy-handle = <&phy22>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 4>;
|
|
};
|
|
|
|
port19: port@19 {
|
|
reg = <19>;
|
|
microchip,bandwidth = <1000>;
|
|
phy-handle = <&phy23>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 4>;
|
|
};
|
|
|
|
port20: port@20 {
|
|
reg = <20>;
|
|
microchip,bandwidth = <1000>;
|
|
phy-handle = <&phy24>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 5>;
|
|
};
|
|
|
|
port21: port@21 {
|
|
reg = <21>;
|
|
microchip,bandwidth = <1000>;
|
|
phy-handle = <&phy25>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 5>;
|
|
};
|
|
|
|
port22: port@22 {
|
|
reg = <22>;
|
|
microchip,bandwidth = <1000>;
|
|
phy-handle = <&phy26>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 5>;
|
|
};
|
|
|
|
port23: port@23 {
|
|
reg = <23>;
|
|
microchip,bandwidth = <1000>;
|
|
phy-handle = <&phy27>;
|
|
phy-mode = "qsgmii";
|
|
phys = <&serdes 5>;
|
|
};
|
|
|
|
port24: port@24 {
|
|
reg = <24>;
|
|
microchip,bandwidth = <10000>;
|
|
phys = <&serdes 6>;
|
|
phy-mode = "10gbase-r";
|
|
sfp = <&sfp0>;
|
|
microchip,sd-sgpio = <24>;
|
|
managed = "in-band-status";
|
|
};
|
|
|
|
port25: port@25 {
|
|
reg = <25>;
|
|
microchip,bandwidth = <10000>;
|
|
phys = <&serdes 7>;
|
|
phy-mode = "10gbase-r";
|
|
sfp = <&sfp1>;
|
|
microchip,sd-sgpio = <28>;
|
|
managed = "in-band-status";
|
|
};
|
|
|
|
port26: port@26 {
|
|
reg = <26>;
|
|
microchip,bandwidth = <10000>;
|
|
phys = <&serdes 8>;
|
|
phy-mode = "10gbase-r";
|
|
sfp = <&sfp2>;
|
|
microchip,sd-sgpio = <32>;
|
|
managed = "in-band-status";
|
|
};
|
|
|
|
port27: port@27 {
|
|
reg = <27>;
|
|
microchip,bandwidth = <10000>;
|
|
phys = <&serdes 9>;
|
|
phy-mode = "10gbase-r";
|
|
sfp = <&sfp3>;
|
|
microchip,sd-sgpio = <36>;
|
|
managed = "in-band-status";
|
|
};
|
|
|
|
port29: port@29 {
|
|
reg = <29>;
|
|
microchip,bandwidth = <1000>;
|
|
phys = <&serdes 11>;
|
|
phy-handle = <&phy3>;
|
|
phy-mode = "rgmii";
|
|
rx-internal-delay-ps = <1000>;
|
|
tx-internal-delay-ps = <1000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&usb {
|
|
status = "okay";
|
|
pinctrl-0 = <&usb_ulpi_pins>, <&usb_rst_pins>, <&usb_over_pins>, <&usb_power_pins>;
|
|
pinctrl-names = "default";
|
|
};
|