mirror of
https://git.openwrt.org/openwrt/openwrt.git
synced 2026-02-10 12:52:56 +01:00
According to MediaTek MT7688 Datasheet v1.4, as well as the MT7628 counterpart, the memory controller reset bit (MC_RST) is 10, not 20. Reset bit 20 is used for for UART 2 (UART2_RST). Please note: Due to the lack of hardware, I was not able to test this change. Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com> |
||
|---|---|---|
| .. | ||
| imagebuilder | ||
| linux | ||
| llvm-bpf | ||
| sdk | ||
| toolchain | ||
| Config.in | ||
| Makefile | ||