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IPQ5018 based boards come in multiple wireless architectures. The SOC itself provides 2.4G wifi while 5G wifi is added by either an IPQ5018-specific QCN6122 (2x2) solution or by the more generally available PCIe-based QCN9074 (4x4) wifi chip. On IPQ5018/QCN6122-based boards, both QCN6122 and IPQ5018 wifi is initialized by IPQ5018 firmware which comes in different versions: - IPQ5018: firmware files to initialize WCSS and the internal wifi chip - IPQ5018/QCN6122: above + additional firmware segments to initialize the QCN6122 chip incl. (de-)assertion of resets and clocks enablement OpenWrt currently packages the combined IPQ5018/QCN6122 firmware for both architectures. As such, let's switch to using IPQ5018-only firmware for boards not packed with QCN6122 chip(s) and keep using the shared firmware for devices that do have QCN6122(s) chips. This helps us move to using upstreamed IPQ5018 firmware while using the legacy repo for IPQ5018/QCN6122 firmware and rule out any initialization conflicts/issues caused by loading QCN6122 on IPQ5018-only boards. While at it, default to the secure WCSS remoteproc driver sent upstream for review, move QCN6122 wifi nodes to a separate dtsi, override the Q6 node to load the multi-PD-based architecture remoteproc driver for needed only by IPQ5018/QCN6122 designs, reference said dtsi in boards packed with QCN6122 wifi chip(s), and add provision for migrating the radio path as the wifi nodes now adhere to linux device tree naming conventions. Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://github.com/openwrt/openwrt/pull/20928 Signed-off-by: Robert Marko <robimarko@gmail.com>
27 lines
784 B
Diff
27 lines
784 B
Diff
From: George Moussalem <george.moussalem@outlook.com>
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Subject: [PATCH] arm64: dts: qcom: ipq5018: Add PWM node
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Date: Sun, 06 Oct 2024 16:34:11 +0400
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Add PWM node.
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Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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---
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--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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@@ -458,6 +458,16 @@
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reg = <0x01937000 0x21000>;
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};
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+ pwm: pwm@1941010 {
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+ compatible = "qcom,ipq5018-pwm", "qcom,ipq6018-pwm";
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+ reg = <0x01941010 0x20>;
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+ clocks = <&gcc GCC_ADSS_PWM_CLK>;
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+ assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>;
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+ assigned-clock-rates = <100000000>;
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+ #pwm-cells = <2>;
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+ status = "disabled";
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+ };
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+
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sdhc_1: mmc@7804000 {
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compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5";
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reg = <0x7804000 0x1000>;
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