Tomasz Maciej Nowak 2d61f8821c mvebu: cortexa9: correct cpu subtype ... Armada 370 processors have only 16 double-precision registers. The change introduced by 8dcc108760 ("toolchain: ARM: Fix toolchain compilation for gcc 8.x") switched accidentally the toolchain for mvebu cortexa9 subtarget to cpu type with 32 double-precision registers. This stems from gcc defaults which assume "vfpv3-d32" if only "vfpv3" as mfpu is specified. That change resulted in unusable image, in which kernel will kill userspace as soon as it causing "Illegal instruction". Ref: https://forum.openwrt.org/t/gcc-was-broken-on-mvebu-armada-370-device-after-commit-on-2019-03-25/43272 Fixes: 8dcc108760 ("toolchain: ARM: Fix toolchain compilation for gcc 8.x") Signed-off-by: Tomasz Maciej Nowak <tomek_n@o2.pl>		2020-03-28 22:58:36 +01:00
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imagebuilder	target/imagebuilder: use multi-thread support for xz compression	2019-10-09 09:13:44 +02:00
linux	mvebu: cortexa9: correct cpu subtype	2020-03-28 22:58:36 +01:00
sdk	sdk: use bundle-libraries.sh to ship kernel objtool tools	2019-09-03 10:45:25 +02:00
toolchain	toolchain: wrapper.sh: harmonize leading whitespaces	2019-12-31 01:36:16 +01:00
Config.in	build: add a config option for enabling a testing version of the target kernel	2019-05-11 11:37:10 +02:00
Makefile	build: make <subdir>/install opt-in, use it for target/ only	2017-02-09 13:51:35 +01:00