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https://git.openwrt.org/openwrt/openwrt.git
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a66e30631c
Align the qualcommax target to the pattern already used on other devices where the device DTS are placed in a dedicated directory separate from the files directory. This, while trying to enforce a common pattern for every target, also permits to do modification to device DTS without having to trigger a recompilation of the entire kernel (as the files directory is not touched) Link: https://github.com/openwrt/openwrt/pull/22037 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
585 lines
10 KiB
Text
585 lines
10 KiB
Text
/dts-v1/;
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#include "ipq5018.dtsi"
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#include "ipq5018-ess.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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/ {
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model = "Xiaomi AX6000";
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compatible = "xiaomi,ax6000", "qcom,ipq5018";
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aliases {
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label-mac-device = &dp1;
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led-boot = &led_system_blue;
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led-failsafe = &led_system_yellow;
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led-running = &led_system_blue;
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led-upgrade = &led_system_yellow;
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serial0 = &blsp1_uart1;
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};
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chosen {
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/* Xiaomi's U-boot sets bootargs to:
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* ubi.mtd=rootfs_1 root=mtd:ubi_rootfs rootfstype=squashfs rootwait uart_en=1
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* so we need to override and set ubi.mtd=rootfs
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*/
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bootargs-append = " ubi.mtd=rootfs root=/dev/ubiblock0_0 coherent_pool=2M";
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stdout-path = "serial0:115200n8";
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};
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keys {
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compatible = "gpio-keys";
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pinctrl-0 = <&button_pins>;
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pinctrl-names = "default";
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reset-button {
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label = "reset";
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gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-0 = <&leds_pins>;
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pinctrl-names = "default";
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led_wlan_green: wlan-green {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_WLAN;
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gpios = <&tlmm 23 GPIO_ACTIVE_HIGH>;
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};
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led_system_blue: system-blue {
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color = <LED_COLOR_ID_BLUE>;
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function = LED_FUNCTION_POWER;
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gpios = <&tlmm 24 GPIO_ACTIVE_HIGH>;
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};
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led_system_yellow: system-yellow {
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color = <LED_COLOR_ID_YELLOW>;
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function = LED_FUNCTION_POWER;
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gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
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};
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led_net_blue: net-blue {
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color = <LED_COLOR_ID_BLUE>;
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function = LED_FUNCTION_WAN_ONLINE;
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gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
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};
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led_net_yellow: net-yellow {
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color = <LED_COLOR_ID_YELLOW>;
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function = LED_FUNCTION_WAN;
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gpios = <&tlmm 27 GPIO_ACTIVE_HIGH>;
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};
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led_phy_green: phy-green {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
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};
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};
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};
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&sleep_clk {
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clock-frequency = <32000>;
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};
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&xo_board_clk {
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clock-div = <4>;
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clock-mult = <1>;
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};
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&blsp1_uart1 {
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status = "okay";
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pinctrl-0 = <&serial_0_pins>;
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pinctrl-names = "default";
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};
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&crypto {
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status = "okay";
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};
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&cryptobam {
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status = "okay";
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};
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&prng {
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status = "okay";
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};
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&qfprom {
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status = "okay";
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};
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&qpic_bam {
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status = "okay";
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};
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&qpic_nand {
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pinctrl-0 = <&qpic_pins>;
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pinctrl-names = "default";
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status = "okay";
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nand@0 {
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compatible = "spi-nand";
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reg = <0>;
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nand-ecc-engine = <&qpic_nand>;
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nand-bus-width = <8>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "0:sbl1";
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reg = <0x00000000 0x80000>;
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read-only;
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};
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partition@80000 {
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label = "0:mibib";
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reg = <0x00080000 0x80000>;
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read-only;
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};
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partition@100000 {
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label = "0:bootconfig";
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reg = <0x00100000 0x40000>;
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read-only;
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};
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partition@140000 {
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label = "0:bootconfig1";
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reg = <0x00140000 0x40000>;
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read-only;
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};
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partition@180000 {
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label = "0:qsee";
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reg = <0x00180000 0x100000>;
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read-only;
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};
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partition@280000 {
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label = "0:qsee_1";
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reg = <0x00280000 0x100000>;
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read-only;
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};
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partition@380000 {
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label = "0:devcfg";
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reg = <0x00380000 0x40000>;
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read-only;
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};
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partition@3c0000 {
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label = "0:devcfg_1";
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reg = <0x003c0000 0x40000>;
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read-only;
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};
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partition@400000 {
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label = "0:cdt";
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reg = <0x00400000 0x40000>;
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read-only;
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};
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partition@440000 {
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label = "0:cdt_1`";
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reg = <0x00440000 0x40000>;
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read-only;
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};
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partition@480000 {
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label = "0:appsblenv";
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reg = <0x00480000 0x80000>;
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};
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partition@500000 {
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label = "0:appsbl";
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reg = <0x00500000 0x140000>;
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read-only;
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};
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partition@640000 {
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label = "0:appsbl_1";
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reg = <0x00640000 0x140000>;
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read-only;
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};
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partition@780000 {
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label = "0:art";
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reg = <0x00780000 0x100000>;
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read-only;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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mac_addr_dp1: macaddr@0 {
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reg = <0x0 0x6>;
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};
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mac_addr_dp2: macaddr@6 {
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reg = <0x6 0x6>;
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};
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caldata_qca9889: caldata@4d000 {
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reg = <0x4d000 0x844>;
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};
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};
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};
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partition@880000 {
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label = "0:training";
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reg = <0x00880000 0x80000>;
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read-only;
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};
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partition@900000 {
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label = "bdata";
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reg = <0x00900000 0x80000>;
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};
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partition@980000 {
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label = "crash";
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reg = <0x00980000 0x80000>;
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};
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partition@a00000 {
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label = "crash_syslog";
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reg = <0x00a00000 0x80000>;
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};
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partition@a80000 {
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label = "ubi_kernel";
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reg = <0x00a80000 0x2400000>;
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};
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partition@2e80000 {
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label = "rootfs";
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reg = <0x02e80000 0x5180000>;
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};
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};
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};
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};
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/*
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* =================================================================
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* _______________________ _______________________
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* | IPQ5018 | | QCA8337 |
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* | +------+ +--------+ | | +--------+ +------+ |
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* | | MAC0 |---| GE Phy |-+--- MDI ---+ | Phy3 |---| MAC4 | |
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* | +------+ +--------+ | | +--------+ +------+ |
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* | | |_______________________|
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* | | _______________________
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* | | | QCA8081 |
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* | +------+ +--------+ | | +-------------------+ |
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* | | MAC1 |---| Uniphy |-+-- SGMII+--+ | Phy | |
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* | +------+ +--------+ | | +-------------------+ |
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* |_______________________| |_______________________|
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*
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* =================================================================
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*/
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&switch {
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status = "okay";
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switch_mac_mode = <MAC_MODE_SGMII_CHANNEL0>;
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qcom,port_phyinfo {
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// MAC0 -> GE Phy --- MDI --- QCA8337 Switch
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port@1 {
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port_id = <1>;
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mdiobus = <&mdio0>;
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phy_address = <7>;
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phy_dac = <0x10 0x10>;
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};
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// MAC1 -> Uniphy --- SGMII --- QCA8081
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port@2 {
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port_id = <2>;
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mdiobus = <&mdio1>;
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phy_address = <8>;
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port_mac_sel = "QGMAC_PORT";
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};
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};
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};
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// MAC0 -> GE Phy
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&dp1 {
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status = "okay";
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nvmem-cells = <&mac_addr_dp1 0>;
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nvmem-cell-names = "mac-address";
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};
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// MAC1 ---SGMII---> QCA8081
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&dp2 {
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status = "okay";
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label = "wan";
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phy-handle = <&qca8081>;
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nvmem-cells = <&mac_addr_dp2 0>;
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nvmem-cell-names = "mac-address";
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};
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&mdio0 {
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status = "okay";
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};
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// IPQ5018 GE Phy -> QCA8337 PHY0
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&ge_phy {
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qcom,dac-preset-short-cable;
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};
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&mdio1 {
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status = "okay";
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pinctrl-0 = <&mdio1_pins>;
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pinctrl-names = "default";
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reset-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
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// QCA8337 Phy0 -> LAN1
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qca8337_0: ethernet-phy@0 {
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reg = <0>;
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};
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// QCA8337 Phy1 -> LAN2
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qca8337_1: ethernet-phy@1 {
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reg = <1>;
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};
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// QCA8337 Phy2 -> LAN3
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qca8337_2: ethernet-phy@2 {
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reg = <2>;
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};
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// QCA8337 Phy3 -> IPQ5018 GE Phy
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qca8337_3: ethernet-phy@3 {
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reg = <3>;
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};
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// QCA8081 Phy -> WAN
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qca8081: ethernet-phy@8 {
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compatible = "ethernet-phy-id004d.d101";
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reg = <8>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_WAN;
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default-state = "keep";
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};
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};
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};
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// QCA8337 switch
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ethernet-switch@11 {
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compatible = "qca,qca8337";
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reg = <17>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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reg = <1>;
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label = "lan1";
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phy-handle = <&qca8337_0>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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};
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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phy-handle = <&qca8337_1>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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};
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};
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port@3 {
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reg = <3>;
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label = "lan3";
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phy-handle = <&qca8337_2>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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default-state = "keep";
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};
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};
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};
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port@4 {
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reg = <4>;
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phy-handle = <&qca8337_3>;
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phy-mode = "gmii";
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ethernet = <&dp1>;
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};
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};
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};
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};
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&tlmm {
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button_pins: button-state {
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pins = "gpio38";
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function = "gpio";
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drive-strength = <8>;
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bias-pull-up;
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};
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leds_pins: leds-state {
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pins = "gpio23", "gpio24", "gpio25",
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"gpio26", "gpio27", "gpio28";
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function = "gpio";
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drive-strength = <8>;
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bias-pull-down;
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};
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mdio1_pins: mdio-state {
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mdc-pins {
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pins = "gpio36";
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function = "mdc";
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drive-strength = <8>;
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bias-pull-up;
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};
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mdio-pins {
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pins = "gpio37";
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function = "mdio";
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drive-strength = <8>;
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bias-pull-up;
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};
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};
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qpic_pins: qpic-state {
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clock-pins {
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pins = "gpio9";
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function = "qspi_clk";
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drive-strength = <8>;
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bias-disable;
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};
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cs-pins {
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pins = "gpio8";
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function = "qspi_cs";
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drive-strength = <8>;
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bias-disable;
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};
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data-pins {
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pins = "gpio4", "gpio5", "gpio6", "gpio7";
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function = "qspi_data";
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drive-strength = <8>;
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bias-disable;
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};
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};
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serial_0_pins: uart0-state {
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pins = "gpio20", "gpio21";
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function = "blsp0_uart0";
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bias-disable;
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};
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};
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&pcie0_phy {
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status = "okay";
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};
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&pcie0 {
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status = "okay";
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perst-gpios = <&tlmm 15 GPIO_ACTIVE_LOW>;
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pcie@0 {
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wifi@0,0 {
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status = "okay";
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/* QCN9074: ath11k lacks DT compatible for PCI cards */
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compatible = "pci17cb,1104";
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reg = <0x00010000 0 0 0 0>;
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qcom,ath11k-calibration-variant = "Xiaomi-AX6000";
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};
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};
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};
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&pcie1_phy {
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status = "okay";
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};
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&pcie1 {
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/*
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* although the pcie1 phy probes successfully, the controller is unable
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* to bring it up. So let's disable it until a solution is found.
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*/
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status = "disabled";
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perst-gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
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pcie@0 {
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wifi@0,0 {
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status = "okay";
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compatible = "qcom,ath10k";
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reg = <0x00010000 0 0 0 0>;
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qcom,ath10k-calibration-variant = "Xiaomi-AX6000";
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nvmem-cell-names = "calibration";
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nvmem-cells = <&caldata_qca9889>;
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};
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};
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};
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&q6v5_wcss {
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firmware-name = "ath11k/IPQ5018/hw1.0/q6_fw.mdt",
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"ath11k/IPQ5018/hw1.0/m3_fw.mdt";
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};
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&wifi {
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status = "okay";
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qcom,rproc = <&q6v5_wcss>;
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qcom,ath11k-calibration-variant = "Xiaomi-AX6000";
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qcom,ath11k-fw-memory-mode = <1>;
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};
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