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realtek: pcs: rtl838x: import SerDes code from DSA/PHY
Import functions 'rtl8380_sds_rst', 'rtl8380_sds_power', 'rtl8380_configure_serdes' and 'rtl83xx_config_interface' from DSA and PHY driver respectively but comment the code for now. The code needs heavy adjustments to make it compile and work. To make this as transparent as possible, do that in two stages. Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com> Link: https://github.com/openwrt/openwrt/pull/20876 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Jonas Jelonek
Hauke Mehrtens
parent
6a5cae7d74
commit
f4129beb39
1 changed files with 202 additions and 0 deletions
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@ -53,6 +53,18 @@
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#define RTPCS_838X_SDS_CFG_REG 0x34
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#define RTPCS_838X_RST_GLB_CTRL_0 0x3c
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#define RTL838X_SDS_MODE_SEL (0x0028)
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#define RTL838X_INT_MODE_CTRL (0x005c)
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#define RTL838X_DMY_REG31 (0x3b28)
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#define RTL838X_INT_RW_CTRL (0x0058)
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#define RTL838X_PLL_CML_CTRL (0x0FF8)
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#define RTL8380_SDS4_FIB_REG0 (0xF800)
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#define RTL838X_SDS4_REG28 (0xef80)
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#define RTL838X_SDS4_DUMMY0 (0xef8c)
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#define RTL838X_SDS5_EXT_REG6 (0xf18c)
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#define RTL838X_SDS4_FIB_REG0 (RTL838X_SDS4_REG28 + 0x880)
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#define RTL838X_SDS5_FIB_REG0 (RTL838X_SDS4_REG28 + 0x980)
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#define RTPCS_93XX_MAC_LINK_SPD_BITS 4
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@ -394,6 +406,196 @@ static void rtpcs_838x_sds_patch_5_fiber_6275b(struct rtpcs_ctrl *ctrl)
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rtpcs_sds_write(ctrl, 5, 1, 9, 0x8c64);
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}
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/*
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void rtl8380_sds_rst(int mac)
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{
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u32 offset = (mac == 24) ? 0 : 0x100;
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sw_w32_mask(1 << 11, 0, RTL838X_SDS4_FIB_REG0 + offset);
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sw_w32_mask(0x3, 0, RTL838X_SDS4_REG28 + offset);
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sw_w32_mask(0x3, 0x3, RTL838X_SDS4_REG28 + offset);
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sw_w32_mask(0, 0x1 << 6, RTL838X_SDS4_DUMMY0 + offset);
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sw_w32_mask(0x1 << 6, 0, RTL838X_SDS4_DUMMY0 + offset);
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pr_debug("SERDES reset: %d\n", mac);
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}
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int rtl8380_sds_power(int mac, int val)
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{
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u32 mode = (val == 1) ? 0x4 : 0x9;
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u32 offset = (mac == 24) ? 5 : 0;
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if ((mac != 24) && (mac != 26)) {
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pr_err("%s: not a fibre port: %d\n", __func__, mac);
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return -1;
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}
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sw_w32_mask(0x1f << offset, mode << offset, RTL838X_SDS_MODE_SEL);
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rtl8380_sds_rst(mac);
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return 0;
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}
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static int rtl8380_configure_serdes(struct phy_device *phydev)
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{
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u32 v;
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u32 sds_conf_value;
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int i;
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struct fw_header *h;
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u32 *rtl8380_sds_take_reset;
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u32 *rtl8380_sds_common;
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u32 *rtl8380_sds01_qsgmii_6275b;
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u32 *rtl8380_sds23_qsgmii_6275b;
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u32 *rtl8380_sds4_fiber_6275b;
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u32 *rtl8380_sds5_fiber_6275b;
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u32 *rtl8380_sds_reset;
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u32 *rtl8380_sds_release_reset;
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phydev_info(phydev, "Detected internal RTL8380 SERDES\n");
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h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8380_1);
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if (!h)
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return -1;
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if (h->magic != 0x83808380) {
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phydev_err(phydev, "Wrong firmware file: magic number mismatch.\n");
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return -1;
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}
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rtl8380_sds_take_reset = (void *)h + sizeof(struct fw_header) + h->parts[0].start;
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rtl8380_sds_common = (void *)h + sizeof(struct fw_header) + h->parts[1].start;
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rtl8380_sds01_qsgmii_6275b = (void *)h + sizeof(struct fw_header) + h->parts[2].start;
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rtl8380_sds23_qsgmii_6275b = (void *)h + sizeof(struct fw_header) + h->parts[3].start;
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rtl8380_sds4_fiber_6275b = (void *)h + sizeof(struct fw_header) + h->parts[4].start;
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rtl8380_sds5_fiber_6275b = (void *)h + sizeof(struct fw_header) + h->parts[5].start;
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rtl8380_sds_reset = (void *)h + sizeof(struct fw_header) + h->parts[6].start;
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rtl8380_sds_release_reset = (void *)h + sizeof(struct fw_header) + h->parts[7].start;
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// Back up serdes power off value
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sds_conf_value = sw_r32(RTL838X_SDS_CFG_REG);
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pr_info("SDS power down value: %x\n", sds_conf_value);
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// take serdes into reset
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i = 0;
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while (rtl8380_sds_take_reset[2 * i]) {
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sw_w32(rtl8380_sds_take_reset[2 * i + 1], rtl8380_sds_take_reset[2 * i]);
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i++;
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udelay(1000);
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}
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// apply common serdes patch
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i = 0;
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while (rtl8380_sds_common[2 * i]) {
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sw_w32(rtl8380_sds_common[2 * i + 1], rtl8380_sds_common[2 * i]);
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i++;
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udelay(1000);
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}
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// internal R/W enable
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sw_w32(3, RTL838X_INT_RW_CTRL);
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// SerDes ports 4 and 5 are FIBRE ports
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sw_w32_mask(0x7 | 0x38, 1 | (1 << 3), RTL838X_INT_MODE_CTRL);
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// SerDes module settings, SerDes 0-3 are QSGMII
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v = 0x6 << 25 | 0x6 << 20 | 0x6 << 15 | 0x6 << 10;
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// SerDes 4 and 5 are 1000BX FIBRE
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v |= 0x4 << 5 | 0x4;
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sw_w32(v, RTL838X_SDS_MODE_SEL);
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pr_info("PLL control register: %x\n", sw_r32(RTL838X_PLL_CML_CTRL));
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sw_w32_mask(0xfffffff0, 0xaaaaaaaf & 0xf, RTL838X_PLL_CML_CTRL);
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i = 0;
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while (rtl8380_sds01_qsgmii_6275b[2 * i]) {
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sw_w32(rtl8380_sds01_qsgmii_6275b[2 * i + 1],
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rtl8380_sds01_qsgmii_6275b[2 * i]);
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i++;
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}
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i = 0;
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while (rtl8380_sds23_qsgmii_6275b[2 * i]) {
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sw_w32(rtl8380_sds23_qsgmii_6275b[2 * i + 1], rtl8380_sds23_qsgmii_6275b[2 * i]);
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i++;
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}
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i = 0;
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while (rtl8380_sds4_fiber_6275b[2 * i]) {
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sw_w32(rtl8380_sds4_fiber_6275b[2 * i + 1], rtl8380_sds4_fiber_6275b[2 * i]);
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i++;
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}
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i = 0;
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while (rtl8380_sds5_fiber_6275b[2 * i]) {
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sw_w32(rtl8380_sds5_fiber_6275b[2 * i + 1], rtl8380_sds5_fiber_6275b[2 * i]);
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i++;
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}
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i = 0;
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while (rtl8380_sds_reset[2 * i]) {
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sw_w32(rtl8380_sds_reset[2 * i + 1], rtl8380_sds_reset[2 * i]);
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i++;
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}
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i = 0;
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while (rtl8380_sds_release_reset[2 * i]) {
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sw_w32(rtl8380_sds_release_reset[2 * i + 1], rtl8380_sds_release_reset[2 * i]);
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i++;
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}
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pr_info("SDS power down value now: %x\n", sw_r32(RTL838X_SDS_CFG_REG));
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sw_w32(sds_conf_value, RTL838X_SDS_CFG_REG);
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pr_info("Configuration of SERDES done\n");
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return 0;
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}
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static void rtl83xx_config_interface(int port, phy_interface_t interface)
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{
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u32 old, int_shift, sds_shift;
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switch (port) {
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case 24:
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int_shift = 0;
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sds_shift = 5;
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break;
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case 26:
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int_shift = 3;
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sds_shift = 0;
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break;
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default:
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return;
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}
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old = sw_r32(RTL838X_SDS_MODE_SEL);
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switch (interface) {
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case PHY_INTERFACE_MODE_1000BASEX:
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if ((old >> sds_shift & 0x1f) == 4)
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return;
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sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
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sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
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break;
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case PHY_INTERFACE_MODE_SGMII:
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if ((old >> sds_shift & 0x1f) == 2)
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return;
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sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
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sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
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break;
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default:
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return;
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}
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pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
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}
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*/
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/* RTL930X */
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/* The access registers for SDS_MODE_SEL and the LSB for each SDS within */
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