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realtek: fix stall after restart of otto timer
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Once tested this will go upstream. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Link: https://github.com/openwrt/openwrt/pull/19468 Signed-off-by: Robert Marko <robimarko@gmail.com>
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Markus Stockhausen
Robert Marko
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1 changed files with 146 additions and 0 deletions
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From: Markus Stockhausen <markus.stockhausen@gmx.de>
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Date: Sat, 19 Jul 2025 18:22:21 +0200
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Subject: [PATCH] realtek: fix stall after restart of otto timer
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With kernel 6.9 the kernel scheduler has been redesigned. This uncovered
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a bug in the realtek timer hardware and a misconception in the driver.
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Regarding the driver: Software cannot set the current counter value to
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zero directly. This is automatically done when writing a new target value.
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Drop function rttm_set_counter(). Additionally do not use stop timer
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during normal operation because it acknowledges interrupts. This should
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only be done from the interrupt handler. Replace this with disable_timer().
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Regarding the hardware: There is a minimal chance that a timer dies if it
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is reprogrammed within the 5us before its expiration time. Let's call this
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the "critical time window". Work around this issue by introducing a
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bounce() function. It restarts the timer directly before the normal
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restart functions as follows:
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- Stop timer
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- Restart timer with a slow frequency.
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- Target time will be >5us
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- The subsequent normal restart will be outside the critical window
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While we are here clarify documentation and double the timer frequency to
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6.25 Mhz. This allows for more detailed timestamps.
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Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
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---
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--- a/drivers/clocksource/timer-rtl-otto.c
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+++ b/drivers/clocksource/timer-rtl-otto.c
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@@ -25,12 +25,11 @@
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/*
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* The Otto platform provides multiple 28 bit timers/counters with the following
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- * operating logic. If enabled the timer counts up. Per timer one can set a
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- * maximum counter value as an end marker. If end marker is reached the timer
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- * fires an interrupt. If the timer "overflows" by reaching the end marker or
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- * by adding 1 to 0x0fffffff the counter is reset to 0. When this happens and
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- * the timer is in operating mode COUNTER it stops. In mode TIMER it will
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- * continue to count up.
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+ * operating logic. If enabled the timer counts up. Per timer a counter target
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+ * value can be set with the minimum being 0x2 and the maximumu being 0xfffffff.
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+ * If the the target value is reached the timer is reset to 0. Depending on its
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+ * configuration the timer will then fire an interrupt. In case the timer is in
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+ * operating mode COUNTER it stops. In mode TIMER it will continue to count up.
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*/
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#define RTTM_CTRL_COUNTER 0
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#define RTTM_CTRL_TIMER BIT(24)
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@@ -38,16 +37,15 @@
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#define RTTM_BIT_COUNT 28
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#define RTTM_MIN_DELTA 8
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#define RTTM_MAX_DELTA CLOCKSOURCE_MASK(28)
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+#define RTTM_MAX_DIVISOR GENMASK(15, 0)
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/*
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- * Timers are derived from the LXB clock frequency. Usually this is a fixed
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- * multiple of the 25 MHz oscillator. The 930X SOC is an exception from that.
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- * Its LXB clock has only dividers and uses the switch PLL of 2.45 GHz as its
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- * base. The only meaningful frequencies we can achieve from that are 175.000
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- * MHz and 153.125 MHz. The greatest common divisor of all explained possible
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- * speeds is 3125000. Pin the timers to this 3.125 MHz reference frequency.
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+ * Timers are derived from the lexra bus (LXB) clock frequency. This is 175 MHz
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+ * on RTL930x and 200 MHz on the other platforms. With 6.25 MHz choose a common
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+ * divisor to have enough range and detail. This even allows to compare the
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+ * different platforms more easily.
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*/
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-#define RTTM_TICKS_PER_SEC 3125000
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+#define RTTM_TICKS_PER_SEC 6250000
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struct rttm_cs {
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struct timer_of to;
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@@ -55,11 +53,6 @@ struct rttm_cs {
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};
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/* Simple internal register functions */
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-static inline void rttm_set_counter(void __iomem *base, unsigned int counter)
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-{
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- iowrite32(counter, base + RTTM_CNT);
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-}
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-
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static inline unsigned int rttm_get_counter(void __iomem *base)
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{
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return ioread32(base + RTTM_CNT);
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@@ -112,6 +105,22 @@ static irqreturn_t rttm_timer_interrupt(
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return IRQ_HANDLED;
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}
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+static void rttm_bounce_timer(void __iomem *base, u32 mode)
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+{
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+ /*
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+ * When a running timer has less than ~5us left, a stop/start sequence
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+ * might fail. While the details are unknown the most evident effect is
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+ * that the subsequent interrupt will not be fired.
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+ *
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+ * As a workaround issue an intermediate restart with a very slow
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+ * frequency of ~3kHz keeping the target value. So the actual follow
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+ * up restart will always be issued outside the critical window.
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+ */
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+
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+ rttm_disable_timer(base);
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+ rttm_enable_timer(base, mode, RTTM_MAX_DIVISOR);
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+}
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+
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static void rttm_stop_timer(void __iomem *base)
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{
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rttm_disable_timer(base);
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@@ -120,7 +129,6 @@ static void rttm_stop_timer(void __iomem
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static void rttm_start_timer(struct timer_of *to, u32 mode)
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{
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- rttm_set_counter(to->of_base.base, 0);
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rttm_enable_timer(to->of_base.base, mode, to->of_clk.rate / RTTM_TICKS_PER_SEC);
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}
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@@ -129,7 +137,8 @@ static int rttm_next_event(unsigned long
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struct timer_of *to = to_timer_of(clkevt);
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RTTM_DEBUG(to->of_base.base);
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- rttm_stop_timer(to->of_base.base);
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+ rttm_bounce_timer(to->of_base.base, RTTM_CTRL_COUNTER);
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+ rttm_disable_timer(to->of_base.base);
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rttm_set_period(to->of_base.base, delta);
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rttm_start_timer(to, RTTM_CTRL_COUNTER);
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@@ -141,7 +150,8 @@ static int rttm_state_oneshot(struct clo
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struct timer_of *to = to_timer_of(clkevt);
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RTTM_DEBUG(to->of_base.base);
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- rttm_stop_timer(to->of_base.base);
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+ rttm_bounce_timer(to->of_base.base, RTTM_CTRL_COUNTER);
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+ rttm_disable_timer(to->of_base.base);
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rttm_set_period(to->of_base.base, RTTM_TICKS_PER_SEC / HZ);
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rttm_start_timer(to, RTTM_CTRL_COUNTER);
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@@ -153,7 +163,8 @@ static int rttm_state_periodic(struct cl
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struct timer_of *to = to_timer_of(clkevt);
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RTTM_DEBUG(to->of_base.base);
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- rttm_stop_timer(to->of_base.base);
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+ rttm_bounce_timer(to->of_base.base, RTTM_CTRL_TIMER);
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+ rttm_disable_timer(to->of_base.base);
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rttm_set_period(to->of_base.base, RTTM_TICKS_PER_SEC / HZ);
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rttm_start_timer(to, RTTM_CTRL_TIMER);
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