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realtek: pcs: make rtl930x CMU config generic
Generalize the RTL930x CMU configuration to support RTL931x as well. Both implementations differ only in minor details, allowing them to share common code and avoid duplication. Affected functions are moved up in the code to the 93xx common area and slightly renamed. Existing variant-specific functions are adjusted too and assigned to the previously added SerDes operation hooks. Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com> Link: https://github.com/openwrt/openwrt/pull/22198 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Jonas Jelonek
Hauke Mehrtens
parent
8e29b78726
commit
eccb5c6fa1
1 changed files with 137 additions and 137 deletions
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@ -1119,6 +1119,135 @@ static int rtpcs_93xx_init_serdes_common(struct rtpcs_ctrl *ctrl)
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return 0;
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}
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static int rtpcs_93xx_sds_get_pll_config(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll,
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enum rtpcs_sds_pll_speed *speed)
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{
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struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds);
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int sbit, speed_val;
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/*
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* PLL config is shared between adjacent SerDes in the even lane. Each SerDes defines
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* what PLL it needs (ring or LC) while the PLL itself stores the current speed.
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*/
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sbit = pll == RTPCS_SDS_PLL_TYPE_LC ? 8 : 12;
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speed_val = rtpcs_sds_read_bits(even_sds, 0x20, 0x12, sbit + 3, sbit);
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if (speed_val < 0)
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return speed_val;
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/* bit 0 is force-bit, bits [3:1] are speed selector */
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*speed = (enum rtpcs_sds_pll_speed)(speed_val >> 1);
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return 0;
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}
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static int rtpcs_93xx_sds_set_pll_config(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll,
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enum rtpcs_sds_pll_speed speed)
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{
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struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds);
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int sbit = pll == RTPCS_SDS_PLL_TYPE_LC ? 8 : 12;
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int ret;
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if (speed >= RTPCS_SDS_PLL_SPD_END)
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return -EINVAL;
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if (pll >= RTPCS_SDS_PLL_TYPE_END)
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return -EINVAL;
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if ((pll == RTPCS_SDS_PLL_TYPE_RING) && (speed == RTPCS_SDS_PLL_SPD_10000))
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return -EINVAL;
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/*
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* A SerDes clock can either be taken from the low speed ring PLL or the high speed
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* LC PLL. As it is unclear if disabling PLLs has any positive or negative effect,
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* always activate both.
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*/
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ret = rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 3, 0, 0xf);
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if (ret < 0)
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return ret;
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/* bit 0 is force-bit, bits [3:1] are speed selector */
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ret = rtpcs_sds_write_bits(even_sds, 0x20, 0x12, sbit + 3, sbit, (speed << 1) | BIT(0));
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if (ret < 0)
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return ret;
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if (sds->ops->reset_cmu)
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ret = sds->ops->reset_cmu(sds, pll);
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return ret;
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}
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static int rtpcs_93xx_sds_config_cmu(struct rtpcs_serdes *sds, enum rtpcs_sds_mode hw_mode)
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{
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struct rtpcs_serdes *nb_sds = rtpcs_sds_get_neighbor(sds);
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enum rtpcs_sds_pll_speed speed, neighbor_speed;
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enum rtpcs_sds_pll_type pll, neighbor_pll;
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bool speed_changed = true;
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int ret;
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/*
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* A SerDes pair on the RTL930x is driven by two PLLs. A low speed ring PLL can generate
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* signals of 1.25G and 3.125G for link speeds of 1G/2.5G. A high speed LC PLL can
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* additionally generate a 10.3125G signal for 10G speeds. To drive the pair at different
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* speeds each SerDes must use its own PLL. But what if the SerDess attached to the ring
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* PLL suddenly needs 10G but the LC PLL is running at 1G? To avoid reconfiguring the
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* "partner" SerDes we must choose wisely what assignment serves the current needs. The
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* logic boils down to the following rules:
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*
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* - Use ring PLL for slow 1G speeds
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* - Use LC PLL for fast 10G speeds
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* - For 2.5G prefer ring over LC PLL
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*
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* However, when we want to configure 10G speed while the other SerDes is already using
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* the LC PLL for a slower speed, there is no way to avoid reconfiguration. Note that
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* this can even happen when the other SerDes is not actually in use, because changing
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* the state of a SerDes back to RTL930X_SDS_OFF is not (yet) implemented.
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*/
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ret = nb_sds->ops->get_pll_select(nb_sds, &neighbor_pll);
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if (ret < 0)
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return ret;
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ret = rtpcs_93xx_sds_get_pll_config(nb_sds, neighbor_pll, &neighbor_speed);
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if (ret < 0)
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return ret;
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ret = rtpcs_sds_select_pll_speed(hw_mode, &speed);
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if (ret < 0)
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return ret;
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if (nb_sds->hw_mode == RTPCS_SDS_MODE_OFF)
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pll = speed == RTPCS_SDS_PLL_SPD_10000 ? RTPCS_SDS_PLL_TYPE_LC
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: RTPCS_SDS_PLL_TYPE_RING;
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else if (speed == neighbor_speed) {
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speed_changed = false;
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pll = neighbor_pll;
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} else if (neighbor_pll == RTPCS_SDS_PLL_TYPE_RING)
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pll = RTPCS_SDS_PLL_TYPE_LC;
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else if (speed == RTPCS_SDS_PLL_SPD_10000) {
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pr_info("%s: SDS %d needs LC PLL, reconfigure SDS %d to use ring PLL\n",
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__func__, sds->id, nb_sds->id);
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ret = nb_sds->ops->reconfigure_to_pll(nb_sds, RTPCS_SDS_PLL_TYPE_RING);
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if (ret < 0)
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return ret;
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pll = RTPCS_SDS_PLL_TYPE_LC;
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} else
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pll = RTPCS_SDS_PLL_TYPE_RING;
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if (speed_changed)
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ret = rtpcs_93xx_sds_set_pll_config(sds, pll, speed);
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ret = sds->ops->set_pll_select(sds, hw_mode, pll);
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if (ret < 0)
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return ret;
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pr_info("%s: SDS %d using %s PLL for mode %d\n", __func__, sds->id,
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pll == RTPCS_SDS_PLL_TYPE_LC ? "LC" : "ring", hw_mode);
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return ret;
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}
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/* RTL930X */
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/*
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@ -1290,27 +1419,6 @@ static int rtpcs_930x_sds_get_pll_select(struct rtpcs_serdes *sds, enum rtpcs_sd
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return 0;
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}
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static int rtpcs_930x_sds_get_pll_config(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll,
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enum rtpcs_sds_pll_speed *speed)
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{
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struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds);
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int sbit, speed_val;
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/*
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* PLL data is shared between adjacent SerDes in the even lane. Each SerDes defines
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* what PLL it needs (ring or LC) while the PLL itself stores the current speed.
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*/
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sbit = pll == RTPCS_SDS_PLL_TYPE_LC ? 8 : 12;
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speed_val = rtpcs_sds_read_bits(even_sds, 0x20, 0x12, sbit + 3, sbit);
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if (speed_val < 0)
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return speed_val;
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/* bit 0 is force-bit, bits [3:1] are speed selector */
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*speed = (enum rtpcs_sds_pll_speed)(speed_val >> 1);
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return 0;
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}
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static int rtpcs_930x_sds_set_pll_select(struct rtpcs_serdes *sds, enum rtpcs_sds_mode hw_mode,
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enum rtpcs_sds_pll_type pll)
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{
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@ -1323,11 +1431,10 @@ static int rtpcs_930x_sds_set_pll_select(struct rtpcs_serdes *sds, enum rtpcs_sd
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return rtpcs_sds_write_bits(even_sds, 0x20, 0x12, pbit + 1, pbit, (pll << 1) | BIT(0));
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}
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static int rtpcs_930x_sds_reset_cmu(struct rtpcs_serdes *sds)
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static int rtpcs_930x_sds_reset_cmu(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll)
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{
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struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds);
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int reset_sequence[4] = { 3, 2, 3, 1 };
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enum rtpcs_sds_pll_type pll;
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int bit, i, ret;
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/*
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@ -1335,9 +1442,6 @@ static int rtpcs_930x_sds_reset_cmu(struct rtpcs_serdes *sds)
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* of the Otto platform have different reset sequences. Luckily it always boils down
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* to flipping two bits in a special sequence.
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*/
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ret = rtpcs_930x_sds_get_pll_select(sds, &pll);
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if (ret < 0)
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return ret;
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bit = pll == RTPCS_SDS_PLL_TYPE_LC ? 2 : 0;
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@ -1350,40 +1454,6 @@ static int rtpcs_930x_sds_reset_cmu(struct rtpcs_serdes *sds)
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return 0;
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}
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static int rtpcs_930x_sds_set_pll_config(struct rtpcs_serdes *sds, enum rtpcs_sds_pll_type pll,
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enum rtpcs_sds_pll_speed speed)
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{
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struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds);
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int sbit = pll == RTPCS_SDS_PLL_TYPE_LC ? 8 : 12;
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int ret;
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if (speed >= RTPCS_SDS_PLL_SPD_END)
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return -EINVAL;
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if (pll >= RTPCS_SDS_PLL_TYPE_END)
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return -EINVAL;
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if ((pll == RTPCS_SDS_PLL_TYPE_RING) && (speed == RTPCS_SDS_PLL_SPD_10000))
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return -EINVAL;
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/*
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* A SerDes clock can either be taken from the low speed ring PLL or the high speed
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* LC PLL. As it is unclear if disabling PLLs has any positive or negative effect,
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* always activate both.
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*/
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ret = rtpcs_sds_write_bits(even_sds, 0x20, 0x12, 3, 0, 0xf);
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if (ret < 0)
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return ret;
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/* bit 0 is force-bit, bits [3:1] are speed selector */
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ret = rtpcs_sds_write_bits(even_sds, 0x20, 0x12, sbit + 3, sbit, (speed << 1) | BIT(0));
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if (ret < 0)
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return ret;
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return rtpcs_930x_sds_reset_cmu(sds);
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}
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static int rtpcs_930x_sds_wait_clock_ready(struct rtpcs_serdes *sds)
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{
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struct rtpcs_serdes *even_sds = rtpcs_sds_get_even(sds);
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@ -1441,14 +1511,14 @@ static int rtpcs_930x_sds_reconfigure_to_pll(struct rtpcs_serdes *sds, enum rtpc
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if (ret < 0)
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return ret;
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ret = rtpcs_930x_sds_get_pll_config(sds, old_pll, &speed);
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ret = rtpcs_93xx_sds_get_pll_config(sds, old_pll, &speed);
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if (ret < 0)
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return ret;
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rtpcs_930x_sds_set_power(sds, false);
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__rtpcs_930x_sds_set_ip_mode(sds, RTPCS_930X_SDS_OFF);
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ret = rtpcs_930x_sds_set_pll_config(sds, pll, speed);
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ret = rtpcs_93xx_sds_set_pll_config(sds, pll, speed);
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if (ret < 0)
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return ret;
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@ -1464,80 +1534,6 @@ static int rtpcs_930x_sds_reconfigure_to_pll(struct rtpcs_serdes *sds, enum rtpc
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return 0;
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}
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static int rtpcs_930x_sds_config_cmu(struct rtpcs_serdes *sds,
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enum rtpcs_sds_mode hw_mode)
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{
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struct rtpcs_serdes *nb_sds = rtpcs_sds_get_neighbor(sds);
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enum rtpcs_sds_pll_speed speed, neighbor_speed;
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enum rtpcs_sds_pll_type pll, neighbor_pll;
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bool speed_changed = true;
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int neighbor_mode, ret;
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/*
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* A SerDes pair on the RTL930x is driven by two PLLs. A low speed ring PLL can generate
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* signals of 1.25G and 3.125G for link speeds of 1G/2.5G. A high speed LC PLL can
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* additionally generate a 10.3125G signal for 10G speeds. To drive the pair at different
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* speeds each SerDes must use its own PLL. But what if the SerDess attached to the ring
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* PLL suddenly needs 10G but the LC PLL is running at 1G? To avoid reconfiguring the
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* "partner" SerDes we must choose wisely what assignment serves the current needs. The
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* logic boils down to the following rules:
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*
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* - Use ring PLL for slow 1G speeds
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* - Use LC PLL for fast 10G speeds
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* - For 2.5G prefer ring over LC PLL
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*
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* However, when we want to configure 10G speed while the other SerDes is already using
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* the LC PLL for a slower speed, there is no way to avoid reconfiguration. Note that
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* this can even happen when the other SerDes is not actually in use, because changing
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* the state of a SerDes back to RTL930X_SDS_OFF is not (yet) implemented.
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*/
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neighbor_mode = __rtpcs_930x_sds_get_ip_mode(nb_sds);
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ret = rtpcs_930x_sds_get_pll_select(sds, &neighbor_pll);
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if (ret < 0)
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return ret;
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ret = rtpcs_930x_sds_get_pll_config(nb_sds, neighbor_pll, &neighbor_speed);
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if (ret < 0)
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return ret;
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ret = rtpcs_sds_select_pll_speed(hw_mode, &speed);
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if (ret < 0)
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return ret;
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if (!neighbor_mode)
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pll = speed == RTPCS_SDS_PLL_SPD_10000 ? RTPCS_SDS_PLL_TYPE_LC
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: RTPCS_SDS_PLL_TYPE_RING;
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else if (speed == neighbor_speed) {
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speed_changed = false;
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pll = neighbor_pll;
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} else if (neighbor_pll == RTPCS_SDS_PLL_TYPE_RING)
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pll = RTPCS_SDS_PLL_TYPE_LC;
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else if (speed == RTPCS_SDS_PLL_SPD_10000) {
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pr_info("%s: SDS %d needs LC PLL, reconfigure SDS %d to use ring PLL\n",
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__func__, sds->id, nb_sds->id);
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ret = rtpcs_930x_sds_reconfigure_to_pll(nb_sds, RTPCS_SDS_PLL_TYPE_RING);
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if (ret < 0)
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return ret;
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pll = RTPCS_SDS_PLL_TYPE_LC;
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} else
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pll = RTPCS_SDS_PLL_TYPE_RING;
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if (speed_changed)
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ret = rtpcs_930x_sds_set_pll_config(sds, pll, speed);
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ret = rtpcs_930x_sds_set_pll_select(sds, hw_mode, pll);
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if (ret < 0)
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return ret;
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pr_info("%s: SDS %d using %s PLL for mode %d\n", __func__, sds->id,
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pll == RTPCS_SDS_PLL_TYPE_LC ? "LC" : "ring", hw_mode);
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return ret;
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}
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static void rtpcs_930x_sds_reset_state_machine(struct rtpcs_serdes *sds)
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{
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rtpcs_sds_write_bits(sds, 0x06, 0x02, 12, 12, 0x01); /* SM_RESET bit */
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@ -1627,7 +1623,7 @@ static int rtpcs_930x_sds_set_ip_mode(struct rtpcs_serdes *sds,
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if (hw_mode == RTPCS_SDS_MODE_OFF)
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return 0;
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ret = rtpcs_930x_sds_config_cmu(sds, hw_mode);
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ret = rtpcs_93xx_sds_config_cmu(sds, hw_mode);
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if (ret < 0)
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pr_err("%s: SDS %d could not configure PLL for mode %d: %d\n", __func__,
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sds->id, hw_mode, ret);
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@ -4300,6 +4296,10 @@ static const struct rtpcs_serdes_ops rtpcs_930x_sds_ops = {
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.xsg_write = rtpcs_930x_sds_op_xsg_write,
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.set_autoneg = rtpcs_93xx_sds_set_autoneg,
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.restart_autoneg = rtpcs_generic_sds_restart_autoneg,
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.get_pll_select = rtpcs_930x_sds_get_pll_select,
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.set_pll_select = rtpcs_930x_sds_set_pll_select,
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.reset_cmu = rtpcs_930x_sds_reset_cmu,
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.reconfigure_to_pll = rtpcs_930x_sds_reconfigure_to_pll,
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};
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static const struct rtpcs_sds_regs rtpcs_930x_sds_regs = {
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