mirror/openwrt
1
0
Fork 1
mirror of https://git.openwrt.org/openwrt/openwrt.git synced 2025-12-10 08:44:39 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

realtek: rtl838x: setup SDS entirely in PCS driver

Browse source 
After having moved the configuration code and sequences from PHY and
DSA drivers to the PCS driver, add the hooks in PCS driver and remove
calls in PHY and DSA drivers to let PCS driver setup the SerDes
entirely on its own.

Also add pcs-handle to device tree definitions for most of the switch
ports because, due to the refactoring of the SerDes configuration, this
is needed now for all SerDes-attached ports.

Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/20876
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Jonas Jelonek 2025-11-07 16:15:17 +00:00 • committed by Hauke Mehrtens
parent b670d48366
commit e956adfe3e
25 changed files with 319 additions and 279 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

13
target/linux/realtek/dts/rtl8380_netgear_gs110tup-v1.dts
View file

@ -53,7 +53,18 @@
&switch0 { &switch0 {
ports { ports {
SWITCH_PORT(16, 9, qsgmii) SWITCH_PORT(16, 9, qsgmii)
/* TODO: fixed link SFP is not right */ /* TODO: fixed link SFP is not right */
SWITCH_SFP_PORT(24, 10, rgmii-id) port24: port@24 {
reg = <24>;
label = SWITCH_PORT_LABEL(10);
pcs-handle = <&serdes4>;
phy-handle = <&phy24>;
phy-mode = "1000base-x";
fixed-link {
speed = <1000>;
full-duplex;
};
};
}; };
}; };

25
target/linux/realtek/dts/rtl8380_netgear_gs310tp-v1.dts
View file

@ -57,7 +57,28 @@
&switch0 { &switch0 {
ports { ports {
/* TODO: fixed link SFP is not right */ /* TODO: fixed link SFP is not right */
SWITCH_SFP_PORT(24, 9, 1000base-x)
SWITCH_SFP_PORT(26, 10, 1000base-x) port24: port@24 {
reg = <24>;
label = SWITCH_PORT_LABEL(9);
pcs-handle = <&serdes4>;
phy-handle = <&phy24>;
phy-mode = "1000base-x";
fixed-link {
speed = <1000>;
full-duplex;
};
};
port26: port@26 {
reg = <26>;
label = SWITCH_PORT_LABEL(10);
pcs-handle = <&serdes5>;
phy-handle = <&phy26>;
phy-mode = "1000base-x";
fixed-link {
speed = <1000>;
full-duplex;
};
};
}; };
}; };

24
target/linux/realtek/dts/rtl8380_tplink_sg2xxx.dtsi
View file

@ -168,8 +168,28 @@
SWITCH_PORT(8, 8, internal) SWITCH_PORT(8, 8, internal)
/* TODO: fixed link SFP is not right */ /* TODO: fixed link SFP is not right */
SWITCH_SFP_PORT(24, 9, 1000base-x) port24: port@24 {
SWITCH_SFP_PORT(26, 10, 1000base-x) reg = <24>;
label = SWITCH_PORT_LABEL(9);
pcs-handle = <&serdes4>;
phy-handle = <&phy24>;
phy-mode = "1000base-x";
fixed-link {
speed = <1000>;
full-duplex;
};
};
port26: port@26 {
reg = <26>;
label = SWITCH_PORT_LABEL(10);
pcs-handle = <&serdes5>;
phy-handle = <&phy26>;
phy-mode = "1000base-x";
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@28 { port@28 {
ethernet = <&ethernet0>; ethernet = <&ethernet0>;

24
target/linux/realtek/dts/rtl8382_apresia_aplgs120gtss.dts
View file

@ -229,14 +229,14 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
SWITCH_PORT(0, 1, qsgmii) SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT(1, 2, qsgmii) SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT(2, 3, qsgmii) SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT(3, 4, qsgmii) SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT(4, 5, qsgmii) SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT(5, 6, qsgmii) SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT(6, 7, qsgmii) SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT(7, 8, qsgmii) SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT(8, 9, internal) SWITCH_PORT(8, 9, internal)
SWITCH_PORT(9, 10, internal) SWITCH_PORT(9, 10, internal)
@ -247,10 +247,10 @@
SWITCH_PORT(14, 15, internal) SWITCH_PORT(14, 15, internal)
SWITCH_PORT(15, 16, internal) SWITCH_PORT(15, 16, internal)
SWITCH_PORT(24, 17, qsgmii) SWITCH_PORT_SDS(24, 17, 4, qsgmii)
SWITCH_PORT(25, 18, qsgmii) SWITCH_PORT_SDS(25, 18, 4, qsgmii)
SWITCH_PORT(26, 19, qsgmii) SWITCH_PORT_SDS(26, 19, 4, qsgmii)
SWITCH_PORT(27, 20, qsgmii) SWITCH_PORT_SDS(27, 20, 4, qsgmii)
port@28 { port@28 {
ethernet = <&ethernet0>; ethernet = <&ethernet0>;

24
target/linux/realtek/dts/rtl8382_d-link_dgs-1210-16.dts
View file

@ -39,14 +39,14 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
SWITCH_PORT(0, 1, qsgmii) SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT(1, 2, qsgmii) SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT(2, 3, qsgmii) SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT(3, 4, qsgmii) SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT(4, 5, qsgmii) SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT(5, 6, qsgmii) SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT(6, 7, qsgmii) SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT(7, 8, qsgmii) SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT(8, 9, internal) SWITCH_PORT(8, 9, internal)
SWITCH_PORT(9, 10, internal) SWITCH_PORT(9, 10, internal)
@ -57,10 +57,10 @@
SWITCH_PORT(14, 15, internal) SWITCH_PORT(14, 15, internal)
SWITCH_PORT(15, 16, internal) SWITCH_PORT(15, 16, internal)
SWITCH_PORT(24, 17, qsgmii) SWITCH_PORT_SDS(24, 17, 4, qsgmii)
SWITCH_PORT(25, 18, qsgmii) SWITCH_PORT_SDS(25, 18, 4, qsgmii)
SWITCH_PORT(26, 19, qsgmii) SWITCH_PORT_SDS(26, 19, 4, qsgmii)
SWITCH_PORT(27, 20, qsgmii) SWITCH_PORT_SDS(27, 20, 4, qsgmii)
port@28 { port@28 {
ethernet = <&ethernet0>; ethernet = <&ethernet0>;

24
target/linux/realtek/dts/rtl8382_d-link_dgs-1210-20.dts
View file

@ -39,14 +39,14 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
SWITCH_PORT(0, 1, qsgmii) SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT(1, 2, qsgmii) SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT(2, 3, qsgmii) SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT(3, 4, qsgmii) SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT(4, 5, qsgmii) SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT(5, 6, qsgmii) SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT(6, 7, qsgmii) SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT(7, 8, qsgmii) SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT(8, 9, internal) SWITCH_PORT(8, 9, internal)
SWITCH_PORT(9, 10, internal) SWITCH_PORT(9, 10, internal)
@ -57,10 +57,10 @@
SWITCH_PORT(14, 15, internal) SWITCH_PORT(14, 15, internal)
SWITCH_PORT(15, 16, internal) SWITCH_PORT(15, 16, internal)
SWITCH_PORT(24, 17, qsgmii) SWITCH_PORT_SDS(24, 17, 4, qsgmii)
SWITCH_PORT(25, 18, qsgmii) SWITCH_PORT_SDS(25, 18, 4, qsgmii)
SWITCH_PORT(26, 19, qsgmii) SWITCH_PORT_SDS(26, 19, 4, qsgmii)
SWITCH_PORT(27, 20, qsgmii) SWITCH_PORT_SDS(27, 20, 4, qsgmii)
port@28 { port@28 {
ethernet = <&ethernet0>; ethernet = <&ethernet0>;

32
target/linux/realtek/dts/rtl8382_d-link_dgs-1210-26.dts
View file

@ -82,14 +82,14 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
SWITCH_PORT(0, 1, qsgmii) SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT(1, 2, qsgmii) SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT(2, 3, qsgmii) SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT(3, 4, qsgmii) SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT(4, 5, qsgmii) SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT(5, 6, qsgmii) SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT(6, 7, qsgmii) SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT(7, 8, qsgmii) SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT(8, 9, internal) SWITCH_PORT(8, 9, internal)
SWITCH_PORT(9, 10, internal) SWITCH_PORT(9, 10, internal)
@ -100,14 +100,14 @@
SWITCH_PORT(14, 15, internal) SWITCH_PORT(14, 15, internal)
SWITCH_PORT(15, 16, internal) SWITCH_PORT(15, 16, internal)
SWITCH_PORT(16, 17, qsgmii) SWITCH_PORT_SDS(16, 17, 2, qsgmii)
SWITCH_PORT(17, 18, qsgmii) SWITCH_PORT_SDS(17, 18, 2, qsgmii)
SWITCH_PORT(18, 19, qsgmii) SWITCH_PORT_SDS(18, 19, 2, qsgmii)
SWITCH_PORT(19, 20, qsgmii) SWITCH_PORT_SDS(19, 20, 2, qsgmii)
SWITCH_PORT(20, 21, qsgmii) SWITCH_PORT_SDS(20, 21, 3, qsgmii)
SWITCH_PORT(21, 22, qsgmii) SWITCH_PORT_SDS(21, 22, 3, qsgmii)
SWITCH_PORT(22, 23, qsgmii) SWITCH_PORT_SDS(22, 23, 3, qsgmii)
SWITCH_PORT(23, 24, qsgmii) SWITCH_PORT_SDS(23, 24, 3, qsgmii)
port@24 { port@24 {
reg = <24>; reg = <24>;

40
target/linux/realtek/dts/rtl8382_d-link_dgs-1210-28_common.dtsi
View file

@ -40,14 +40,14 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
SWITCH_PORT(0, 1, qsgmii) SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT(1, 2, qsgmii) SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT(2, 3, qsgmii) SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT(3, 4, qsgmii) SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT(4, 5, qsgmii) SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT(5, 6, qsgmii) SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT(6, 7, qsgmii) SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT(7, 8, qsgmii) SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT(8, 9, internal) SWITCH_PORT(8, 9, internal)
SWITCH_PORT(9, 10, internal) SWITCH_PORT(9, 10, internal)
@ -58,19 +58,19 @@
SWITCH_PORT(14, 15, internal) SWITCH_PORT(14, 15, internal)
SWITCH_PORT(15, 16, internal) SWITCH_PORT(15, 16, internal)
SWITCH_PORT(16, 17, qsgmii) SWITCH_PORT_SDS(16, 17, 2, qsgmii)
SWITCH_PORT(17, 18, qsgmii) SWITCH_PORT_SDS(17, 18, 2, qsgmii)
SWITCH_PORT(18, 19, qsgmii) SWITCH_PORT_SDS(18, 19, 2, qsgmii)
SWITCH_PORT(19, 20, qsgmii) SWITCH_PORT_SDS(19, 20, 2, qsgmii)
SWITCH_PORT(20, 21, qsgmii) SWITCH_PORT_SDS(20, 21, 3, qsgmii)
SWITCH_PORT(21, 22, qsgmii) SWITCH_PORT_SDS(21, 22, 3, qsgmii)
SWITCH_PORT(22, 23, qsgmii) SWITCH_PORT_SDS(22, 23, 3, qsgmii)
SWITCH_PORT(23, 24, qsgmii) SWITCH_PORT_SDS(23, 24, 3, qsgmii)
SWITCH_PORT(24, 25, qsgmii) SWITCH_PORT_SDS(24, 25, 4, qsgmii)
SWITCH_PORT(25, 26, qsgmii) SWITCH_PORT_SDS(25, 26, 4, qsgmii)
SWITCH_PORT(26, 27, qsgmii) SWITCH_PORT_SDS(26, 27, 4, qsgmii)
SWITCH_PORT(27, 28, qsgmii) SWITCH_PORT_SDS(27, 28, 4, qsgmii)
port@28 { port@28 {
ethernet = <&ethernet0>; ethernet = <&ethernet0>;

24
target/linux/realtek/dts/rtl8382_hpe_1920-16g.dts
View file

@ -21,19 +21,19 @@
SWITCH_PORT(14, 7, internal) SWITCH_PORT(14, 7, internal)
SWITCH_PORT(15, 8, internal) SWITCH_PORT(15, 8, internal)
SWITCH_PORT(16, 9, qsgmii) SWITCH_PORT_SDS(16, 9, 2, qsgmii)
SWITCH_PORT(17, 10, qsgmii) SWITCH_PORT_SDS(17, 10, 2, qsgmii)
SWITCH_PORT(18, 11, qsgmii) SWITCH_PORT_SDS(18, 11, 2, qsgmii)
SWITCH_PORT(19, 12, qsgmii) SWITCH_PORT_SDS(19, 12, 2, qsgmii)
SWITCH_PORT(20, 13, qsgmii) SWITCH_PORT_SDS(20, 13, 3, qsgmii)
SWITCH_PORT(21, 14, qsgmii) SWITCH_PORT_SDS(21, 14, 3, qsgmii)
SWITCH_PORT(22, 15, qsgmii) SWITCH_PORT_SDS(22, 15, 3, qsgmii)
SWITCH_PORT(23, 16, qsgmii) SWITCH_PORT_SDS(23, 16, 3, qsgmii)
SWITCH_PORT(24, 17, qsgmii) SWITCH_PORT_SDS(24, 17, 4, qsgmii)
SWITCH_PORT(25, 18, qsgmii) SWITCH_PORT_SDS(25, 18, 4, qsgmii)
SWITCH_PORT(26, 19, qsgmii) SWITCH_PORT_SDS(26, 19, 4, qsgmii)
SWITCH_PORT(27, 20, qsgmii) SWITCH_PORT_SDS(27, 20, 4, qsgmii)
port@28 { port@28 {
ethernet = <&ethernet0>; ethernet = <&ethernet0>;

40
target/linux/realtek/dts/rtl8382_hpe_1920-24g.dtsi
View file

@ -23,14 +23,14 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
SWITCH_PORT(0, 1, qsgmii) SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT(1, 2, qsgmii) SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT(2, 3, qsgmii) SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT(3, 4, qsgmii) SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT(4, 5, qsgmii) SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT(5, 6, qsgmii) SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT(6, 7, qsgmii) SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT(7, 8, qsgmii) SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT(8, 9, internal) SWITCH_PORT(8, 9, internal)
SWITCH_PORT(9, 10, internal) SWITCH_PORT(9, 10, internal)
@ -41,19 +41,19 @@
SWITCH_PORT(14, 15, internal) SWITCH_PORT(14, 15, internal)
SWITCH_PORT(15, 16, internal) SWITCH_PORT(15, 16, internal)
SWITCH_PORT(16, 17, qsgmii) SWITCH_PORT_SDS(16, 17, 2, qsgmii)
SWITCH_PORT(17, 18, qsgmii) SWITCH_PORT_SDS(17, 18, 2, qsgmii)
SWITCH_PORT(18, 19, qsgmii) SWITCH_PORT_SDS(18, 19, 2, qsgmii)
SWITCH_PORT(19, 20, qsgmii) SWITCH_PORT_SDS(19, 20, 2, qsgmii)
SWITCH_PORT(20, 21, qsgmii) SWITCH_PORT_SDS(20, 21, 3, qsgmii)
SWITCH_PORT(21, 22, qsgmii) SWITCH_PORT_SDS(21, 22, 3, qsgmii)
SWITCH_PORT(22, 23, qsgmii) SWITCH_PORT_SDS(22, 23, 3, qsgmii)
SWITCH_PORT(23, 24, qsgmii) SWITCH_PORT_SDS(23, 24, 3, qsgmii)
SWITCH_PORT(24, 25, qsgmii) SWITCH_PORT_SDS(24, 25, 4, qsgmii)
SWITCH_PORT(25, 26, qsgmii) SWITCH_PORT_SDS(25, 26, 4, qsgmii)
SWITCH_PORT(26, 27, qsgmii) SWITCH_PORT_SDS(26, 27, 4, qsgmii)
SWITCH_PORT(27, 28, qsgmii) SWITCH_PORT_SDS(27, 28, 4, qsgmii)
port@28 { port@28 {
ethernet = <&ethernet0>; ethernet = <&ethernet0>;

16
target/linux/realtek/dts/rtl8382_inaba_aml2-17gp.dts
View file

@ -121,14 +121,14 @@
SWITCH_PORT(14, 7, internal) SWITCH_PORT(14, 7, internal)
SWITCH_PORT(15, 8, internal) SWITCH_PORT(15, 8, internal)
SWITCH_PORT(16, 9, qsgmii) SWITCH_PORT_SDS(16, 9, 2, qsgmii)
SWITCH_PORT(17, 10, qsgmii) SWITCH_PORT_SDS(17, 10, 2, qsgmii)
SWITCH_PORT(18, 11, qsgmii) SWITCH_PORT_SDS(18, 11, 2, qsgmii)
SWITCH_PORT(19, 12, qsgmii) SWITCH_PORT_SDS(19, 12, 2, qsgmii)
SWITCH_PORT(20, 13, qsgmii) SWITCH_PORT_SDS(20, 13, 3, qsgmii)
SWITCH_PORT(21, 14, qsgmii) SWITCH_PORT_SDS(21, 14, 3, qsgmii)
SWITCH_PORT(22, 15, qsgmii) SWITCH_PORT_SDS(22, 15, 3, qsgmii)
SWITCH_PORT(23, 16, qsgmii) SWITCH_PORT_SDS(23, 16, 3, qsgmii)
port@24 { port@24 {
reg = <24>; reg = <24>;

32
target/linux/realtek/dts/rtl8382_iodata_bsh-g24mb.dts
View file

@ -155,14 +155,14 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
SWITCH_PORT(0, 1, qsgmii) SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT(1, 2, qsgmii) SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT(2, 3, qsgmii) SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT(3, 4, qsgmii) SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT(4, 5, qsgmii) SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT(5, 6, qsgmii) SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT(6, 7, qsgmii) SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT(7, 8, qsgmii) SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT(8, 9, internal) SWITCH_PORT(8, 9, internal)
SWITCH_PORT(9, 10, internal) SWITCH_PORT(9, 10, internal)
@ -173,14 +173,14 @@
SWITCH_PORT(14, 15, internal) SWITCH_PORT(14, 15, internal)
SWITCH_PORT(15, 16, internal) SWITCH_PORT(15, 16, internal)
SWITCH_PORT(16, 17, qsgmii) SWITCH_PORT_SDS(16, 17, 2, qsgmii)
SWITCH_PORT(17, 18, qsgmii) SWITCH_PORT_SDS(17, 18, 2, qsgmii)
SWITCH_PORT(18, 19, qsgmii) SWITCH_PORT_SDS(18, 19, 2, qsgmii)
SWITCH_PORT(19, 20, qsgmii) SWITCH_PORT_SDS(19, 20, 2, qsgmii)
SWITCH_PORT(20, 21, qsgmii) SWITCH_PORT_SDS(20, 21, 3, qsgmii)
SWITCH_PORT(21, 22, qsgmii) SWITCH_PORT_SDS(21, 22, 3, qsgmii)
SWITCH_PORT(22, 23, qsgmii) SWITCH_PORT_SDS(22, 23, 3, qsgmii)
SWITCH_PORT(23, 24, qsgmii) SWITCH_PORT_SDS(23, 24, 3, qsgmii)
port@28 { port@28 {
ethernet = <&ethernet0>; ethernet = <&ethernet0>;

16
target/linux/realtek/dts/rtl8382_panasonic_m16eg-pn28160k.dts
View file

@ -140,14 +140,14 @@
SWITCH_PORT(14, 7, internal) SWITCH_PORT(14, 7, internal)
SWITCH_PORT(15, 8, internal) SWITCH_PORT(15, 8, internal)
SWITCH_PORT(16, 9, qsgmii) SWITCH_PORT_SDS(16, 9, 2, qsgmii)
SWITCH_PORT(17, 10, qsgmii) SWITCH_PORT_SDS(17, 10, 2, qsgmii)
SWITCH_PORT(18, 11, qsgmii) SWITCH_PORT_SDS(18, 11, 2, qsgmii)
SWITCH_PORT(19, 12, qsgmii) SWITCH_PORT_SDS(19, 12, 2, qsgmii)
SWITCH_PORT(20, 13, qsgmii) SWITCH_PORT_SDS(20, 13, 3, qsgmii)
SWITCH_PORT(21, 14, qsgmii) SWITCH_PORT_SDS(21, 14, 3, qsgmii)
SWITCH_PORT(22, 15, qsgmii) SWITCH_PORT_SDS(22, 15, 3, qsgmii)
SWITCH_PORT(23, 16, qsgmii) SWITCH_PORT_SDS(23, 16, 3, qsgmii)
port@28 { port@28 {
ethernet = <&ethernet0>; ethernet = <&ethernet0>;

32
target/linux/realtek/dts/rtl8382_panasonic_m24eg-pn28240k.dts
View file

@ -141,14 +141,14 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
SWITCH_PORT(0, 1, qsgmii) SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT(1, 2, qsgmii) SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT(2, 3, qsgmii) SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT(3, 4, qsgmii) SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT(4, 5, qsgmii) SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT(5, 6, qsgmii) SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT(6, 7, qsgmii) SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT(7, 8, qsgmii) SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT(8, 9, internal) SWITCH_PORT(8, 9, internal)
SWITCH_PORT(9, 10, internal) SWITCH_PORT(9, 10, internal)
@ -159,14 +159,14 @@
SWITCH_PORT(14, 15, internal) SWITCH_PORT(14, 15, internal)
SWITCH_PORT(15, 16, internal) SWITCH_PORT(15, 16, internal)
SWITCH_PORT(16, 17, qsgmii) SWITCH_PORT_SDS(16, 17, 2, qsgmii)
SWITCH_PORT(17, 18, qsgmii) SWITCH_PORT_SDS(17, 18, 2, qsgmii)
SWITCH_PORT(18, 19, qsgmii) SWITCH_PORT_SDS(18, 19, 2, qsgmii)
SWITCH_PORT(19, 20, qsgmii) SWITCH_PORT_SDS(19, 20, 2, qsgmii)
SWITCH_PORT(20, 21, qsgmii) SWITCH_PORT_SDS(20, 21, 3, qsgmii)
SWITCH_PORT(21, 22, qsgmii) SWITCH_PORT_SDS(21, 22, 3, qsgmii)
SWITCH_PORT(22, 23, qsgmii) SWITCH_PORT_SDS(22, 23, 3, qsgmii)
SWITCH_PORT(23, 24, qsgmii) SWITCH_PORT_SDS(23, 24, 3, qsgmii)
port@28 { port@28 {
ethernet = <&ethernet0>; ethernet = <&ethernet0>;

32
target/linux/realtek/dts/rtl8382_tplink_t1600g-28ts-v3.dts
View file

@ -128,14 +128,14 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
SWITCH_PORT(0, 1, qsgmii) SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT(1, 2, qsgmii) SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT(2, 3, qsgmii) SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT(3, 4, qsgmii) SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT(4, 5, qsgmii) SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT(5, 6, qsgmii) SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT(6, 7, qsgmii) SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT(7, 8, qsgmii) SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT(8, 9, internal) SWITCH_PORT(8, 9, internal)
SWITCH_PORT(9, 10, internal) SWITCH_PORT(9, 10, internal)
@ -146,14 +146,14 @@
SWITCH_PORT(14, 15, internal) SWITCH_PORT(14, 15, internal)
SWITCH_PORT(15, 16, internal) SWITCH_PORT(15, 16, internal)
SWITCH_PORT(16, 17, qsgmii) SWITCH_PORT_SDS(16, 17, 2, qsgmii)
SWITCH_PORT(17, 18, qsgmii) SWITCH_PORT_SDS(17, 18, 2, qsgmii)
SWITCH_PORT(18, 19, qsgmii) SWITCH_PORT_SDS(18, 19, 2, qsgmii)
SWITCH_PORT(19, 20, qsgmii) SWITCH_PORT_SDS(19, 20, 2, qsgmii)
SWITCH_PORT(20, 21, qsgmii) SWITCH_PORT_SDS(20, 21, 3, qsgmii)
SWITCH_PORT(21, 22, qsgmii) SWITCH_PORT_SDS(21, 22, 3, qsgmii)
SWITCH_PORT(22, 23, qsgmii) SWITCH_PORT_SDS(22, 23, 3, qsgmii)
SWITCH_PORT(23, 24, qsgmii) SWITCH_PORT_SDS(23, 24, 3, qsgmii)
port@28 { port@28 {
ethernet = <&ethernet0>; ethernet = <&ethernet0>;

16
target/linux/realtek/dts/rtl8382_zyxel_gs1900-16-a1.dts
View file

@ -21,14 +21,14 @@
&switch0 { &switch0 {
ports { ports {
SWITCH_PORT(16, 9, qsgmii) SWITCH_PORT_SDS(16, 9, 2, qsgmii)
SWITCH_PORT(17, 10, qsgmii) SWITCH_PORT_SDS(17, 10, 2, qsgmii)
SWITCH_PORT(18, 11, qsgmii) SWITCH_PORT_SDS(18, 11, 2, qsgmii)
SWITCH_PORT(19, 12, qsgmii) SWITCH_PORT_SDS(19, 12, 2, qsgmii)
SWITCH_PORT(20, 13, qsgmii) SWITCH_PORT_SDS(20, 13, 3, qsgmii)
SWITCH_PORT(21, 14, qsgmii) SWITCH_PORT_SDS(21, 14, 3, qsgmii)
SWITCH_PORT(22, 15, qsgmii) SWITCH_PORT_SDS(22, 15, 3, qsgmii)
SWITCH_PORT(23, 16, qsgmii) SWITCH_PORT_SDS(23, 16, 3, qsgmii)
}; };
}; };

32
target/linux/realtek/dts/rtl8382_zyxel_gs1900-24-a1.dts
View file

@ -79,14 +79,14 @@
&switch0 { &switch0 {
ports { ports {
SWITCH_PORT(0, 1, qsgmii) SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT(1, 2, qsgmii) SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT(2, 3, qsgmii) SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT(3, 4, qsgmii) SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT(4, 5, qsgmii) SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT(5, 6, qsgmii) SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT(6, 7, qsgmii) SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT(7, 8, qsgmii) SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT(8, 9, internal) SWITCH_PORT(8, 9, internal)
SWITCH_PORT(9, 10, internal) SWITCH_PORT(9, 10, internal)
@ -97,14 +97,14 @@
SWITCH_PORT(14, 15, internal) SWITCH_PORT(14, 15, internal)
SWITCH_PORT(15, 16, internal) SWITCH_PORT(15, 16, internal)
SWITCH_PORT(16, 17, qsgmii) SWITCH_PORT_SDS(16, 17, 2, qsgmii)
SWITCH_PORT(17, 18, qsgmii) SWITCH_PORT_SDS(17, 18, 2, qsgmii)
SWITCH_PORT(18, 19, qsgmii) SWITCH_PORT_SDS(18, 19, 2, qsgmii)
SWITCH_PORT(19, 20, qsgmii) SWITCH_PORT_SDS(19, 20, 2, qsgmii)
SWITCH_PORT(20, 21, qsgmii) SWITCH_PORT_SDS(20, 21, 3, qsgmii)
SWITCH_PORT(21, 22, qsgmii) SWITCH_PORT_SDS(21, 22, 3, qsgmii)
SWITCH_PORT(22, 23, qsgmii) SWITCH_PORT_SDS(22, 23, 3, qsgmii)
SWITCH_PORT(23, 24, qsgmii) SWITCH_PORT_SDS(23, 24, 3, qsgmii)
port@24 { port@24 {
reg = <24>; reg = <24>;

32
target/linux/realtek/dts/rtl8382_zyxel_gs1900-24e-a1.dts
View file

@ -30,14 +30,14 @@
&switch0 { &switch0 {
ports { ports {
SWITCH_PORT(1, 1, qsgmii) SWITCH_PORT_SDS(1, 1, 0, qsgmii)
SWITCH_PORT(0, 2, qsgmii) SWITCH_PORT_SDS(0, 2, 0, qsgmii)
SWITCH_PORT(3, 3, qsgmii) SWITCH_PORT_SDS(3, 3, 0, qsgmii)
SWITCH_PORT(2, 4, qsgmii) SWITCH_PORT_SDS(2, 4, 0, qsgmii)
SWITCH_PORT(5, 5, qsgmii) SWITCH_PORT_SDS(5, 5, 1, qsgmii)
SWITCH_PORT(4, 6, qsgmii) SWITCH_PORT_SDS(4, 6, 1, qsgmii)
SWITCH_PORT(7, 7, qsgmii) SWITCH_PORT_SDS(7, 7, 1, qsgmii)
SWITCH_PORT(6, 8, qsgmii) SWITCH_PORT_SDS(6, 8, 1, qsgmii)
SWITCH_PORT(9, 9, internal) SWITCH_PORT(9, 9, internal)
SWITCH_PORT(8, 10, internal) SWITCH_PORT(8, 10, internal)
@ -48,14 +48,14 @@
SWITCH_PORT(15, 15, internal) SWITCH_PORT(15, 15, internal)
SWITCH_PORT(14, 16, internal) SWITCH_PORT(14, 16, internal)
SWITCH_PORT(17, 17, qsgmii) SWITCH_PORT_SDS(17, 17, 2, qsgmii)
SWITCH_PORT(16, 18, qsgmii) SWITCH_PORT_SDS(16, 18, 2, qsgmii)
SWITCH_PORT(19, 19, qsgmii) SWITCH_PORT_SDS(19, 19, 2, qsgmii)
SWITCH_PORT(18, 20, qsgmii) SWITCH_PORT_SDS(18, 20, 2, qsgmii)
SWITCH_PORT(21, 21, qsgmii) SWITCH_PORT_SDS(21, 21, 3, qsgmii)
SWITCH_PORT(20, 22, qsgmii) SWITCH_PORT_SDS(20, 22, 3, qsgmii)
SWITCH_PORT(23, 23, qsgmii) SWITCH_PORT_SDS(23, 23, 3, qsgmii)
SWITCH_PORT(22, 24, qsgmii) SWITCH_PORT_SDS(22, 24, 3, qsgmii)
}; };
}; };

32
target/linux/realtek/dts/rtl8382_zyxel_gs1900-24ep-a1.dts
View file

@ -34,14 +34,14 @@
&switch0 { &switch0 {
ports { ports {
SWITCH_PORT(0, 1, qsgmii) SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT(1, 2, qsgmii) SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT(2, 3, qsgmii) SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT(3, 4, qsgmii) SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT(4, 5, qsgmii) SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT(5, 6, qsgmii) SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT(6, 7, qsgmii) SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT(7, 8, qsgmii) SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT(8, 9, internal) SWITCH_PORT(8, 9, internal)
SWITCH_PORT(9, 10, internal) SWITCH_PORT(9, 10, internal)
@ -52,13 +52,13 @@
SWITCH_PORT(14, 15, internal) SWITCH_PORT(14, 15, internal)
SWITCH_PORT(15, 16, internal) SWITCH_PORT(15, 16, internal)
SWITCH_PORT(16, 17, qsgmii) SWITCH_PORT_SDS(16, 17, 2, qsgmii)
SWITCH_PORT(17, 18, qsgmii) SWITCH_PORT_SDS(17, 18, 2, qsgmii)
SWITCH_PORT(18, 19, qsgmii) SWITCH_PORT_SDS(18, 19, 2, qsgmii)
SWITCH_PORT(19, 20, qsgmii) SWITCH_PORT_SDS(19, 20, 2, qsgmii)
SWITCH_PORT(20, 21, qsgmii) SWITCH_PORT_SDS(20, 21, 3, qsgmii)
SWITCH_PORT(21, 22, qsgmii) SWITCH_PORT_SDS(21, 22, 3, qsgmii)
SWITCH_PORT(22, 23, qsgmii) SWITCH_PORT_SDS(22, 23, 3, qsgmii)
SWITCH_PORT(23, 24, qsgmii) SWITCH_PORT_SDS(23, 24, 3, qsgmii)
}; };
}; };

32
target/linux/realtek/dts/rtl8382_zyxel_gs1900-24hp-a1.dts
View file

@ -79,14 +79,14 @@
&switch0 { &switch0 {
ports { ports {
SWITCH_PORT(0, 1, qsgmii) SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT(1, 2, qsgmii) SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT(2, 3, qsgmii) SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT(3, 4, qsgmii) SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT(4, 5, qsgmii) SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT(5, 6, qsgmii) SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT(6, 7, qsgmii) SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT(7, 8, qsgmii) SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT(8, 9, internal) SWITCH_PORT(8, 9, internal)
SWITCH_PORT(9, 10, internal) SWITCH_PORT(9, 10, internal)
@ -97,14 +97,14 @@
SWITCH_PORT(14, 15, internal) SWITCH_PORT(14, 15, internal)
SWITCH_PORT(15, 16, internal) SWITCH_PORT(15, 16, internal)
SWITCH_PORT(16, 17, qsgmii) SWITCH_PORT_SDS(16, 17, 2, qsgmii)
SWITCH_PORT(17, 18, qsgmii) SWITCH_PORT_SDS(17, 18, 2, qsgmii)
SWITCH_PORT(18, 19, qsgmii) SWITCH_PORT_SDS(18, 19, 2, qsgmii)
SWITCH_PORT(19, 20, qsgmii) SWITCH_PORT_SDS(19, 20, 2, qsgmii)
SWITCH_PORT(20, 21, qsgmii) SWITCH_PORT_SDS(20, 21, 3, qsgmii)
SWITCH_PORT(21, 22, qsgmii) SWITCH_PORT_SDS(21, 22, 3, qsgmii)
SWITCH_PORT(22, 23, qsgmii) SWITCH_PORT_SDS(22, 23, 3, qsgmii)
SWITCH_PORT(23, 24, qsgmii) SWITCH_PORT_SDS(23, 24, 3, qsgmii)
port@24 { port@24 {
reg = <24>; reg = <24>;

32
target/linux/realtek/dts/rtl8382_zyxel_gs1900-24hp-b1.dts
View file

@ -75,14 +75,14 @@
&switch0 { &switch0 {
ports { ports {
SWITCH_PORT(0, 1, qsgmii) SWITCH_PORT_SDS(0, 1, 0, qsgmii)
SWITCH_PORT(1, 2, qsgmii) SWITCH_PORT_SDS(1, 2, 0, qsgmii)
SWITCH_PORT(2, 3, qsgmii) SWITCH_PORT_SDS(2, 3, 0, qsgmii)
SWITCH_PORT(3, 4, qsgmii) SWITCH_PORT_SDS(3, 4, 0, qsgmii)
SWITCH_PORT(4, 5, qsgmii) SWITCH_PORT_SDS(4, 5, 1, qsgmii)
SWITCH_PORT(5, 6, qsgmii) SWITCH_PORT_SDS(5, 6, 1, qsgmii)
SWITCH_PORT(6, 7, qsgmii) SWITCH_PORT_SDS(6, 7, 1, qsgmii)
SWITCH_PORT(7, 8, qsgmii) SWITCH_PORT_SDS(7, 8, 1, qsgmii)
SWITCH_PORT(8, 9, internal) SWITCH_PORT(8, 9, internal)
SWITCH_PORT(9, 10, internal) SWITCH_PORT(9, 10, internal)
@ -93,14 +93,14 @@
SWITCH_PORT(14, 15, internal) SWITCH_PORT(14, 15, internal)
SWITCH_PORT(15, 16, internal) SWITCH_PORT(15, 16, internal)
SWITCH_PORT(16, 17, qsgmii) SWITCH_PORT_SDS(16, 17, 2, qsgmii)
SWITCH_PORT(17, 18, qsgmii) SWITCH_PORT_SDS(17, 18, 2, qsgmii)
SWITCH_PORT(18, 19, qsgmii) SWITCH_PORT_SDS(18, 19, 2, qsgmii)
SWITCH_PORT(19, 20, qsgmii) SWITCH_PORT_SDS(19, 20, 2, qsgmii)
SWITCH_PORT(20, 21, qsgmii) SWITCH_PORT_SDS(20, 21, 3, qsgmii)
SWITCH_PORT(21, 22, qsgmii) SWITCH_PORT_SDS(21, 22, 3, qsgmii)
SWITCH_PORT(22, 23, qsgmii) SWITCH_PORT_SDS(22, 23, 3, qsgmii)
SWITCH_PORT(23, 24, qsgmii) SWITCH_PORT_SDS(23, 24, 3, qsgmii)
port@24 { port@24 {

7
target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c
View file

@ -408,13 +408,6 @@ static int __init rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv)
sw_w32_mask(BIT(7), 0, RTL839X_SMI_GLB_CTRL); sw_w32_mask(BIT(7), 0, RTL839X_SMI_GLB_CTRL);
} }
/* Power on fibre ports and reset them if necessary */
if (priv->ports[24].phy == PHY_RTL838X_SDS) {
pr_debug("Powering on fibre ports & reset\n");
rtl8380_sds_power(24, 1);
rtl8380_sds_power(26, 1);
}
return 0; return 0;
} }

3
target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c
View file

@ -652,6 +652,7 @@ static struct phylink_pcs *rtldsa_phylink_mac_select_pcs(struct dsa_switch *ds,
return priv->pcs[port]; return priv->pcs[port];
} }
__attribute__((unused))
static void rtl83xx_config_interface(int port, phy_interface_t interface) static void rtl83xx_config_interface(int port, phy_interface_t interface)
{ {
u32 old, int_shift, sds_shift; u32 old, int_shift, sds_shift;
@ -754,7 +755,7 @@ static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
mcr = sw_r32(priv->r->mac_force_mode_ctrl(port)); mcr = sw_r32(priv->r->mac_force_mode_ctrl(port));
if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) { if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
pr_debug("port %d PHY autonegotiates\n", port); pr_debug("port %d PHY autonegotiates\n", port);
rtl83xx_config_interface(port, state->interface);
mcr |= RTL838X_NWAY_EN; mcr |= RTL838X_NWAY_EN;
} else { } else {
mcr &= ~RTL838X_NWAY_EN; mcr &= ~RTL838X_NWAY_EN;

4
target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c
View file

@ -453,7 +453,6 @@ static int rtpcs_838x_sds_patch(struct rtpcs_ctrl *ctrl, u32 sds,
return 0; return 0;
} }
__always_unused
static int rtpcs_838x_init_serdes_common(struct rtpcs_ctrl *ctrl) static int rtpcs_838x_init_serdes_common(struct rtpcs_ctrl *ctrl)
{ {
u32 val; u32 val;
@ -474,7 +473,6 @@ static int rtpcs_838x_init_serdes_common(struct rtpcs_ctrl *ctrl)
return 0; return 0;
} }
__always_unused
static int rtpcs_838x_setup_serdes(struct rtpcs_ctrl *ctrl, int sds, static int rtpcs_838x_setup_serdes(struct rtpcs_ctrl *ctrl, int sds,
phy_interface_t mode) phy_interface_t mode)
{ {
@ -3101,6 +3099,8 @@ static const struct rtpcs_config rtpcs_838x_cfg = {
.mac_rx_pause_sts = RTPCS_838X_MAC_RX_PAUSE_STS, .mac_rx_pause_sts = RTPCS_838X_MAC_RX_PAUSE_STS,
.mac_tx_pause_sts = RTPCS_838X_MAC_TX_PAUSE_STS, .mac_tx_pause_sts = RTPCS_838X_MAC_TX_PAUSE_STS,
.pcs_ops = &rtpcs_838x_pcs_ops, .pcs_ops = &rtpcs_838x_pcs_ops,
.init_serdes_common = rtpcs_838x_init_serdes_common,
.setup_serdes = rtpcs_838x_setup_serdes,
}; };
static const struct phylink_pcs_ops rtpcs_839x_pcs_ops = { static const struct phylink_pcs_ops rtpcs_839x_pcs_ops = {

10
target/linux/realtek/files-6.12/drivers/net/phy/rtl83xx-phy.c
View file

@ -146,6 +146,7 @@ static void rtl8380_phy_reset(struct phy_device *phydev)
/* Read the link and speed status of the 2 internal SGMII/1000Base-X /* Read the link and speed status of the 2 internal SGMII/1000Base-X
* ports of the RTL838x SoCs * ports of the RTL838x SoCs
*/ */
__attribute__((unused))
static int rtl8380_read_status(struct phy_device *phydev) static int rtl8380_read_status(struct phy_device *phydev)
{ {
int err; int err;
@ -1107,14 +1108,7 @@ static int rtl838x_serdes_probe(struct phy_device *phydev)
if (addr < 24) if (addr < 24)
return -ENODEV; return -ENODEV;
/* On the RTL8380M, PHYs 24-27 connect to the internal SerDes */ return 0;
if (soc_info.id == 0x8380) {
if (addr == 24)
return rtl8380_configure_serdes(phydev);
return 0;
}
return -ENODEV;
} }
static int rtl8393_serdes_probe(struct phy_device *phydev) static int rtl8393_serdes_probe(struct phy_device *phydev)