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realtek: pcs: Fix overflow in rtpcs_930x_sds_clock_wait

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It can happen that the calculation `start + (HZ / 1000) * timeout`
overflows `unsigned long`. This must be handled correctly to avoid too long
waits. Luckily, the `time_before()` helper already does this.

Signed-off-by: Sven Eckelmann <sven@narfation.org>
Link: https://github.com/openwrt/openwrt/pull/20906
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Sven Eckelmann 2025-11-23 15:25:05 +01:00 • committed by Hauke Mehrtens
parent 69c6658c73
commit d5fec0b125
1 changed files with 2 additions and 1 deletions
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3
target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c
View file

@ -685,13 +685,14 @@ static int rtpcs_930x_sds_clock_wait(struct rtpcs_ctrl *ctrl, int timeout)
{ {
u32 v; u32 v;
unsigned long start = jiffies; unsigned long start = jiffies;
unsigned long end = start + (HZ / 1000) * timeout;
do { do {
rtpcs_sds_write_bits(ctrl, 2, 0x1f, 0x2, 15, 0, 53); rtpcs_sds_write_bits(ctrl, 2, 0x1f, 0x2, 15, 0, 53);
v = rtpcs_sds_read_bits(ctrl, 2, 0x1f, 20, 5, 4); v = rtpcs_sds_read_bits(ctrl, 2, 0x1f, 20, 5, 4);
if (v == 3) if (v == 3)
return 0; return 0;
} while (jiffies < start + (HZ / 1000) * timeout); } while (time_before(jiffies, end));
return 1; return 1;
} }