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realtek: pcs: fix PLL_CML_CTRL for serdes 0/1

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Setup of register PLL_CML_CTRL has two issues.

- It clears out bits 4-31 due to a wrong mask
- Setup of bits 0-3 is not generic but depends on the mode of
  serdes 0/1

Fix that by relocating the code and adapting the mask. The error
exists for longer but it has survived the pcs refactoring. Thus
blame the corresponding refactoring commit.

Fixes: b670d48 ("realtek: pcs: rtl838x: refactor imported code")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21956
Signed-off-by: Robert Marko <robimarko@gmail.com>
(cherry picked from commit fdc3776068)
Link: https://github.com/openwrt/openwrt/pull/22087
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Markus Stockhausen 2026-02-09 20:26:07 +01:00 • committed by Hauke Mehrtens
parent ebd1c54443
commit cbb365a77b
1 changed files with 3 additions and 7 deletions
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10
target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c
View file

@ -286,6 +286,9 @@ static struct rtpcs_link *rtpcs_phylink_pcs_to_link(struct phylink_pcs *pcs)
static void rtpcs_838x_sds_patch_01_qsgmii_6275b(struct rtpcs_ctrl *ctrl)
{
/* CKREFBUF_S0S1 for QSGMII */
regmap_write_bits(ctrl->map, RTPCS_838X_PLL_CML_CTRL, 0xf, 0xf);
rtpcs_sds_write(SDS(ctrl, 0), 1, 3, 0xf46f);
rtpcs_sds_write(SDS(ctrl, 0), 1, 2, 0x85fa);
rtpcs_sds_write(SDS(ctrl, 1), 1, 2, 0x85fa);
@ -522,18 +525,11 @@ static int rtpcs_838x_sds_patch(struct rtpcs_serdes *sds,
static int rtpcs_838x_init_serdes_common(struct rtpcs_ctrl *ctrl)
{
u32 val;
dev_dbg(ctrl->dev, "Init RTL838X SerDes common\n");
/* enable R/W of some protected registers */
regmap_write(ctrl->map, RTPCS_838X_INT_RW_CTRL, 0x3);
regmap_read(ctrl->map, RTPCS_838X_PLL_CML_CTRL, &val);
dev_dbg(ctrl->dev, "PLL control register: %x\n", val);
regmap_write_bits(ctrl->map, RTPCS_838X_PLL_CML_CTRL, 0xfffffff0,
0xaaaaaaaf & 0xf);
/* power off and reset all SerDes */
regmap_write(ctrl->map, RTPCS_838X_SDS_CFG_REG, 0x3f);
regmap_write(ctrl->map, RTPCS_838X_RST_GLB_CTRL_0, 0x10); /* SW_SERDES_RST */