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realtek: dsa,phy: rtl838x: remove 'SerDes as PHY' leftovers
RTL838X SerDes is now completely managed by the PCS driver so it's time to remove all the unused leftovers from DSA and PHY drivers to have that finally separated. Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com> Link: https://github.com/openwrt/openwrt/pull/20876 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Jonas Jelonek
Hauke Mehrtens
parent
a63da75e44
commit
c3887c126d
7 changed files with 0 additions and 261 deletions
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@ -369,14 +369,6 @@ static int __init rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv)
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continue;
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}
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/* Check for the integrated SerDes of the RTL8380M first */
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if (of_property_read_bool(phy_node, "phy-is-integrated")
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&& priv->id == 0x8380 && pn >= 24) {
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pr_debug("----> FOUND A SERDES\n");
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priv->ports[pn].phy = PHY_RTL838X_SDS;
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continue;
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}
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if (of_property_read_bool(phy_node, "phy-is-integrated") &&
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!of_property_read_bool(phy_node, "sfp")) {
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priv->ports[pn].phy = PHY_RTL8218B_INT;
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@ -652,44 +652,6 @@ static struct phylink_pcs *rtldsa_phylink_mac_select_pcs(struct dsa_switch *ds,
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return priv->pcs[port];
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}
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__attribute__((unused))
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static void rtl83xx_config_interface(int port, phy_interface_t interface)
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{
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u32 old, int_shift, sds_shift;
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switch (port) {
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case 24:
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int_shift = 0;
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sds_shift = 5;
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break;
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case 26:
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int_shift = 3;
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sds_shift = 0;
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break;
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default:
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return;
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}
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old = sw_r32(RTL838X_SDS_MODE_SEL);
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switch (interface) {
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case PHY_INTERFACE_MODE_1000BASEX:
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if ((old >> sds_shift & 0x1f) == 4)
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return;
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sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
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sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
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break;
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case PHY_INTERFACE_MODE_SGMII:
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if ((old >> sds_shift & 0x1f) == 2)
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return;
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sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
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sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
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break;
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default:
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return;
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}
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pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
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}
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static void rtldsa_83xx_phylink_get_caps(struct dsa_switch *ds, int port,
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struct phylink_config *config)
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{
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@ -1810,31 +1810,3 @@ void rtl838x_vlan_profile_dump(int profile)
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profile, p & 1, (p >> 1) & 0x1ff, (p >> 10) & 0x1ff, (p >> 19) & 0x1ff);
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}
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void rtl8380_sds_rst(int mac)
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{
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u32 offset = (mac == 24) ? 0 : 0x100;
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sw_w32_mask(1 << 11, 0, RTL838X_SDS4_FIB_REG0 + offset);
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sw_w32_mask(0x3, 0, RTL838X_SDS4_REG28 + offset);
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sw_w32_mask(0x3, 0x3, RTL838X_SDS4_REG28 + offset);
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sw_w32_mask(0, 0x1 << 6, RTL838X_SDS4_DUMMY0 + offset);
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sw_w32_mask(0x1 << 6, 0, RTL838X_SDS4_DUMMY0 + offset);
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pr_debug("SERDES reset: %d\n", mac);
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}
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int rtl8380_sds_power(int mac, int val)
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{
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u32 mode = (val == 1) ? 0x4 : 0x9;
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u32 offset = (mac == 24) ? 5 : 0;
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if ((mac != 24) && (mac != 26)) {
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pr_err("%s: not a fibre port: %d\n", __func__, mac);
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return -1;
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}
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sw_w32_mask(0x1f << offset, mode << offset, RTL838X_SDS_MODE_SEL);
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rtl8380_sds_rst(mac);
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return 0;
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}
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@ -21,10 +21,6 @@
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#define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C)
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#define RTL931X_MAC_FORCE_MODE_CTRL (0x0DCC)
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#define RTL838X_DMY_REG31 (0x3b28)
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#define RTL838X_SDS_MODE_SEL (0x0028)
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#define RTL838X_SDS_CFG_REG (0x0034)
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#define RTL838X_INT_MODE_CTRL (0x005c)
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#define RTL838X_PORT_ISO_CTRL(port) (0x4100 + ((port) << 2))
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#define RTL839X_PORT_ISO_CTRL(port) (0x1400 + ((port) << 3))
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@ -54,12 +50,6 @@
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#define RTL839X_SDS12_13_PWR0 (0xb880)
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#define RTL839X_SDS12_13_PWR1 (0xb980)
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/* Registers of the internal Serdes of the 8380 */
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#define RTL838X_SDS4_FIB_REG0 (0xF800)
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#define RTL838X_SDS4_REG28 (0xef80)
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#define RTL838X_SDS4_DUMMY0 (0xef8c)
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#define RTL838X_SDS5_EXT_REG6 (0xf18c)
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/* VLAN registers */
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#define RTL838X_VLAN_CTRL (0x3A74)
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#define RTL838X_VLAN_PROFILE(idx) (0x3A88 + ((idx) << 2))
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@ -162,8 +162,6 @@ u32 rtl838x_hash(struct rtl838x_switch_priv *priv, u64 seed);
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irqreturn_t rtl838x_switch_irq(int irq, void *dev_id);
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void rtl8380_get_version(struct rtl838x_switch_priv *priv);
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void rtl838x_vlan_profile_dump(int index);
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void rtl8380_sds_rst(int mac);
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int rtl8380_sds_power(int mac, int val);
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void rtl838x_print_matrix(void);
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/* RTL839x-specific */
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@ -143,24 +143,6 @@ static void rtl8380_phy_reset(struct phy_device *phydev)
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phy_modify(phydev, 0, BMCR_RESET, BMCR_RESET);
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}
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/* Read the link and speed status of the 2 internal SGMII/1000Base-X
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* ports of the RTL838x SoCs
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*/
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__attribute__((unused))
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static int rtl8380_read_status(struct phy_device *phydev)
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{
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int err;
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err = genphy_read_status(phydev);
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if (phydev->link) {
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phydev->speed = SPEED_1000;
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phydev->duplex = DUPLEX_FULL;
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}
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return err;
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}
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/* Read the link and speed status of the 2 internal SGMII/1000Base-X
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* ports of the RTL8393 SoC
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*/
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@ -808,127 +790,6 @@ static int rtl8380_configure_rtl8214fc(struct phy_device *phydev)
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return 0;
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}
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static int rtl8380_configure_serdes(struct phy_device *phydev)
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{
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u32 v;
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u32 sds_conf_value;
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int i;
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struct fw_header *h;
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u32 *rtl8380_sds_take_reset;
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u32 *rtl8380_sds_common;
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u32 *rtl8380_sds01_qsgmii_6275b;
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u32 *rtl8380_sds23_qsgmii_6275b;
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u32 *rtl8380_sds4_fiber_6275b;
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u32 *rtl8380_sds5_fiber_6275b;
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u32 *rtl8380_sds_reset;
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u32 *rtl8380_sds_release_reset;
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phydev_info(phydev, "Detected internal RTL8380 SERDES\n");
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h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8380_1);
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if (!h)
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return -1;
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if (h->magic != 0x83808380) {
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phydev_err(phydev, "Wrong firmware file: magic number mismatch.\n");
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return -1;
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}
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rtl8380_sds_take_reset = (void *)h + sizeof(struct fw_header) + h->parts[0].start;
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rtl8380_sds_common = (void *)h + sizeof(struct fw_header) + h->parts[1].start;
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rtl8380_sds01_qsgmii_6275b = (void *)h + sizeof(struct fw_header) + h->parts[2].start;
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rtl8380_sds23_qsgmii_6275b = (void *)h + sizeof(struct fw_header) + h->parts[3].start;
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rtl8380_sds4_fiber_6275b = (void *)h + sizeof(struct fw_header) + h->parts[4].start;
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rtl8380_sds5_fiber_6275b = (void *)h + sizeof(struct fw_header) + h->parts[5].start;
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rtl8380_sds_reset = (void *)h + sizeof(struct fw_header) + h->parts[6].start;
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rtl8380_sds_release_reset = (void *)h + sizeof(struct fw_header) + h->parts[7].start;
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/* Back up serdes power off value */
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sds_conf_value = sw_r32(RTL838X_SDS_CFG_REG);
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pr_info("SDS power down value: %x\n", sds_conf_value);
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/* take serdes into reset */
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i = 0;
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while (rtl8380_sds_take_reset[2 * i]) {
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sw_w32(rtl8380_sds_take_reset[2 * i + 1], rtl8380_sds_take_reset[2 * i]);
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i++;
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udelay(1000);
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}
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/* apply common serdes patch */
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i = 0;
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while (rtl8380_sds_common[2 * i]) {
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sw_w32(rtl8380_sds_common[2 * i + 1], rtl8380_sds_common[2 * i]);
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i++;
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udelay(1000);
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}
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/* internal R/W enable */
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sw_w32(3, RTL838X_INT_RW_CTRL);
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/* SerDes ports 4 and 5 are FIBRE ports */
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sw_w32_mask(0x7 | 0x38, 1 | (1 << 3), RTL838X_INT_MODE_CTRL);
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/* SerDes module settings, SerDes 0-3 are QSGMII */
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v = 0x6 << 25 | 0x6 << 20 | 0x6 << 15 | 0x6 << 10;
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/* SerDes 4 and 5 are 1000BX FIBRE */
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v |= 0x4 << 5 | 0x4;
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sw_w32(v, RTL838X_SDS_MODE_SEL);
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pr_info("PLL control register: %x\n", sw_r32(RTL838X_PLL_CML_CTRL));
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sw_w32_mask(0xfffffff0, 0xaaaaaaaf & 0xf, RTL838X_PLL_CML_CTRL);
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i = 0;
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while (rtl8380_sds01_qsgmii_6275b[2 * i]) {
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sw_w32(rtl8380_sds01_qsgmii_6275b[2 * i + 1],
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rtl8380_sds01_qsgmii_6275b[2 * i]);
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i++;
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}
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i = 0;
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while (rtl8380_sds23_qsgmii_6275b[2 * i]) {
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sw_w32(rtl8380_sds23_qsgmii_6275b[2 * i + 1], rtl8380_sds23_qsgmii_6275b[2 * i]);
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i++;
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}
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i = 0;
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while (rtl8380_sds4_fiber_6275b[2 * i]) {
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sw_w32(rtl8380_sds4_fiber_6275b[2 * i + 1], rtl8380_sds4_fiber_6275b[2 * i]);
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i++;
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}
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i = 0;
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while (rtl8380_sds5_fiber_6275b[2 * i]) {
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sw_w32(rtl8380_sds5_fiber_6275b[2 * i + 1], rtl8380_sds5_fiber_6275b[2 * i]);
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i++;
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}
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i = 0;
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while (rtl8380_sds_reset[2 * i]) {
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sw_w32(rtl8380_sds_reset[2 * i + 1], rtl8380_sds_reset[2 * i]);
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i++;
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}
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i = 0;
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while (rtl8380_sds_release_reset[2 * i]) {
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sw_w32(rtl8380_sds_release_reset[2 * i + 1], rtl8380_sds_release_reset[2 * i]);
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i++;
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}
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pr_info("SDS power down value now: %x\n", sw_r32(RTL838X_SDS_CFG_REG));
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sw_w32(sds_conf_value, RTL838X_SDS_CFG_REG);
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pr_info("Configuration of SERDES done\n");
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return 0;
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}
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static int rtl8390_configure_serdes(struct phy_device *phydev)
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{
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phydev_info(phydev, "Detected internal RTL8390 SERDES\n");
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@ -1099,18 +960,6 @@ static int rtl8218b_config_init(struct phy_device *phydev)
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return 0;
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}
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static int rtl838x_serdes_probe(struct phy_device *phydev)
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{
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int addr = phydev->mdio.addr;
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if (soc_info.family != RTL8380_FAMILY_ID)
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return -ENODEV;
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if (addr < 24)
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return -ENODEV;
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return 0;
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}
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static int rtl8393_serdes_probe(struct phy_device *phydev)
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{
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int addr = phydev->mdio.addr;
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@ -1218,17 +1067,6 @@ static struct phy_driver rtl83xx_phy_driver[] = {
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.write_mmd = rtl821x_write_mmd,
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.write_page = rtl821x_write_page,
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},
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{
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PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
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.name = "Realtek RTL8380 SERDES",
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.features = PHY_GBIT_FIBRE_FEATURES,
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.probe = rtl838x_serdes_probe,
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.read_page = rtl821x_read_page,
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.write_page = rtl821x_write_page,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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.read_status = rtl8380_read_status,
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},
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{
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PHY_ID_MATCH_MODEL(PHY_ID_RTL8393_I),
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.name = "Realtek RTL8393 SERDES",
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@ -35,19 +35,6 @@ struct __packed fw_header {
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#define PHY_IS_RTL8214FB 2
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#define PHY_IS_RTL8218B_E 3
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/* Registers of the internal Serdes of the 8380 */
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#define RTL838X_SDS_MODE_SEL (0x0028)
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#define RTL838X_SDS_CFG_REG (0x0034)
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#define RTL838X_INT_MODE_CTRL (0x005c)
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#define RTL838X_DMY_REG31 (0x3b28)
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#define RTL8380_SDS4_FIB_REG0 (0xF800)
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#define RTL838X_SDS4_REG28 (0xef80)
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#define RTL838X_SDS4_DUMMY0 (0xef8c)
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#define RTL838X_SDS5_EXT_REG6 (0xf18c)
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#define RTL838X_SDS4_FIB_REG0 (RTL838X_SDS4_REG28 + 0x880)
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#define RTL838X_SDS5_FIB_REG0 (RTL838X_SDS4_REG28 + 0x980)
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/* Registers of the internal SerDes of the RTL8390 */
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#define RTL839X_SDS12_13_XSG0 (0xB800)
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