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realtek: phy: align page select register naming with upstream
The downstream driver has different naming conventions than upstream. Register: 31 Downstream name: RTL8XXX_PAGE_SELECT Upstream name: RTL821x_PAGE_SELECT Register: 30 Downstream name: RTL821XEXT_MEDIA_PAGE_SELECT Upstream name: RTL821x_EXT_PAGE_SELECT Align to upstream. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Link: https://github.com/openwrt/openwrt/pull/21716 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Markus Stockhausen
Hauke Mehrtens
parent
3c024c00ce
commit
c2a3871387
1 changed files with 37 additions and 30 deletions
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@ -20,8 +20,16 @@
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extern struct rtl83xx_soc_info soc_info;
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/* all Clause-22 RealTek MDIO PHYs use register 0x1f for page select */
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#define RTL8XXX_PAGE_SELECT 0x1f
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/*
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* Realtek PHYs have three special page registers. Register 31 (page select) switches the
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* register pages and gives access to special registers that are mapped into register
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* range 16-24. Register 30 (extended page select) does basically the same. It especially
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* grants access to special internal data like fibre, copper or serdes setup. Register
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* 29 is a write only companion of register 30. As it flips back to 0 and register 30
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* shows the original write content it should be avoided at all cost.
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*/
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#define RTL821x_PAGE_SELECT 0x1f
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#define RTL821x_EXT_PAGE_SELECT 0x1e
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#define RTL8XXX_PAGE_MAIN 0x0000
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#define RTL821X_PAGE_PORT 0x0266
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@ -38,7 +46,6 @@ extern struct rtl83xx_soc_info soc_info;
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*/
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#define RTL838X_PAGE_RAW 0x0fff
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#define RTL821XEXT_MEDIA_PAGE_SELECT 0x1e
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#define RTL821X_PHYCR2 0x19
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#define RTL821X_PHYCR2_PHY_EEE_ENABLE BIT(5)
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@ -179,12 +186,12 @@ static void rtl8380_phy_reset(struct phy_device *phydev)
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static int rtl821x_read_page(struct phy_device *phydev)
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{
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return __phy_read(phydev, RTL8XXX_PAGE_SELECT);
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return __phy_read(phydev, RTL821x_PAGE_SELECT);
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}
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static int rtl821x_write_page(struct phy_device *phydev, int page)
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{
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return __phy_write(phydev, RTL8XXX_PAGE_SELECT, page);
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return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
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}
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static struct fw_header *rtl838x_request_fw(struct phy_device *phydev,
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@ -327,15 +334,15 @@ static bool __rtl8214fc_media_is_fibre(struct phy_device *phydev)
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int reg = regs[phydev->mdio.addr & 3];
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int oldpage, oldxpage, val;
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oldpage = __phy_read(basephy, RTL8XXX_PAGE_SELECT);
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oldxpage = __phy_read(basephy, RTL821XEXT_MEDIA_PAGE_SELECT);
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oldpage = __phy_read(basephy, RTL821x_PAGE_SELECT);
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oldxpage = __phy_read(basephy, RTL821x_EXT_PAGE_SELECT);
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__phy_write(basephy, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
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__phy_write(basephy, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PORT);
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__phy_write(basephy, RTL821x_EXT_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
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__phy_write(basephy, RTL821x_PAGE_SELECT, RTL821X_PAGE_PORT);
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val = __phy_read(basephy, reg);
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__phy_write(basephy, RTL821XEXT_MEDIA_PAGE_SELECT, oldxpage);
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__phy_write(basephy, RTL8XXX_PAGE_SELECT, oldpage);
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__phy_write(basephy, RTL821x_EXT_PAGE_SELECT, oldxpage);
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__phy_write(basephy, RTL821x_PAGE_SELECT, oldpage);
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return !(val & RTL8214FC_MEDIA_COPPER);
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}
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@ -354,15 +361,15 @@ static bool rtl8214fc_media_is_fibre(struct phy_device *phydev)
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static void rtl8214fc_power_set(struct phy_device *phydev, int port, bool on)
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{
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int page = port == PORT_FIBRE ? RTL821X_MEDIA_PAGE_FIBRE : RTL821X_MEDIA_PAGE_COPPER;
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int oldxpage = __phy_read(phydev, RTL821XEXT_MEDIA_PAGE_SELECT);
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int oldxpage = __phy_read(phydev, RTL821x_EXT_PAGE_SELECT);
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int pdown = on ? 0 : BMCR_PDOWN;
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phydev_info(phydev, "power %s %s\n", on ? "on" : "off",
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port == PORT_FIBRE ? "fibre" : "copper");
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phy_write(phydev, RTL821XEXT_MEDIA_PAGE_SELECT, page);
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phy_write(phydev, RTL821x_EXT_PAGE_SELECT, page);
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phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, BMCR_PDOWN, pdown);
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phy_write(phydev, RTL821XEXT_MEDIA_PAGE_SELECT, oldxpage);
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phy_write(phydev, RTL821x_EXT_PAGE_SELECT, oldxpage);
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}
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static int rtl8214fc_suspend(struct phy_device *phydev)
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@ -386,15 +393,15 @@ static int rtl8214fc_resume(struct phy_device *phydev)
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static void rtl8214fc_media_set(struct phy_device *phydev, bool set_fibre)
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{
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struct phy_device *basephy = get_base_phy(phydev);
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int oldxpage = phy_read(basephy, RTL821XEXT_MEDIA_PAGE_SELECT);
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int oldxpage = phy_read(basephy, RTL821x_EXT_PAGE_SELECT);
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int copper = set_fibre ? 0 : RTL8214FC_MEDIA_COPPER;
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static int regs[] = {16, 19, 20, 21};
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int reg = regs[phydev->mdio.addr & 3];
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phydev_info(phydev, "switch to %s\n", set_fibre ? "fibre" : "copper");
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phy_write(basephy, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
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phy_write(basephy, RTL821x_EXT_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
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phy_modify_paged(basephy, RTL821X_PAGE_PORT, reg, RTL8214FC_MEDIA_COPPER, copper);
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phy_write(basephy, RTL821XEXT_MEDIA_PAGE_SELECT, oldxpage);
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phy_write(basephy, RTL821x_EXT_PAGE_SELECT, oldxpage);
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if (!phydev->suspended) {
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rtl8214fc_power_set(phydev, PORT_MII, !set_fibre);
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@ -627,10 +634,10 @@ static int rtl8218d_config_init(struct phy_device *phydev)
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* phy_write(phydev, 0x1e, 0x8);
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* phy_write_paged(phydev, 0x262, 0x10, 0x1);
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*/
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oldpage = phy_read(phydev, RTL8XXX_PAGE_SELECT);
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oldxpage = phy_read(phydev, RTL821XEXT_MEDIA_PAGE_SELECT);
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oldpage = phy_read(phydev, RTL821x_PAGE_SELECT);
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oldxpage = phy_read(phydev, RTL821x_EXT_PAGE_SELECT);
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phy_write(phydev, RTL821XEXT_MEDIA_PAGE_SELECT, 0x8);
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phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0x8);
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chip_info = phy_read_paged(phydev, 0x327, 0x15);
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is_qsgmii = (phy_read_paged(phydev, 0x260, 0x12) & 0xf0) == 0xd0;
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@ -663,8 +670,8 @@ static int rtl8218d_config_init(struct phy_device *phydev)
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phy_write_paged(phydev, 0x500, 0x10, 0x1400);
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phy_write_paged(phydev, 0x500, 0x10, 0x1403);
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phy_write(phydev, RTL821XEXT_MEDIA_PAGE_SELECT, oldxpage);
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phy_write(phydev, RTL8XXX_PAGE_SELECT, oldpage);
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phy_write(phydev, RTL821x_EXT_PAGE_SELECT, oldxpage);
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phy_write(phydev, RTL821x_PAGE_SELECT, oldpage);
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return 0;
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}
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@ -693,9 +700,9 @@ static int rtl8218b_config_init(struct phy_device *phydev)
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* so that ports at least get link up and pass traffic.
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*/
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oldpage = phy_read(phydev, RTL8XXX_PAGE_SELECT);
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oldxpage = phy_read(phydev, RTL821XEXT_MEDIA_PAGE_SELECT);
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phy_write(phydev, RTL821XEXT_MEDIA_PAGE_SELECT, 0x8);
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oldpage = phy_read(phydev, RTL821x_PAGE_SELECT);
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oldxpage = phy_read(phydev, RTL821x_EXT_PAGE_SELECT);
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phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0x8);
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/* activate 32/40 bit redundancy algorithm for first MAC serdes */
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phy_modify_paged(phydev, RTL821X_MAC_SDS_PAGE(0, 1), 0x14, 0, BIT(3));
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@ -722,8 +729,8 @@ static int rtl8218b_config_init(struct phy_device *phydev)
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phy_modify_paged(phydev, RTL821X_MAC_SDS_PAGE(sds, 0), 0x13, BIT(6), 0);
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}
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phy_write(phydev, RTL821XEXT_MEDIA_PAGE_SELECT, oldxpage);
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phy_write(phydev, RTL8XXX_PAGE_SELECT, oldpage);
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phy_write(phydev, RTL821x_EXT_PAGE_SELECT, oldxpage);
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phy_write(phydev, RTL821x_PAGE_SELECT, oldpage);
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return 0;
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}
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@ -749,20 +756,20 @@ static int rtl8214fc_phy_probe(struct phy_device *phydev)
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if (phydev->mdio.addr % 8 == 0) {
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/* Force all ports to copper */
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phy_write(phydev, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
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phy_write(phydev, RTL821x_EXT_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
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for (int port = 0; port < 4; port++)
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phy_modify_paged(phydev, 0x266, regs[port], 0, GENMASK(11, 10));
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}
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/* Step 2 - port setup */
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phy_write(phydev, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE);
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phy_write(phydev, RTL821x_EXT_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE);
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/* set fiber SerDes RX to negative edge */
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phy_modify_paged(phydev, 0x8, 0x17, 0, BIT(14));
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/* auto negotiation disable link on */
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phy_modify_paged(phydev, 0x8, 0x14, 0, BIT(2));
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/* disable fiber 100MBit */
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phy_modify_paged(phydev, 0x8, 0x11, BIT(5), 0);
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phy_write(phydev, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
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phy_write(phydev, RTL821x_EXT_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
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/* Disable EEE. 0xa5d/0x10 is the same as MDIO_MMD_AN / MDIO_AN_EEE_ADV */
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phy_write_paged(phydev, 0xa5d, 0x10, 0x0000);
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