From b4df523754e8364fcab92db2e2724a6146495a0c Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Thu, 26 Feb 2026 15:04:21 +0100 Subject: [PATCH] microchipsw: backport fix for ets qdisc offload Backport upstream fix for ets qdisc offloading. Signed-off-by: Robert Marko --- ...9x-fix-DWRR-cost-max-to-match-hardwa.patch | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 target/linux/microchipsw/patches-6.12/0098-v7.0-net-sparx5-lan969x-fix-DWRR-cost-max-to-match-hardwa.patch diff --git a/target/linux/microchipsw/patches-6.12/0098-v7.0-net-sparx5-lan969x-fix-DWRR-cost-max-to-match-hardwa.patch b/target/linux/microchipsw/patches-6.12/0098-v7.0-net-sparx5-lan969x-fix-DWRR-cost-max-to-match-hardwa.patch new file mode 100644 index 0000000000..27c4a31912 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0098-v7.0-net-sparx5-lan969x-fix-DWRR-cost-max-to-match-hardwa.patch @@ -0,0 +1,38 @@ +From 6c28aa8dfdf24f554d4c5d4ff7d723a95360d94a Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Tue, 10 Feb 2026 14:44:01 +0100 +Subject: [PATCH] net: sparx5/lan969x: fix DWRR cost max to match hardware + register width + +DWRR (Deficit Weighted Round Robin) scheduling distributes bandwidth +across traffic classes based on per-queue cost values, where lower cost +means higher bandwidth share. + +The SPX5_DWRR_COST_MAX constant is 63 (6 bits) but the hardware +register field HSCH_DWRR_ENTRY_DWRR_COST is GENMASK(24, 20), only +5 bits wide (max 31). This causes sparx5_weight_to_hw_cost() to +compute cost values that silently overflow via FIELD_PREP, resulting +in incorrect scheduling weights. + +Set SPX5_DWRR_COST_MAX to 31 to match the hardware register width. + +Fixes: 211225428d65 ("net: microchip: sparx5: add support for offloading ets qdisc") +Signed-off-by: Daniel Machon +Reviewed-by: Simon Horman +Link: https://patch.msgid.link/20260210-sparx5-fix-dwrr-cost-max-v1-1-58fbdbc25652@microchip.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/microchip/sparx5/sparx5_qos.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_qos.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_qos.h +@@ -35,7 +35,7 @@ + #define SPX5_SE_BURST_UNIT 4096 + + /* Dwrr */ +-#define SPX5_DWRR_COST_MAX 63 ++#define SPX5_DWRR_COST_MAX 31 + + struct sparx5_shaper { + u32 mode;