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realtek: dsa: provide generic fast_age for RTL93xx

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Fast ageing of L2 entries is supported by DSA with two callbacks.

- port_fast_age(): age out for one port
- port_vlan_fast_age(): age out for one vlan on one port

Independent from the SoC it always boils down to issue a command
to the L2_TBL_FLUSH_CTRL register. Nevertheless the current
implemententation is repeated multiple times and makes use of
the family_id.

As a first refactoring step provide generic fast_age() functions
for RTL930x and RTL931x by rearranging the existing definitions
of vlan_port_fast_age().

The logic is as follows:

- provide a SoC dependent function that works with or without VLAN.
  When VLAN/VID = -1 only flush the specific port otherwise only
  flush given VLAN on port.
- provide a port_fast_age() helper that calls the SoC specific
  functions with VLAN = -1.
- provide a port_vlan_fast_age() helper that calls the SOC specific
  functions and handing over the given VLAN.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22145
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Markus Stockhausen 2026-02-22 14:09:07 +01:00 • committed by Robert Marko
parent 0f878ab9dc
commit b37c4dbb2a
4 changed files with 17 additions and 11 deletions
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4
target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c
View file

@ -2190,11 +2190,11 @@ static int rtldsa_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid)
struct rtl838x_switch_priv *priv = ds->priv;
int ret;
if (!priv->r->vlan_port_fast_age)
if (!priv->r->fast_age)
return -EOPNOTSUPP;
mutex_lock(&priv->reg_mutex);
ret = priv->r->vlan_port_fast_age(priv, port, vid);
ret = priv->r->fast_age(priv, port, vid);
mutex_unlock(&priv->reg_mutex);
return ret;

2
target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.h
View file

@ -1284,7 +1284,7 @@ struct rtldsa_config {
void (*vlan_port_pvidmode_set)(int port, enum pbvlan_type type, enum pbvlan_mode mode);
void (*vlan_port_pvid_set)(int port, enum pbvlan_type type, int pvid);
void (*vlan_port_keep_tag_set)(int port, bool keep_outer, bool keep_inner);
int (*vlan_port_fast_age)(struct rtl838x_switch_priv *priv, int port, u16 vid);
int (*fast_age)(struct rtl838x_switch_priv *priv, int port, int vid);
void (*set_vlan_igr_filter)(int port, enum igr_filter state);
void (*set_vlan_egr_filter)(int port, enum egr_filter state);
void (*enable_learning)(int port, bool enable);

11
target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl930x.c
View file

@ -2338,17 +2338,20 @@ static void rtl930x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid
sw_w32_mask(0xfff << 16, pvid << 16, RTL930X_VLAN_PORT_PB_VLAN + (port << 2));
}
static int rtldsa_930x_vlan_port_fast_age(struct rtl838x_switch_priv *priv, int port, u16 vid)
static int rtldsa_930x_fast_age(struct rtl838x_switch_priv *priv, int port, int vid)
{
u32 val;
sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
val = 0;
val |= vid << 12;
val |= BIT(26); /* compare port id */
val |= BIT(28); /* compare VID */
val |= BIT(30); /* status - trigger flush */
if (vid >= 0) {
val |= BIT(28); /* compare VID */
val |= vid << 12;
}
sw_w32(val, RTL930X_L2_TBL_FLUSH_CTRL);
do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
@ -2673,7 +2676,7 @@ const struct rtldsa_config rtldsa_930x_cfg = {
.vlan_port_keep_tag_set = rtl930x_vlan_port_keep_tag_set,
.vlan_port_pvidmode_set = rtl930x_vlan_port_pvidmode_set,
.vlan_port_pvid_set = rtl930x_vlan_port_pvid_set,
.vlan_port_fast_age = rtldsa_930x_vlan_port_fast_age,
.fast_age = rtldsa_930x_fast_age,
.trk_mbr_ctr = rtl930x_trk_mbr_ctr,
.rma_bpdu_fld_pmask = RTL930X_RMA_BPDU_FLD_PMSK,
.init_eee = rtl930x_init_eee,

11
target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl931x.c
View file

@ -1478,17 +1478,20 @@ static void rtl931x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid
sw_w32_mask(0xfff << 14, pvid << 14, RTL931X_VLAN_PORT_IGR_CTRL + (port << 2));
}
static int rtldsa_931x_vlan_port_fast_age(struct rtl838x_switch_priv *priv, int port, u16 vid)
static int rtldsa_931x_fast_age(struct rtl838x_switch_priv *priv, int port, int vid)
{
u32 val;
sw_w32(vid << 20, RTL931X_L2_TBL_FLUSH_CTRL + 4);
sw_w32(0, RTL931X_L2_TBL_FLUSH_CTRL + 4);
val = 0;
val |= port << 11;
val |= BIT(24); /* compare port id */
val |= BIT(26); /* compare VID */
val |= BIT(28); /* status - trigger flush */
if (vid >= 0) {
sw_w32(vid << 20, RTL931X_L2_TBL_FLUSH_CTRL + 4);
val |= BIT(26); /* compare VID */
}
sw_w32(val, RTL931X_L2_TBL_FLUSH_CTRL);
do { } while (sw_r32(RTL931X_L2_TBL_FLUSH_CTRL) & BIT(28));
@ -1827,7 +1830,7 @@ const struct rtldsa_config rtldsa_931x_cfg = {
.vlan_port_keep_tag_set = rtl931x_vlan_port_keep_tag_set,
.vlan_port_pvidmode_set = rtl931x_vlan_port_pvidmode_set,
.vlan_port_pvid_set = rtl931x_vlan_port_pvid_set,
.vlan_port_fast_age = rtldsa_931x_vlan_port_fast_age,
.fast_age = rtldsa_931x_fast_age,
.trk_mbr_ctr = rtldsa_931x_trk_mbr_ctr,
.rma_bpdu_fld_pmask = RTL931X_RMA_BPDU_FLD_PMSK,
.set_vlan_igr_filter = rtl931x_set_igr_filter,