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realtek: dsa,phy: rtl839x: remove SerDes PHY leftovers

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Drop several leftovers of SerDes configuration from PHY and DSA drivers.
Both drivers can be seen as free from any SoC-side SerDes stuff.

Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21360
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
This commit is contained in:
Jonas Jelonek 2025-11-09 11:15:42 +00:00 • committed by Stijn Tintel
parent 9c0dfa339f
commit a9254a593b
5 changed files with 0 additions and 147 deletions
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8
target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.h
View file

@ -42,14 +42,6 @@
#define RTL930X_STAT_CTRL (0x3248)
#define RTL931X_STAT_CTRL (0x5720)
/* Registers of the internal Serdes of the 8390 */
#define RTL8390_SDS0_1_XSG0 (0xA000)
#define RTL8390_SDS0_1_XSG1 (0xA100)
#define RTL839X_SDS12_13_XSG0 (0xB800)
#define RTL839X_SDS12_13_XSG1 (0xB900)
#define RTL839X_SDS12_13_PWR0 (0xb880)
#define RTL839X_SDS12_13_PWR1 (0xb980)
/* VLAN registers */
#define RTL838X_VLAN_CTRL (0x3A74)
#define RTL838X_VLAN_PROFILE(idx) (0x3A88 + ((idx) << 2))

19
target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl839x.c
View file

@ -624,25 +624,6 @@ irqreturn_t rtl839x_switch_irq(int irq, void *dev_id)
return IRQ_HANDLED;
}
/* TODO: unused */
int rtl8390_sds_power(int mac, int val)
{
u32 offset = (mac == 48) ? 0x0 : 0x100;
u32 mode = val ? 0 : 1;
pr_debug("In %s: mac %d, set %d\n", __func__, mac, val);
if ((mac != 48) && (mac != 49)) {
pr_err("%s: not an SFP port: %d\n", __func__, mac);
return -1;
}
/* Set bit 1003. 1000 starts at 7c */
sw_w32_mask(BIT(11), mode << 11, RTL839X_SDS12_13_PWR0 + offset);
return 0;
}
void rtl8390_get_version(struct rtl838x_switch_priv *priv)
{
u32 info, model;

1
target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl83xx.h
View file

@ -196,7 +196,6 @@ int rtl83xx_lag_del(struct dsa_switch *ds, int group, int port);
void rtl838x_egress_rate_queue_limit(struct rtl838x_switch_priv *priv, int port,
int queue, u32 rate);
int rtl8390_sds_power(int mac, int val);
void rtl839x_pie_rule_dump(struct pie_rule *pr);
void rtl839x_set_egress_queue(int port, int queue);

113
target/linux/realtek/files-6.12/drivers/net/phy/rtl83xx-phy.c
View file

@ -181,34 +181,6 @@ static void rtl8380_phy_reset(struct phy_device *phydev)
phy_modify(phydev, 0, BMCR_RESET, BMCR_RESET);
}
/* Read the link and speed status of the 2 internal SGMII/1000Base-X
* ports of the RTL8393 SoC
*/
static int rtl8393_read_status(struct phy_device *phydev)
{
int offset = 0;
int err;
int phy_addr = phydev->mdio.addr;
u32 v;
err = genphy_read_status(phydev);
if (phy_addr == 49)
offset = 0x100;
if (phydev->link) {
phydev->speed = SPEED_100;
/* Read SPD_RD_00 (bit 13) and SPD_RD_01 (bit 6) out of the internal
* PHY registers
*/
v = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80);
if (!(v & (1 << 13)) && (v & (1 << 6)))
phydev->speed = SPEED_1000;
phydev->duplex = DUPLEX_FULL;
}
return err;
}
static int rtl821x_read_page(struct phy_device *phydev)
{
return __phy_read(phydev, RTL8XXX_PAGE_SELECT);
@ -281,27 +253,6 @@ static void rtl821x_phy_setup_package_broadcast(struct phy_device *phydev, bool
mdelay(1);
}
static int rtl8390_configure_generic(struct phy_device *phydev)
{
int mac = phydev->mdio.addr;
u32 val, phy_id;
val = phy_read(phydev, 2);
phy_id = val << 16;
val = phy_read(phydev, 3);
phy_id |= val;
pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
/* Read internal PHY ID */
phy_write_paged(phydev, 31, 27, 0x0002);
val = phy_read_paged(phydev, 31, 28);
/* Internal RTL8218B, version 2 */
phydev_info(phydev, "Detected unknown %x\n", val);
return 0;
}
static int rtl821x_prepare_patch(struct phy_device *phydev, int ports)
{
struct phy_device *patchphy;
@ -828,22 +779,6 @@ static int rtl8380_configure_rtl8214fc(struct phy_device *phydev)
return 0;
}
static int rtl8390_configure_serdes(struct phy_device *phydev)
{
phydev_info(phydev, "Detected internal RTL8390 SERDES\n");
/* In autoneg state, force link, set SR4_CFG_EN_LINK_FIB1G */
sw_w32_mask(0, 1 << 18, RTL839X_SDS12_13_XSG0 + 0x0a);
/* Disable EEE: Clear FRE16_EEE_RSG_FIB1G, FRE16_EEE_STD_FIB1G,
* FRE16_C1_PWRSAV_EN_FIB1G, FRE16_C2_PWRSAV_EN_FIB1G
* and FRE16_EEE_QUIET_FIB1G
*/
sw_w32_mask(0x1f << 10, 0, RTL839X_SDS12_13_XSG0 + 0xe0);
return 0;
}
static int rtl8214fc_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
{
__ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, };
@ -985,33 +920,6 @@ static int rtl8218b_config_init(struct phy_device *phydev)
return 0;
}
static int rtl8393_serdes_probe(struct phy_device *phydev)
{
int addr = phydev->mdio.addr;
pr_info("%s: id: %d\n", __func__, addr);
if (soc_info.family != RTL8390_FAMILY_ID)
return -ENODEV;
if (addr < 24)
return -ENODEV;
return rtl8390_configure_serdes(phydev);
}
static int rtl8390_serdes_probe(struct phy_device *phydev)
{
int addr = phydev->mdio.addr;
if (soc_info.family != RTL8390_FAMILY_ID)
return -ENODEV;
if (addr < 24)
return -ENODEV;
return rtl8390_configure_generic(phydev);
}
static struct phy_driver rtl83xx_phy_driver[] = {
{
PHY_ID_MATCH_EXACT(PHY_ID_RTL8214C),
@ -1092,27 +1000,6 @@ static struct phy_driver rtl83xx_phy_driver[] = {
.write_mmd = rtl821x_write_mmd,
.write_page = rtl821x_write_page,
},
{
PHY_ID_MATCH_MODEL(PHY_ID_RTL8393_I),
.name = "Realtek RTL8393 SERDES",
.features = PHY_GBIT_FIBRE_FEATURES,
.probe = rtl8393_serdes_probe,
.read_page = rtl821x_read_page,
.write_page = rtl821x_write_page,
.suspend = genphy_suspend,
.resume = genphy_resume,
.read_status = rtl8393_read_status,
},
{
PHY_ID_MATCH_MODEL(PHY_ID_RTL8390_GENERIC),
.name = "Realtek RTL8390 Generic",
.features = PHY_GBIT_FIBRE_FEATURES,
.read_page = rtl821x_read_page,
.write_page = rtl821x_write_page,
.probe = rtl8390_serdes_probe,
.suspend = genphy_suspend,
.resume = genphy_resume,
},
};
module_phy_driver(rtl83xx_phy_driver);

6
target/linux/realtek/files-6.12/drivers/net/phy/rtl83xx-phy.h
View file

@ -25,9 +25,6 @@ struct __packed fw_header {
#define PHY_ID_RTL8218D 0x001cc983
#define PHY_ID_RTL8218E 0x001cc984
#define PHY_ID_RTL8218B_I 0x001cca40
#define PHY_ID_RTL8390_GENERIC 0x001ccab0
#define PHY_ID_RTL8393_I 0x001c8393
#define PHY_ID_RTL9300_I 0x338002a0
/* These PHYs share the same id (0x001cc981) */
#define PHY_IS_NOT_RTL821X 0
@ -35,6 +32,3 @@ struct __packed fw_header {
#define PHY_IS_RTL8214FB 2
#define PHY_IS_RTL8218B_E 3
/* Registers of the internal SerDes of the RTL8390 */
#define RTL839X_SDS12_13_XSG0 (0xB800)