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kernel: QCOM SPI NAND: backport multiple fixes
These patches fix bugs in a patch we backported. These patch were cherry picked from upstream Linux because it references a patch we backported in the fixes tag. The patches were reordered to match the ordering in the upstream Linux kernel. Fixes:93173aee96("qualcommbe: ipq95xx: Add initial support for new target") Link: https://github.com/openwrt/openwrt/pull/21366 (cherry picked from commit5230157a16) Link: https://github.com/openwrt/openwrt/pull/21390 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Hauke Mehrtens
parent
236149c306
commit
a78f0078c4
13 changed files with 441 additions and 6 deletions
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@ -0,0 +1,37 @@
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From 36c6468724aa98d33fea9a1d7e07ddda6302f5d4 Mon Sep 17 00:00:00 2001
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From: Geert Uytterhoeven <geert+renesas@glider.be>
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Date: Fri, 28 Mar 2025 09:24:01 +0100
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Subject: mtd: nand: Drop explicit test for built-in CONFIG_SPI_QPIC_SNAND
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If CONFIG_SPI_QPIC_SNAND=m, but CONFIG_MTD_NAND_QCOM=n:
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ERROR: modpost: "qcom_nandc_unalloc" [drivers/spi/spi-qpic-snand.ko] undefined!
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...
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Fix this by dropping the explicit test for a built-in
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CONFIG_SPI_QPIC_SNAND completely. Kbuild handles multiple and mixed
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obj-y/obj-m rules for the same object file fine.
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Reported-by: kernel test robot <lkp@intel.com>
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Closes: https://lore.kernel.org/oe-kbuild-all/202503280759.XhwLcV7m-lkp@intel.com/
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Fixes: 7304d1909080ef0c ("spi: spi-qpic: add driver for QCOM SPI NAND flash Interface")
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Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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---
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drivers/mtd/nand/Makefile | 3 ---
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1 file changed, 3 deletions(-)
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--- a/drivers/mtd/nand/Makefile
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+++ b/drivers/mtd/nand/Makefile
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@@ -3,11 +3,8 @@
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nandcore-objs := core.o bbt.o
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obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o
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obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) += ecc-mtk.o
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-ifeq ($(CONFIG_SPI_QPIC_SNAND),y)
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obj-$(CONFIG_SPI_QPIC_SNAND) += qpic_common.o
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-else
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obj-$(CONFIG_MTD_NAND_QCOM) += qpic_common.o
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-endif
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obj-y += onenand/
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obj-y += raw/
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obj-y += spi/
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@ -0,0 +1,113 @@
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From 2abf107dcd797c60c86e9f17319cd1658862f6b2 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <j4g8y7@gmail.com>
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Date: Thu, 15 May 2025 20:58:05 +0200
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Subject: spi: spi-qpic-snand: use CW_PER_PAGE_MASK bitmask
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Change the code to use the already defined CW_PER_PAGE_MASK
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bitmask along with the FIELD_PREP() macro instead of using
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magic values.
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This makes the code more readable. It also syncs the affected
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codes with their counterparts in the 'qcom_nandc' driver, so it
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makes it easier to spot the differences between the two
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implementations.
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No functional changes intended.
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Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
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Reviewed-by: Md Sadre Alam <quic_mdalam@quicinc.com>
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Link: https://patch.msgid.link/20250515-qpic-snand-use-bitmasks-v1-1-11729aeae73b@gmail.com
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Signed-off-by: Mark Brown <broonie@kernel.org>
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---
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drivers/spi/spi-qpic-snand.c | 31 ++++++++++++++++---------------
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1 file changed, 16 insertions(+), 15 deletions(-)
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--- a/drivers/spi/spi-qpic-snand.c
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+++ b/drivers/spi/spi-qpic-snand.c
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@@ -483,7 +483,8 @@ static int qcom_spi_block_erase(struct q
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snandc->regs->cmd = snandc->qspi->cmd;
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snandc->regs->addr0 = snandc->qspi->addr1;
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snandc->regs->addr1 = snandc->qspi->addr2;
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- snandc->regs->cfg0 = cpu_to_le32(ecc_cfg->cfg0_raw & ~(7 << CW_PER_PAGE));
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+ snandc->regs->cfg0 = cpu_to_le32((ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) |
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+ FIELD_PREP(CW_PER_PAGE_MASK, 0));
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snandc->regs->cfg1 = cpu_to_le32(ecc_cfg->cfg1_raw);
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snandc->regs->exec = cpu_to_le32(1);
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@@ -544,8 +545,8 @@ static int qcom_spi_read_last_cw(struct
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snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
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snandc->regs->addr1 = snandc->qspi->addr2;
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- cfg0 = (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) |
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- 0 << CW_PER_PAGE;
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+ cfg0 = (ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) |
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+ FIELD_PREP(CW_PER_PAGE_MASK, 0);
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cfg1 = ecc_cfg->cfg1_raw;
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ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
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@@ -687,8 +688,8 @@ static int qcom_spi_read_cw_raw(struct q
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qcom_clear_bam_transaction(snandc);
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raw_cw = num_cw - 1;
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- cfg0 = (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) |
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- 0 << CW_PER_PAGE;
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+ cfg0 = (ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) |
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+ FIELD_PREP(CW_PER_PAGE_MASK, 0);
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cfg1 = ecc_cfg->cfg1_raw;
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ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
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@@ -808,8 +809,8 @@ static int qcom_spi_read_page_ecc(struct
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snandc->buf_start = 0;
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qcom_clear_read_regs(snandc);
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- cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) |
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- (num_cw - 1) << CW_PER_PAGE;
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+ cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) |
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+ FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1);
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cfg1 = ecc_cfg->cfg1;
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ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
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@@ -904,8 +905,8 @@ static int qcom_spi_read_page_oob(struct
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qcom_clear_read_regs(snandc);
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qcom_clear_bam_transaction(snandc);
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- cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) |
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- (num_cw - 1) << CW_PER_PAGE;
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+ cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) |
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+ FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1);
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cfg1 = ecc_cfg->cfg1;
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ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
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@@ -1015,8 +1016,8 @@ static int qcom_spi_program_raw(struct q
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int num_cw = snandc->qspi->num_cw;
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u32 cfg0, cfg1, ecc_bch_cfg;
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- cfg0 = (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) |
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- (num_cw - 1) << CW_PER_PAGE;
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+ cfg0 = (ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) |
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+ FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1);
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cfg1 = ecc_cfg->cfg1_raw;
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ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
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@@ -1098,8 +1099,8 @@ static int qcom_spi_program_ecc(struct q
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int num_cw = snandc->qspi->num_cw;
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u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg;
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- cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) |
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- (num_cw - 1) << CW_PER_PAGE;
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+ cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) |
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+ FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1);
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cfg1 = ecc_cfg->cfg1;
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ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
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ecc_buf_cfg = ecc_cfg->ecc_buf_cfg;
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@@ -1175,8 +1176,8 @@ static int qcom_spi_program_oob(struct q
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int num_cw = snandc->qspi->num_cw;
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u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg;
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- cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) |
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- (num_cw - 1) << CW_PER_PAGE;
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+ cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) |
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+ FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1);
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cfg1 = ecc_cfg->cfg1;
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ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
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ecc_buf_cfg = ecc_cfg->ecc_buf_cfg;
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@ -0,0 +1,81 @@
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From d85d0380292a7e618915069c3579ae23c7c80339 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <j4g8y7@gmail.com>
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Date: Wed, 18 Jun 2025 22:22:49 +0200
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Subject: spi: spi-qpic-snand: reallocate BAM transactions
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Using the mtd_nandbiterrs module for testing the driver occasionally
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results in weird things like below.
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1. swiotlb mapping fails with the following message:
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[ 85.926216] qcom_snand 79b0000.spi: swiotlb buffer is full (sz: 4294967294 bytes), total 512 (slots), used 0 (slots)
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[ 85.932937] qcom_snand 79b0000.spi: failure in mapping desc
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[ 87.999314] qcom_snand 79b0000.spi: failure to write raw page
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[ 87.999352] mtd_nandbiterrs: error: write_oob failed (-110)
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Rebooting the board after this causes a panic due to a NULL pointer
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dereference.
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2. If the swiotlb mapping does not fail, rebooting the board may result
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in a different panic due to a bad spinlock magic:
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[ 256.104459] BUG: spinlock bad magic on CPU#3, procd/2241
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[ 256.104488] Unable to handle kernel paging request at virtual address ffffffff0000049b
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...
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Investigating the issue revealed that these symptoms are results of
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memory corruption which is caused by out of bounds access within the
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driver.
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The driver uses a dynamically allocated structure for BAM transactions,
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which structure must have enough space for all possible variations of
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different flash operations initiated by the driver. The required space
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heavily depends on the actual number of 'codewords' which is calculated
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from the pagesize of the actual NAND chip.
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Although the qcom_nandc_alloc() function allocates memory for the BAM
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transactions during probe, but since the actual number of 'codewords'
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is not yet know the allocation is done for one 'codeword' only.
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Because of this, whenever the driver does a flash operation, and the
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number of the required transactions exceeds the size of the allocated
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arrays the driver accesses memory out of the allocated range.
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To avoid this, change the code to free the initially allocated BAM
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transactions memory, and allocate a new one once the actual number of
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'codewords' required for a given NAND chip is known.
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Fixes: 7304d1909080 ("spi: spi-qpic: add driver for QCOM SPI NAND flash Interface")
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Reviewed-by: Md Sadre Alam <quic_mdalam@quicinc.com>
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Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
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Link: https://patch.msgid.link/20250618-qpic-snand-avoid-mem-corruption-v3-1-319c71296cda@gmail.com
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Signed-off-by: Mark Brown <broonie@kernel.org>
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---
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drivers/spi/spi-qpic-snand.c | 16 ++++++++++++++++
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1 file changed, 16 insertions(+)
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--- a/drivers/spi/spi-qpic-snand.c
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+++ b/drivers/spi/spi-qpic-snand.c
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@@ -315,6 +315,22 @@ static int qcom_spi_ecc_init_ctx_pipelin
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mtd_set_ooblayout(mtd, &qcom_spi_ooblayout);
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+ /*
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+ * Free the temporary BAM transaction allocated initially by
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+ * qcom_nandc_alloc(), and allocate a new one based on the
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+ * updated max_cwperpage value.
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+ */
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+ qcom_free_bam_transaction(snandc);
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+
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+ snandc->max_cwperpage = cwperpage;
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+
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+ snandc->bam_txn = qcom_alloc_bam_transaction(snandc);
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+ if (!snandc->bam_txn) {
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+ dev_err(snandc->dev, "failed to allocate BAM transaction\n");
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+ ret = -ENOMEM;
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+ goto err_free_ecc_cfg;
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+ }
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+
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ecc_cfg->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) |
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FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_data) |
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FIELD_PREP(DISABLE_STATUS_AFTER_WRITE, 1) |
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@ -0,0 +1,31 @@
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From f820034864dd463cdcd2bebe7940f2eca0eb4223 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <j4g8y7@gmail.com>
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Date: Wed, 23 Jul 2025 10:06:43 +0200
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Subject: spi: spi-qpic-snand: don't hardcode ECC steps
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NAND devices with different page sizes requires different number
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of ECC steps, yet the qcom_spi_ecc_init_ctx_pipelined() function
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sets 4 steps in 'ecc_cfg' unconditionally.
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The correct number of the steps is calculated earlier in the
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function already, so use that instead of the hardcoded value.
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Fixes: 7304d1909080 ("spi: spi-qpic: add driver for QCOM SPI NAND flash Interface")
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Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
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Link: https://patch.msgid.link/20250723-qpic-snand-fix-steps-v1-1-d800695dde4c@gmail.com
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Signed-off-by: Mark Brown <broonie@kernel.org>
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---
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drivers/spi/spi-qpic-snand.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/drivers/spi/spi-qpic-snand.c
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+++ b/drivers/spi/spi-qpic-snand.c
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@@ -308,7 +308,7 @@ static int qcom_spi_ecc_init_ctx_pipelin
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ecc_cfg->bch_enabled = true;
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ecc_cfg->bytes = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes + ecc_cfg->bbm_size;
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- ecc_cfg->steps = 4;
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+ ecc_cfg->steps = cwperpage;
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ecc_cfg->cw_data = 516;
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ecc_cfg->cw_size = ecc_cfg->cw_data + ecc_cfg->bytes;
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bad_block_byte = mtd->writesize - ecc_cfg->cw_size * (cwperpage - 1) + 1;
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@ -52,7 +52,7 @@ Signed-off-by: Mark Brown <broonie@kernel.org>
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host->ecc_bytes_hw = 8;
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--- a/drivers/spi/spi-qpic-snand.c
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+++ b/drivers/spi/spi-qpic-snand.c
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@@ -349,7 +349,7 @@ static int qcom_spi_ecc_init_ctx_pipelin
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@@ -365,7 +365,7 @@ static int qcom_spi_ecc_init_ctx_pipelin
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FIELD_PREP(ECC_SW_RESET, 0) |
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FIELD_PREP(ECC_NUM_DATA_BYTES_MASK, ecc_cfg->cw_data) |
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FIELD_PREP(ECC_FORCE_CLK_OPEN, 1) |
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@ -55,7 +55,7 @@ Signed-off-by: Mark Brown <broonie@kernel.org>
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ecc_cfg->bbm_size = 1;
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ecc_cfg->bch_enabled = true;
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ecc_cfg->bytes = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes + ecc_cfg->bbm_size;
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@@ -349,7 +360,7 @@ static int qcom_spi_ecc_init_ctx_pipelin
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@@ -365,7 +376,7 @@ static int qcom_spi_ecc_init_ctx_pipelin
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FIELD_PREP(ECC_SW_RESET, 0) |
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FIELD_PREP(ECC_NUM_DATA_BYTES_MASK, ecc_cfg->cw_data) |
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FIELD_PREP(ECC_FORCE_CLK_OPEN, 1) |
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@ -0,0 +1,56 @@
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From 6bc829220b33da8522572cc50fdf5067c51d3bf3 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <j4g8y7@gmail.com>
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Date: Fri, 1 Aug 2025 09:58:35 +0200
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Subject: spi: spi-qpic-snand: use correct CW_PER_PAGE value for OOB write
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The qcom_spi_program_oob() function uses only the last codeword to write
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the OOB data into the flash, but it sets the CW_PER_PAGE field in the
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CFG0 register as it would use all codewords.
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It seems that this confuses the hardware somehow, and any access to the
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flash fails with a timeout error after the function is called. The problem
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can be easily reproduced with the following commands:
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# dd if=/dev/zero bs=2176 count=1 > /tmp/test.bin
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1+0 records in
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1+0 records out
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# flash_erase /dev/mtd4 0 0
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Erasing 128 Kibyte @ 0 -- 100 % complete
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# nandwrite -O /dev/mtd4 /tmp/test.bin
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Writing data to block 0 at offset 0x0
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# nanddump -o /dev/mtd4 >/dev/null
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ECC failed: 0
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ECC corrected: 0
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Number of bad blocks: 0
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Number of bbt blocks: 0
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Block size 131072, page size 2048, OOB size 128
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Dumping data starting at 0x00000000 and ending at 0x00020000...
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[ 33.197605] qcom_snand 79b0000.spi: failure to read oob
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libmtd: error!: MEMREADOOB64 ioctl failed for mtd4, offset 0 (eraseblock 0)
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error 110 (Operation timed out)
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[ 35.277582] qcom_snand 79b0000.spi: failure in submitting cmd descriptor
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libmtd: error!: cannot read 2048 bytes from mtd4 (eraseblock 0, offset 2048)
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error 110 (Operation timed out)
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nanddump: error!: mtd_read
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Change the code to use the correct CW_PER_PAGE value to avoid this.
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Fixes: 7304d1909080 ("spi: spi-qpic: add driver for QCOM SPI NAND flash Interface")
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Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
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Link: https://patch.msgid.link/20250801-qpic-snand-oob-cwpp-fix-v1-1-f5a41b86af2e@gmail.com
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Signed-off-by: Mark Brown <broonie@kernel.org>
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---
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drivers/spi/spi-qpic-snand.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/drivers/spi/spi-qpic-snand.c
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+++ b/drivers/spi/spi-qpic-snand.c
|
||||
@@ -1204,7 +1204,7 @@ static int qcom_spi_program_oob(struct q
|
||||
u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg;
|
||||
|
||||
cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) |
|
||||
- FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1);
|
||||
+ FIELD_PREP(CW_PER_PAGE_MASK, 0);
|
||||
cfg1 = ecc_cfg->cfg1;
|
||||
ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
|
||||
ecc_buf_cfg = ecc_cfg->ecc_buf_cfg;
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
From 13d0fe84a214658254a7412b2b46ec1507dc51f0 Mon Sep 17 00:00:00 2001
|
||||
From: Gabor Juhos <j4g8y7@gmail.com>
|
||||
Date: Tue, 5 Aug 2025 18:05:42 +0200
|
||||
Subject: spi: spi-qpic-snand: fix calculating of ECC OOB regions' properties
|
||||
|
||||
The OOB layout used by the driver has two distinct regions which contains
|
||||
hardware specific ECC data, yet the qcom_spi_ooblayout_ecc() function sets
|
||||
the same offset and length values for both regions which is clearly wrong.
|
||||
|
||||
Change the code to calculate the correct values for both regions.
|
||||
|
||||
For reference, the following table shows the computed offset and length
|
||||
values for various OOB size/ECC strength configurations:
|
||||
|
||||
+-----------------+-----------------+
|
||||
|before the change| after the change|
|
||||
+-------+----------+--------+--------+--------+--------+--------+
|
||||
| OOB | ECC | region | region | region | region | region |
|
||||
| size | strength | index | offset | length | offset | length |
|
||||
+-------+----------+--------+--------+--------+--------+--------+
|
||||
| 128 | 8 | 0 | 113 | 15 | 0 | 49 |
|
||||
| | | 1 | 113 | 15 | 65 | 63 |
|
||||
+-------+----------+--------+--------+--------+--------+--------+
|
||||
| 128 | 4 | 0 | 117 | 11 | 0 | 37 |
|
||||
| | | 1 | 117 | 11 | 53 | 75 |
|
||||
+-------+----------+--------+--------+--------+--------+--------+
|
||||
| 64 | 4 | 0 | 53 | 11 | 0 | 37 |
|
||||
| | | 1 | 53 | 11 | 53 | 11 |
|
||||
+-------+----------+--------+--------+--------+--------+--------+
|
||||
|
||||
Fixes: 7304d1909080 ("spi: spi-qpic: add driver for QCOM SPI NAND flash Interface")
|
||||
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
|
||||
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
|
||||
Link: https://patch.msgid.link/20250805-qpic-snand-oob-ecc-fix-v2-1-e6f811c70d6f@gmail.com
|
||||
Signed-off-by: Mark Brown <broonie@kernel.org>
|
||||
---
|
||||
drivers/spi/spi-qpic-snand.c | 20 ++++++++++++++------
|
||||
1 file changed, 14 insertions(+), 6 deletions(-)
|
||||
|
||||
--- a/drivers/spi/spi-qpic-snand.c
|
||||
+++ b/drivers/spi/spi-qpic-snand.c
|
||||
@@ -216,13 +216,21 @@ static int qcom_spi_ooblayout_ecc(struct
|
||||
struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
|
||||
struct qpic_ecc *qecc = snandc->qspi->ecc;
|
||||
|
||||
- if (section > 1)
|
||||
- return -ERANGE;
|
||||
+ switch (section) {
|
||||
+ case 0:
|
||||
+ oobregion->offset = 0;
|
||||
+ oobregion->length = qecc->bytes * (qecc->steps - 1) +
|
||||
+ qecc->bbm_size;
|
||||
+ return 0;
|
||||
+ case 1:
|
||||
+ oobregion->offset = qecc->bytes * (qecc->steps - 1) +
|
||||
+ qecc->bbm_size +
|
||||
+ qecc->steps * 4;
|
||||
+ oobregion->length = mtd->oobsize - oobregion->offset;
|
||||
+ return 0;
|
||||
+ }
|
||||
|
||||
- oobregion->length = qecc->ecc_bytes_hw + qecc->spare_bytes;
|
||||
- oobregion->offset = mtd->oobsize - oobregion->length;
|
||||
-
|
||||
- return 0;
|
||||
+ return -ERANGE;
|
||||
}
|
||||
|
||||
static int qcom_spi_ooblayout_free(struct mtd_info *mtd, int section,
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
From 1991a458528588ff34e98b6365362560d208710f Mon Sep 17 00:00:00 2001
|
||||
From: Gabor Juhos <j4g8y7@gmail.com>
|
||||
Date: Wed, 3 Sep 2025 13:56:24 +0200
|
||||
Subject: spi: spi-qpic-snand: unregister ECC engine on probe error and device
|
||||
remove
|
||||
|
||||
The on-host hardware ECC engine remains registered both when
|
||||
the spi_register_controller() function returns with an error
|
||||
and also on device removal.
|
||||
|
||||
Change the qcom_spi_probe() function to unregister the engine
|
||||
on the error path, and add the missing unregistering call to
|
||||
qcom_spi_remove() to avoid possible use-after-free issues.
|
||||
|
||||
Fixes: 7304d1909080 ("spi: spi-qpic: add driver for QCOM SPI NAND flash Interface")
|
||||
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
|
||||
Message-ID: <20250903-qpic-snand-unregister-ecceng-v1-1-ef5387b0abdc@gmail.com>
|
||||
Signed-off-by: Mark Brown <broonie@kernel.org>
|
||||
---
|
||||
drivers/spi/spi-qpic-snand.c | 6 ++++--
|
||||
1 file changed, 4 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/spi/spi-qpic-snand.c
|
||||
+++ b/drivers/spi/spi-qpic-snand.c
|
||||
@@ -1632,11 +1632,13 @@ static int qcom_spi_probe(struct platfor
|
||||
ret = spi_register_controller(ctlr);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "spi_register_controller failed.\n");
|
||||
- goto err_spi_init;
|
||||
+ goto err_register_controller;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
+err_register_controller:
|
||||
+ nand_ecc_unregister_on_host_hw_engine(&snandc->qspi->ecc_eng);
|
||||
err_spi_init:
|
||||
qcom_nandc_unalloc(snandc);
|
||||
err_snand_alloc:
|
||||
@@ -1658,7 +1660,7 @@ static void qcom_spi_remove(struct platf
|
||||
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
|
||||
spi_unregister_controller(ctlr);
|
||||
-
|
||||
+ nand_ecc_unregister_on_host_hw_engine(&snandc->qspi->ecc_eng);
|
||||
qcom_nandc_unalloc(snandc);
|
||||
|
||||
clk_disable_unprepare(snandc->aon_clk);
|
||||
|
|
@ -28,6 +28,6 @@ Subject: [PATCH] mtd/nand: add MediaTek NAND bad block managment table
|
|||
obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o
|
||||
obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) += ecc-mtk.o
|
||||
+obj-$(CONFIG_MTD_NAND_MTK_BMT) += mtk_bmt.o mtk_bmt_v2.o mtk_bmt_bbt.o mtk_bmt_nmbm.o
|
||||
ifeq ($(CONFIG_SPI_QPIC_SNAND),y)
|
||||
obj-$(CONFIG_SPI_QPIC_SNAND) += qpic_common.o
|
||||
else
|
||||
obj-$(CONFIG_MTD_NAND_QCOM) += qpic_common.o
|
||||
obj-y += onenand/
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|||
|
||||
--- a/drivers/spi/spi-qpic-snand.c
|
||||
+++ b/drivers/spi/spi-qpic-snand.c
|
||||
@@ -296,6 +296,24 @@ static int qcom_spi_ecc_init_ctx_pipelin
|
||||
@@ -304,6 +304,24 @@ static int qcom_spi_ecc_init_ctx_pipelin
|
||||
ecc_cfg->spare_bytes = 2;
|
||||
break;
|
||||
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
|
|||
+obj-$(CONFIG_MTD_NAND_ECC_REALTEK) += ecc-realtek.o
|
||||
obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) += ecc-mtk.o
|
||||
obj-$(CONFIG_MTD_NAND_MTK_BMT) += mtk_bmt.o mtk_bmt_v2.o mtk_bmt_bbt.o mtk_bmt_nmbm.o
|
||||
ifeq ($(CONFIG_SPI_QPIC_SNAND),y)
|
||||
obj-$(CONFIG_SPI_QPIC_SNAND) += qpic_common.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/mtd/nand/ecc-realtek.c
|
||||
@@ -0,0 +1,464 @@
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue