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octeon: set kernel 6.12 as default and remove support for 6.6
Some checks are pending
Build Kernel / Build all affected Kernels (push) Waiting to run
Some checks are pending
Build Kernel / Build all affected Kernels (push) Waiting to run
Get the Octeon target ready for the next OpenWrt release. Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
This commit is contained in:
parent
16740f623e
commit
a6ea2aa2b9
12 changed files with 1 additions and 768 deletions
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@ -10,7 +10,7 @@ BOARDNAME:=Cavium Networks Octeon
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FEATURES:=squashfs ramdisk pci usb
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CPU_TYPE:=octeonplus
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KERNEL_PATCHVER:=6.6
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KERNEL_PATCHVER:=6.12
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define Target/Description
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Build firmware images for Cavium Networks Octeon-based boards.
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@ -1,281 +0,0 @@
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CONFIG_64BIT=y
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CONFIG_AHCI_OCTEON=y
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CONFIG_ARCH_DMA_ADDR_T_64BIT=y
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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CONFIG_ARCH_KEEP_MEMBLOCK=y
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CONFIG_ARCH_MMAP_RND_BITS=12
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CONFIG_ARCH_MMAP_RND_BITS_MAX=18
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CONFIG_ARCH_MMAP_RND_BITS_MIN=12
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CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
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CONFIG_ARCH_SPARSEMEM_ENABLE=y
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CONFIG_ARCH_SUSPEND_POSSIBLE=y
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CONFIG_AT803X_PHY=y
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CONFIG_ATA=y
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CONFIG_BLK_DEV_LOOP=y
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CONFIG_BLK_DEV_SD=y
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CONFIG_BLK_MQ_PCI=y
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CONFIG_BUFFER_HEAD=y
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CONFIG_BUILTIN_DTB=y
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CONFIG_CAVIUM_CN63XXP1=y
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CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=0
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CONFIG_CAVIUM_OCTEON_LOCK_L2=y
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CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION=y
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CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT=y
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CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT=y
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CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY=y
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CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB=y
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CONFIG_CAVIUM_OCTEON_SOC=y
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CONFIG_CAVIUM_RESERVE32=0
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CONFIG_CEVT_R4K=y
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CONFIG_CLONE_BACKWARDS=y
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# CONFIG_COMMON_CLK is not set
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CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
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CONFIG_COMPAT_32BIT_TIME=y
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CONFIG_CONTEXT_TRACKING=y
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CONFIG_CONTEXT_TRACKING_IDLE=y
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CONFIG_CPU_BIG_ENDIAN=y
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CONFIG_CPU_CAVIUM_OCTEON=y
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CONFIG_CPU_GENERIC_DUMP_TLB=y
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CONFIG_CPU_HAS_DIEI=y
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CONFIG_CPU_HAS_PREFETCH=y
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CONFIG_CPU_HAS_RIXI=y
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CONFIG_CPU_HAS_SYNC=y
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CONFIG_CPU_MIPS64=y
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CONFIG_CPU_MIPSR2=y
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CONFIG_CPU_MITIGATIONS=y
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CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
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CONFIG_CPU_R4K_FPU=y
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CONFIG_CPU_RMAP=y
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CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
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CONFIG_CPU_SUPPORTS_HIGHMEM=y
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CONFIG_CPU_SUPPORTS_HUGEPAGES=y
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CONFIG_CRAMFS=y
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CONFIG_CRC16=y
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CONFIG_CRYPTO_CRC32=y
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CONFIG_CRYPTO_CRC32C=y
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CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
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CONFIG_CRYPTO_LIB_GF128MUL=y
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CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
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CONFIG_CRYPTO_LIB_SHA1=y
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CONFIG_CRYPTO_LIB_UTILS=y
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# CONFIG_CRYPTO_MD5_OCTEON is not set
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# CONFIG_CRYPTO_SHA1_OCTEON is not set
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# CONFIG_CRYPTO_SHA256_OCTEON is not set
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# CONFIG_CRYPTO_SHA512_OCTEON is not set
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# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set
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CONFIG_DEBUG_INFO_NONE=y
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CONFIG_DEPRECATED_IRQ_CPU_ONOFFLINE=y
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CONFIG_DNOTIFY=y
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CONFIG_DTC=y
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CONFIG_EARLY_PRINTK=y
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CONFIG_EDAC=y
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CONFIG_EDAC_ATOMIC_SCRUB=y
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# CONFIG_EDAC_DEBUG is not set
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CONFIG_EDAC_LEGACY_SYSFS=y
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CONFIG_EDAC_OCTEON_L2C=y
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CONFIG_EDAC_OCTEON_LMC=y
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CONFIG_EDAC_OCTEON_PC=y
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CONFIG_EDAC_OCTEON_PCI=y
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CONFIG_EDAC_SUPPORT=y
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CONFIG_EEPROM_AT24=y
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CONFIG_EXCLUSIVE_SYSTEM_RAM=y
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CONFIG_EXT4_FS=y
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CONFIG_F2FS_FS=y
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CONFIG_FAT_FS=y
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CONFIG_FIXED_PHY=y
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CONFIG_FS_IOMAP=y
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CONFIG_FS_MBCACHE=y
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CONFIG_FUNCTION_ALIGNMENT=0
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CONFIG_FWNODE_MDIO=y
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CONFIG_FW_LOADER_PAGED_BUF=y
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CONFIG_FW_LOADER_SYSFS=y
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CONFIG_GENERIC_ALLOCATOR=y
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CONFIG_GENERIC_CLOCKEVENTS=y
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CONFIG_GENERIC_CMOS_UPDATE=y
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CONFIG_GENERIC_CPU_AUTOPROBE=y
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CONFIG_GENERIC_GETTIMEOFDAY=y
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CONFIG_GENERIC_IDLE_POLL_SETUP=y
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CONFIG_GENERIC_IOMAP=y
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CONFIG_GENERIC_IRQ_SHOW=y
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CONFIG_GENERIC_LIB_ASHLDI3=y
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CONFIG_GENERIC_LIB_ASHRDI3=y
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CONFIG_GENERIC_LIB_CMPDI2=y
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CONFIG_GENERIC_LIB_LSHRDI3=y
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CONFIG_GENERIC_LIB_UCMPDI2=y
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CONFIG_GENERIC_PCI_IOMAP=y
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CONFIG_GENERIC_SMP_IDLE_THREAD=y
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CONFIG_GENERIC_TIME_VSYSCALL=y
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CONFIG_GLOB=y
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CONFIG_GPIO_CDEV=y
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CONFIG_GPIO_OCTEON=y
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CONFIG_GRO_CELLS=y
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CONFIG_HARDWARE_WATCHPOINTS=y
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CONFIG_HAS_DMA=y
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CONFIG_HAS_IOMEM=y
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CONFIG_HAS_IOPORT=y
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CONFIG_HAS_IOPORT_MAP=y
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CONFIG_HW_RANDOM=y
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CONFIG_HW_RANDOM_OCTEON=y
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CONFIG_HZ_PERIODIC=y
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CONFIG_I2C=y
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CONFIG_I2C_BOARDINFO=y
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CONFIG_I2C_OCTEON=y
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CONFIG_IMAGE_CMDLINE_HACK=y
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CONFIG_INITRAMFS_SOURCE=""
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CONFIG_IRQCHIP=y
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CONFIG_IRQ_DOMAIN=y
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CONFIG_IRQ_FORCED_THREADING=y
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CONFIG_IRQ_WORK=y
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CONFIG_JBD2=y
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CONFIG_LEGACY_DIRECT_IO=y
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CONFIG_LIBFDT=y
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CONFIG_LOCK_DEBUGGING_SUPPORT=y
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CONFIG_MDIO_BUS=y
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CONFIG_MDIO_CAVIUM=y
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CONFIG_MDIO_DEVICE=y
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CONFIG_MDIO_DEVRES=y
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CONFIG_MDIO_OCTEON=y
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CONFIG_MIGRATION=y
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CONFIG_MIPS=y
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CONFIG_MIPS_ASID_BITS=8
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CONFIG_MIPS_ASID_SHIFT=0
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CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
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CONFIG_MIPS_ELF_APPENDED_DTB=y
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CONFIG_MIPS_FP_SUPPORT=y
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CONFIG_MIPS_L1_CACHE_SHIFT=7
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CONFIG_MIPS_L1_CACHE_SHIFT_7=y
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# CONFIG_MIPS_NO_APPENDED_DTB is not set
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CONFIG_MIPS_NR_CPU_NR_MAP=1024
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CONFIG_MIPS_NR_CPU_NR_MAP_1024=y
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CONFIG_MIPS_PGD_C0_CONTEXT=y
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CONFIG_MIPS_SPRAM=y
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CONFIG_MMC=y
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CONFIG_MMC_BLOCK=y
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CONFIG_MMC_CAVIUM_OCTEON=y
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CONFIG_MMU_LAZY_TLB_REFCOUNT=y
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CONFIG_MODULES_USE_ELF_REL=y
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CONFIG_MODULES_USE_ELF_RELA=y
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# CONFIG_MTD_CFI_INTELEXT is not set
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CONFIG_MTD_CMDLINE_PARTS=y
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CONFIG_MTD_PHYSMAP=y
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CONFIG_MTD_SPI_NOR=y
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CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
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CONFIG_NEED_DMA_MAP_STATE=y
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CONFIG_NEED_SRCU_NMI_SAFE=y
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CONFIG_NET_DEVLINK=y
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CONFIG_NET_DSA=y
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CONFIG_NET_EGRESS=y
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CONFIG_NET_FLOW_LIMIT=y
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CONFIG_NET_INGRESS=y
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CONFIG_NET_SELFTESTS=y
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CONFIG_NET_XGRESS=y
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CONFIG_NLS=y
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CONFIG_NLS_CODEPAGE_437=y
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CONFIG_NLS_ISO8859_1=y
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CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
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CONFIG_NR_CPUS=16
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CONFIG_NR_CPUS_DEFAULT_64=y
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CONFIG_NVMEM=y
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CONFIG_NVMEM_LAYOUTS=y
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CONFIG_NVMEM_SYSFS=y
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CONFIG_OCTEON_ETHERNET=y
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CONFIG_OCTEON_ILM=y
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CONFIG_OCTEON_MGMT_ETHERNET=y
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CONFIG_OCTEON_WDT=y
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CONFIG_OF=y
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CONFIG_OF_ADDRESS=y
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CONFIG_OF_EARLY_FLATTREE=y
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CONFIG_OF_FLATTREE=y
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CONFIG_OF_GPIO=y
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CONFIG_OF_IRQ=y
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CONFIG_OF_KOBJ=y
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CONFIG_OF_MDIO=y
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CONFIG_PADATA=y
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CONFIG_PAGE_POOL=y
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CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
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CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
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# CONFIG_PARTITION_ADVANCED is not set
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CONFIG_PATA_OCTEON_CF=y
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CONFIG_PATA_TIMINGS=y
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CONFIG_PCI=y
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CONFIG_PCIEAER=y
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CONFIG_PCIEPORTBUS=y
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CONFIG_PCI_DOMAINS=y
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CONFIG_PCI_DRIVERS_LEGACY=y
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CONFIG_PERF_USE_VMALLOC=y
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CONFIG_PGTABLE_LEVELS=3
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CONFIG_PHYLIB=y
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CONFIG_PHYLIB_LEDS=y
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CONFIG_PHYLINK=y
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CONFIG_PHYS_ADDR_T_64BIT=y
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CONFIG_POSIX_MQUEUE=y
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CONFIG_POSIX_MQUEUE_SYSCTL=y
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CONFIG_PREEMPT_NONE_BUILD=y
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CONFIG_PTP_1588_CLOCK_OPTIONAL=y
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CONFIG_QUEUED_RWLOCKS=y
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CONFIG_QUEUED_SPINLOCKS=y
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CONFIG_RANDSTRUCT_NONE=y
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CONFIG_RAS=y
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CONFIG_REGMAP=y
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CONFIG_REGMAP_I2C=y
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CONFIG_REGULATOR=y
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CONFIG_RELAY=y
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CONFIG_RFS_ACCEL=y
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CONFIG_RPS=y
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CONFIG_SATA_AHCI_PLATFORM=y
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CONFIG_SATA_HOST=y
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CONFIG_SCSI=y
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CONFIG_SCSI_COMMON=y
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CONFIG_SERIAL_8250_DW=y
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CONFIG_SERIAL_8250_DWLIB=y
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CONFIG_SERIAL_MCTRL_GPIO=y
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CONFIG_SG_POOL=y
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CONFIG_SMP=y
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CONFIG_SOCK_RX_QUEUE_MAPPING=y
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CONFIG_SPARSEMEM=y
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CONFIG_SPARSEMEM_EXTREME=y
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CONFIG_SPI=y
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CONFIG_SPI_MASTER=y
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CONFIG_SPI_MEM=y
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CONFIG_SPI_OCTEON=y
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CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
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CONFIG_SWIOTLB=y
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CONFIG_SWPHY=y
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CONFIG_SYSCTL_EXCEPTION_TRACE=y
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CONFIG_SYS_HAS_CPU_CAVIUM_OCTEON=y
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CONFIG_SYS_HAS_EARLY_PRINTK=y
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CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
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CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
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CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
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CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y
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CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
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CONFIG_SYS_SUPPORTS_RELOCATABLE=y
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CONFIG_SYS_SUPPORTS_SMP=y
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CONFIG_TARGET_ISA_REV=2
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CONFIG_TICK_CPU_ACCOUNTING=y
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CONFIG_TREE_RCU=y
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CONFIG_TREE_SRCU=y
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CONFIG_USB=y
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CONFIG_USB_COMMON=y
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CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_HCD_PLATFORM=y
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# CONFIG_USB_OCTEON_EHCI is not set
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CONFIG_USB_OCTEON_HCD=y
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# CONFIG_USB_OCTEON_OHCI is not set
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CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y
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CONFIG_USB_OHCI_HCD=y
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CONFIG_USB_OHCI_HCD_PLATFORM=y
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CONFIG_USB_STORAGE=y
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CONFIG_USB_SUPPORT=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_PLATFORM=y
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CONFIG_USE_OF=y
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CONFIG_VFAT_FS=y
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CONFIG_VITESSE_PHY=y
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CONFIG_VM_EVENT_COUNTERS=y
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CONFIG_WATCHDOG_CORE=y
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CONFIG_WEAK_ORDERING=y
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CONFIG_XPS=y
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CONFIG_ZLIB_INFLATE=y
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CONFIG_ZONE_DMA32=y
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@ -1,38 +0,0 @@
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From: John Crispin <john@phrozen.org>
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Subject: hack: kernel: add generic image_cmdline hack to MIPS targets
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lede-commit: d59f5b3a987a48508257a0ddbaeadc7909f9f976
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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---
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arch/mips/Kconfig | 4 ++++
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arch/mips/kernel/head.S | 6 ++++++
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2 files changed, 10 insertions(+)
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--- a/arch/mips/Kconfig
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+++ b/arch/mips/Kconfig
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@@ -1090,6 +1090,10 @@ config MIPS_MSC
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config SYNC_R4K
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bool
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+config IMAGE_CMDLINE_HACK
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+ bool "OpenWrt specific image command line hack"
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+ default n
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+
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config NO_IOPORT_MAP
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def_bool n
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--- a/arch/mips/kernel/head.S
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+++ b/arch/mips/kernel/head.S
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@@ -79,6 +79,12 @@ FEXPORT(__kernel_entry)
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j kernel_entry
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#endif /* CONFIG_BOOT_RAW */
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+#ifdef CONFIG_IMAGE_CMDLINE_HACK
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+ .ascii "CMDLINE:"
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+EXPORT(__image_cmdline)
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+ .fill 0x400
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+#endif /* CONFIG_IMAGE_CMDLINE_HACK */
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+
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__REF
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NESTED(kernel_entry, 16, sp) # kernel entry point
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@ -1,11 +0,0 @@
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--- a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
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+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
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@@ -174,6 +174,8 @@ int cvmx_helper_board_get_mii_address(in
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return 7 - ipd_port;
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else
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return -1;
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+ case CVMX_BOARD_TYPE_UBNT_E200:
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+ return -1;
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case CVMX_BOARD_TYPE_KONTRON_S1901:
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if (ipd_port == CVMX_HELPER_BOARD_MGMT_IPD_PORT)
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return 1;
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@ -1,34 +0,0 @@
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--- a/drivers/staging/octeon/ethernet.c
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+++ b/drivers/staging/octeon/ethernet.c
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@@ -676,6 +676,7 @@ static int cvm_oct_probe(struct platform
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int interface;
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int fau = FAU_NUM_PACKET_BUFFERS_TO_FREE;
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int qos;
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+ int i;
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struct device_node *pip;
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int mtu_overhead = ETH_HLEN + ETH_FCS_LEN;
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@@ -797,13 +798,19 @@ static int cvm_oct_probe(struct platform
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}
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num_interfaces = cvmx_helper_get_number_of_interfaces();
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- for (interface = 0; interface < num_interfaces; interface++) {
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- cvmx_helper_interface_mode_t imode =
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- cvmx_helper_interface_get_mode(interface);
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- int num_ports = cvmx_helper_ports_on_interface(interface);
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+ for (i = 0; i < num_interfaces; i++) {
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+ cvmx_helper_interface_mode_t imode;
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+ int interface;
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+ int num_ports;
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int port;
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int port_index;
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+ interface = i;
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+ if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_UBNT_E200)
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+ interface = num_interfaces - (i + 1);
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+
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+ num_ports = cvmx_helper_ports_on_interface(interface);
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+ imode = cvmx_helper_interface_get_mode(interface);
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for (port_index = 0,
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port = cvmx_helper_get_ipd_port(interface, 0);
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port < cvmx_helper_get_ipd_port(interface, num_ports);
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@ -1,47 +0,0 @@
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--- a/arch/mips/cavium-octeon/setup.c
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+++ b/arch/mips/cavium-octeon/setup.c
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@@ -653,6 +653,35 @@ void octeon_user_io_init(void)
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write_c0_derraddr1(0);
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}
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+#ifdef CONFIG_IMAGE_CMDLINE_HACK
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+extern char __image_cmdline[];
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+
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+static int __init octeon_use_image_cmdline(void)
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+{
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+ char *p = __image_cmdline;
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+ int replace = 0;
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||||
+
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||||
+ if (*p == '-') {
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+ replace = 1;
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+ p++;
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+ }
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+
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+ if (*p == '\0')
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+ return 0;
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+
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||||
+ if (replace) {
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+ strlcpy(arcs_cmdline, p, sizeof(arcs_cmdline));
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+ } else {
|
||||
+ strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
|
||||
+ strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
|
||||
+ }
|
||||
+
|
||||
+ return 1;
|
||||
+}
|
||||
+#else
|
||||
+static inline int octeon_use_image_cmdline(void) { return 0; }
|
||||
+#endif
|
||||
+
|
||||
/**
|
||||
* prom_init - Early entry point for arch setup
|
||||
*/
|
||||
@@ -896,6 +925,8 @@ void __init prom_init(void)
|
||||
}
|
||||
}
|
||||
|
||||
+ octeon_use_image_cmdline();
|
||||
+
|
||||
if (strstr(arcs_cmdline, "console=") == NULL) {
|
||||
if (octeon_uart == 1)
|
||||
strcat(arcs_cmdline, " console=ttyS1,115200");
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
--- a/arch/mips/cavium-octeon/octeon-platform.c
|
||||
+++ b/arch/mips/cavium-octeon/octeon-platform.c
|
||||
@@ -775,7 +775,7 @@ int __init octeon_prune_device_tree(void
|
||||
if (fdt_check_header(initial_boot_params))
|
||||
panic("Corrupt Device Tree.");
|
||||
|
||||
- WARN(octeon_bootinfo->board_type == CVMX_BOARD_TYPE_CUST_DSR1000N,
|
||||
+ WARN(octeon_bootinfo->board_type == CVMX_BOARD_TYPE_ITUS_SHIELD,
|
||||
"Built-in DTB booting is deprecated on %s. Please switch to use appended DTB.",
|
||||
cvmx_board_type_to_string(octeon_bootinfo->board_type));
|
||||
|
||||
--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h
|
||||
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
|
||||
@@ -298,7 +298,7 @@ enum cvmx_board_types_enum {
|
||||
CVMX_BOARD_TYPE_UBNT_E100 = 20002,
|
||||
CVMX_BOARD_TYPE_UBNT_E200 = 20003,
|
||||
CVMX_BOARD_TYPE_UBNT_E220 = 20005,
|
||||
- CVMX_BOARD_TYPE_CUST_DSR1000N = 20006,
|
||||
+ CVMX_BOARD_TYPE_ITUS_SHIELD = 20006,
|
||||
CVMX_BOARD_TYPE_UBNT_E300 = 20300,
|
||||
CVMX_BOARD_TYPE_KONTRON_S1901 = 21901,
|
||||
CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000,
|
||||
@@ -403,7 +403,7 @@ static inline const char *cvmx_board_typ
|
||||
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E100)
|
||||
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E200)
|
||||
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E220)
|
||||
- ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DSR1000N)
|
||||
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_ITUS_SHIELD)
|
||||
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E300)
|
||||
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KONTRON_S1901)
|
||||
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX)
|
||||
--- a/arch/mips/pci/pci-octeon.c
|
||||
+++ b/arch/mips/pci/pci-octeon.c
|
||||
@@ -211,7 +211,7 @@ const char *octeon_get_pci_interrupts(vo
|
||||
return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
|
||||
case CVMX_BOARD_TYPE_BBGW_REF:
|
||||
return "AABCD";
|
||||
- case CVMX_BOARD_TYPE_CUST_DSR1000N:
|
||||
+ case CVMX_BOARD_TYPE_ITUS_SHIELD:
|
||||
return "CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC";
|
||||
case CVMX_BOARD_TYPE_THUNDER:
|
||||
case CVMX_BOARD_TYPE_EBH3000:
|
||||
|
|
@ -1,46 +0,0 @@
|
|||
--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h
|
||||
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
|
||||
@@ -297,6 +297,7 @@ enum cvmx_board_types_enum {
|
||||
CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001,
|
||||
CVMX_BOARD_TYPE_UBNT_E100 = 20002,
|
||||
CVMX_BOARD_TYPE_UBNT_E200 = 20003,
|
||||
+ CVMX_BOARD_TYPE_UBNT_USG = 20004,
|
||||
CVMX_BOARD_TYPE_UBNT_E220 = 20005,
|
||||
CVMX_BOARD_TYPE_ITUS_SHIELD = 20006,
|
||||
CVMX_BOARD_TYPE_UBNT_E300 = 20300,
|
||||
@@ -401,6 +402,7 @@ static inline const char *cvmx_board_typ
|
||||
/* Customer private range */
|
||||
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN)
|
||||
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E100)
|
||||
+ ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_USG)
|
||||
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E200)
|
||||
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_UBNT_E220)
|
||||
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_ITUS_SHIELD)
|
||||
--- a/arch/mips/cavium-octeon/octeon-platform.c
|
||||
+++ b/arch/mips/cavium-octeon/octeon-platform.c
|
||||
@@ -636,6 +636,7 @@ static void __init octeon_rx_tx_delay(in
|
||||
}
|
||||
break;
|
||||
case CVMX_BOARD_TYPE_UBNT_E100:
|
||||
+ case CVMX_BOARD_TYPE_UBNT_USG:
|
||||
if (iface == 0 && port <= 2) {
|
||||
_octeon_rx_tx_delay(eth, 0x0, 0x10);
|
||||
return;
|
||||
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
|
||||
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
|
||||
@@ -170,6 +170,7 @@ int cvmx_helper_board_get_mii_address(in
|
||||
else
|
||||
return -1;
|
||||
case CVMX_BOARD_TYPE_UBNT_E100:
|
||||
+ case CVMX_BOARD_TYPE_UBNT_USG:
|
||||
if (ipd_port >= 0 && ipd_port <= 2)
|
||||
return 7 - ipd_port;
|
||||
else
|
||||
@@ -337,6 +338,7 @@ enum cvmx_helper_board_usb_clock_types _
|
||||
case CVMX_BOARD_TYPE_LANAI2_G:
|
||||
case CVMX_BOARD_TYPE_NIC10E_66:
|
||||
case CVMX_BOARD_TYPE_UBNT_E100:
|
||||
+ case CVMX_BOARD_TYPE_UBNT_USG:
|
||||
return USB_CLOCK_TYPE_CRYSTAL_12;
|
||||
case CVMX_BOARD_TYPE_NIC10E:
|
||||
return USB_CLOCK_TYPE_REF_12;
|
||||
|
|
@ -1,81 +0,0 @@
|
|||
commit eb6c3ba1d42fd087708f568ca220ff557f22104e
|
||||
Author: Jakob Haufe <sur5r@sur5r.net>
|
||||
Date: Tue Jun 17 13:58:19 2025 +0200
|
||||
|
||||
MIPS: OCTEON: Add UBNT specific DTS pruning
|
||||
|
||||
This imports device specific DTS pruning from
|
||||
https://github.com/UI-Packages/kernel_e200/blob/master/arch/mips/cavium-octeon/octeon-platform.c#L1067
|
||||
|
||||
- Reduce MMC clock frequency on E200/E220 to make
|
||||
MMC communication reliable again. See linked issue.
|
||||
- Remove unused MMC node on E300.
|
||||
|
||||
Related: https://github.com/openwrt/openwrt/issues/13762
|
||||
|
||||
Signed-off-by: Jakob Haufe <sur5r@sur5r.net>
|
||||
|
||||
--- a/arch/mips/cavium-octeon/octeon-platform.c
|
||||
+++ b/arch/mips/cavium-octeon/octeon-platform.c
|
||||
@@ -1133,6 +1133,41 @@ end_led:
|
||||
}
|
||||
#endif
|
||||
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+int __init ubnt_prune_device_tree(void)
|
||||
+{
|
||||
+ /* MMC on UBNT */
|
||||
+ pr_info("UBNT board DTS pruning...\n");
|
||||
+ if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_UBNT_E300) {
|
||||
+ pr_info("UBNT E300 found, looking for mmc-slot@2\n");
|
||||
+ // Remove unused MMC slot definition
|
||||
+ int mmc_slot2 = fdt_path_offset(initial_boot_params, "/soc/mmc/mmc-slot@2");
|
||||
+
|
||||
+ if (mmc_slot2 > 0) {
|
||||
+ pr_info("UBNT E300 found, deleting mmc-slot@2\n");
|
||||
+ fdt_nop_node(initial_boot_params, mmc_slot2);
|
||||
+ } else {
|
||||
+ pr_info("mmc-slot@2 not found\n");
|
||||
+ }
|
||||
+ } else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_UBNT_E200 ||
|
||||
+ octeon_bootinfo->board_type == CVMX_BOARD_TYPE_UBNT_E220) {
|
||||
+ pr_info("UBNT E200/E220 found, looking for mmc-slot@0\n");
|
||||
+ int mmc_slot0 = fdt_path_offset(initial_boot_params, "/soc/mmc/mmc-slot@0");
|
||||
+
|
||||
+ u32 freq = 26000000;
|
||||
+
|
||||
+ if (mmc_slot0 > 0) {
|
||||
+ pr_info("UBNT E200/E220 mmc-slot@0 found, setting frequency to 26MHz");
|
||||
+ fdt_setprop_inplace_cell(initial_boot_params, mmc_slot0,
|
||||
+ "spi-max-frequency", freq);
|
||||
+ } else {
|
||||
+ pr_info("mmc-slot@0 not found\n");
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
--- a/arch/mips/cavium-octeon/setup.c
|
||||
+++ b/arch/mips/cavium-octeon/setup.c
|
||||
@@ -1168,6 +1168,7 @@ void __init prom_free_prom_memory(void)
|
||||
}
|
||||
}
|
||||
|
||||
+int __init ubnt_prune_device_tree(void);
|
||||
void __init octeon_fill_mac_addresses(void);
|
||||
|
||||
void __init device_tree_init(void)
|
||||
@@ -1207,6 +1208,9 @@ void __init device_tree_init(void)
|
||||
octeon_prune_device_tree();
|
||||
pr_info("Using internal Device Tree.\n");
|
||||
}
|
||||
+
|
||||
+ ubnt_prune_device_tree();
|
||||
+
|
||||
if (fill_mac)
|
||||
octeon_fill_mac_addresses();
|
||||
unflatten_and_copy_device_tree();
|
||||
|
|
@ -1,37 +0,0 @@
|
|||
From: Roman Kuzmitskii <damex.pp@icloud.com>
|
||||
Date: Wed, 28 Oct 2020 19:00:00 +0000
|
||||
Subject: [PATCH] staging: octeon: add net-labels support
|
||||
|
||||
With this patch, device name can be set within dts file
|
||||
in the same way as dsa port can.
|
||||
|
||||
Add label to pip interface node to use this feature:
|
||||
label = "lan0";
|
||||
|
||||
Tested-by: Johannes Kimmel <fff@bareminimum.eu>
|
||||
Signed-off-by: Roman Kuzmitskii <damex.pp@icloud.com>
|
||||
--- a/drivers/staging/octeon/ethernet.c
|
||||
+++ b/drivers/staging/octeon/ethernet.c
|
||||
@@ -407,8 +407,12 @@ static int cvm_oct_common_set_mac_addres
|
||||
int cvm_oct_common_init(struct net_device *dev)
|
||||
{
|
||||
struct octeon_ethernet *priv = netdev_priv(dev);
|
||||
+ const u8 *label = NULL;
|
||||
int ret;
|
||||
|
||||
+ if (priv->of_node)
|
||||
+ label = of_get_property(priv->of_node, "label", NULL);
|
||||
+
|
||||
ret = of_get_ethdev_address(priv->of_node, dev);
|
||||
if (ret)
|
||||
eth_hw_addr_random(dev);
|
||||
@@ -441,6 +445,9 @@ int cvm_oct_common_init(struct net_devic
|
||||
if (dev->netdev_ops->ndo_stop)
|
||||
dev->netdev_ops->ndo_stop(dev);
|
||||
|
||||
+ if (!IS_ERR_OR_NULL(label))
|
||||
+ dev_alloc_name(dev, label);
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
From: Roman Kuzmitskii <damex.pp@icloud.com>
|
||||
Date: Sun, 01 Nov 2020 19:00:00 +0000
|
||||
Subject: [PATCH] staging: octeon: sgmii to honor disabled dt node status
|
||||
|
||||
With this patch, sgmii interface device tree node could be disabled and
|
||||
that disabled interface will not be unnecessarily initialized.
|
||||
|
||||
It solves the problem with Octeon boards that have 8 sgmii or more ports
|
||||
initialized but have nothing connected to them.
|
||||
|
||||
Tested-by: Johannes Kimmel <fff@bareminimum.eu>
|
||||
Signed-off-by: Roman Kuzmitskii <damex.pp@icloud.com>
|
||||
--- a/drivers/staging/octeon/ethernet.c
|
||||
+++ b/drivers/staging/octeon/ethernet.c
|
||||
@@ -877,8 +877,10 @@ static int cvm_oct_probe(struct platform
|
||||
|
||||
case CVMX_HELPER_INTERFACE_MODE_SGMII:
|
||||
priv->phy_mode = PHY_INTERFACE_MODE_SGMII;
|
||||
- dev->netdev_ops = &cvm_oct_sgmii_netdev_ops;
|
||||
- strscpy(dev->name, "eth%d", sizeof(dev->name));
|
||||
+ if (of_device_is_available(priv->of_node)) {
|
||||
+ dev->netdev_ops = &cvm_oct_sgmii_netdev_ops;
|
||||
+ strscpy(dev->name, "eth%d", sizeof(dev->name));
|
||||
+ }
|
||||
break;
|
||||
|
||||
case CVMX_HELPER_INTERFACE_MODE_SPI:
|
||||
|
|
@ -1,123 +0,0 @@
|
|||
From: Andrew LaMarche <andrewjlamarche@gmail.com>
|
||||
Date: Mon, 31 Mar 2025 13:00:00 +0000
|
||||
Subject: [PATCH] octeon: force pcs reset
|
||||
|
||||
QCA833x devices misbehave with SGMII until a PCS reset is triggered. U-boot has
|
||||
a newer vendor GPL dump that contains logic to reset the PCS. This patch
|
||||
backports that functionality so that Octeon devices with QCA833{4/7} switchs
|
||||
pass traffic between the switch and CPU.
|
||||
|
||||
References:
|
||||
- https://github.com/u-boot/u-boot/blob/master/arch/mips/mach-octeon/cvmx-helper-sgmii.c#L197-L225
|
||||
- https://github.com/u-boot/u-boot/blob/master/arch/mips/mach-octeon/cvmx-helper-sgmii.c#L701-L737
|
||||
|
||||
Signed-off-by: Andrew LaMarche <andrewjlamarche@gmail.com>
|
||||
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
|
||||
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
|
||||
@@ -125,6 +125,17 @@ static int __cvmx_helper_sgmii_hardware_
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static int __cvmx_helper_need_g15618(void)
|
||||
+{
|
||||
+ if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM ||
|
||||
+ OCTEON_IS_MODEL(OCTEON_CN63XX) ||
|
||||
+ OCTEON_IS_MODEL(OCTEON_CN66XX_PASS1_X) ||
|
||||
+ OCTEON_IS_MODEL(OCTEON_CN68XX))
|
||||
+ return 1;
|
||||
+ else
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
/**
|
||||
* Initialize the SERTES link for the first time or after a loss
|
||||
* of link.
|
||||
@@ -172,6 +183,39 @@ static int __cvmx_helper_sgmii_hardware_
|
||||
cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface),
|
||||
control_reg.u64);
|
||||
|
||||
+ /* Force a PCS reset by powering down the PCS interface
|
||||
+ * This is needed to deal with broken Qualcomm/Atheros PHYs and switches
|
||||
+ * which never recover if PCS is not power cycled. The alternative
|
||||
+ * is to power cycle or hardware reset the Qualcomm devices whenever
|
||||
+ * SGMII is initialized.
|
||||
+ *
|
||||
+ * This is needed for the QCA8033 PHYs as well as the QCA833X switches
|
||||
+ * to work. The QCA8337 switch has additional SGMII problems and is
|
||||
+ * best avoided if at all possible. Failure to power cycle PCS prevents
|
||||
+ * any traffic from flowing between Octeon and Qualcomm devices if there
|
||||
+ * is a warm reset. Even a software reset to the Qualcomm device will
|
||||
+ * not work.
|
||||
+ *
|
||||
+ * Note that this problem has been reported between Qualcomm and other
|
||||
+ * vendor's processors as well so this problem is not unique to
|
||||
+ * Qualcomm and Octeon.
|
||||
+ *
|
||||
+ * Power cycling PCS doesn't hurt anything with non-Qualcomm devices
|
||||
+ * other than adding a 25ms delay during initialization.
|
||||
+ */
|
||||
+ control_reg.s.pwr_dn = 1;
|
||||
+ cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface),
|
||||
+ control_reg.u64);
|
||||
+ cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
|
||||
+
|
||||
+ if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM)
|
||||
+ /* 25ms should be enough, 10ms is too short */
|
||||
+ mdelay(25);
|
||||
+
|
||||
+ control_reg.s.pwr_dn = 0;
|
||||
+ cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface),
|
||||
+ control_reg.u64);
|
||||
+
|
||||
/*
|
||||
* Wait for PCS*_MR*_STATUS_REG[AN_CPT] to be set, indicating
|
||||
* that sgmii autonegotiation is complete. In MAC mode this
|
||||
@@ -507,9 +551,47 @@ union cvmx_helper_link_info __cvmx_helpe
|
||||
int __cvmx_helper_sgmii_link_set(int ipd_port,
|
||||
union cvmx_helper_link_info link_info)
|
||||
{
|
||||
+ union cvmx_pcsx_mrx_control_reg control_reg;
|
||||
int interface = cvmx_helper_get_interface_num(ipd_port);
|
||||
int index = cvmx_helper_get_interface_index_num(ipd_port);
|
||||
- __cvmx_helper_sgmii_hardware_init_link(interface, index);
|
||||
+
|
||||
+ /* For some devices, i.e. the Qualcomm QCA8337 switch we need to power
|
||||
+ * down the PCS interface when the link goes down and power it back
|
||||
+ * up when the link returns.
|
||||
+ */
|
||||
+ if (link_info.s.link_up || !__cvmx_helper_need_g15618()) {
|
||||
+ __cvmx_helper_sgmii_hardware_init_link(interface, index);
|
||||
+ } else {
|
||||
+ union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg;
|
||||
+
|
||||
+ pcsx_miscx_ctl_reg.u64 = cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
|
||||
+
|
||||
+ /* Disable autonegotiation when MAC mode is enabled or
|
||||
+ * autonegotiation is disabled.
|
||||
+ */
|
||||
+ control_reg.u64 = cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
|
||||
+ if (pcsx_miscx_ctl_reg.s.mac_phy == 0 ||
|
||||
+ !cvmx_read_csr(CVMX_PCSX_ANX_RESULTS_REG(index, interface))) {
|
||||
+
|
||||
+ control_reg.s.an_en = 0;
|
||||
+ control_reg.s.spdmsb = 1;
|
||||
+ control_reg.s.spdlsb = 0;
|
||||
+ control_reg.s.dup = 1;
|
||||
+
|
||||
+ }
|
||||
+ cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface),
|
||||
+ control_reg.u64);
|
||||
+ cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface));
|
||||
+ /*
|
||||
+ * Use GMXENO to force the link down it will get
|
||||
+ * reenabled later...
|
||||
+ */
|
||||
+ pcsx_miscx_ctl_reg.s.gmxeno = 1;
|
||||
+ cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface),
|
||||
+ pcsx_miscx_ctl_reg.u64);
|
||||
+ cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface));
|
||||
+ return 0;
|
||||
+ }
|
||||
return __cvmx_helper_sgmii_hardware_init_link_speed(interface, index,
|
||||
link_info);
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue