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microchipsw: sync with DTS sent upstream
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Sync the DTS with the version sent upstream, clock bindings also.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
(cherry picked from commit bce8432bbd)
This commit is contained in:
Robert Marko 2025-12-23 14:08:26 +01:00
parent c3cf33f98b
commit a4a2638590
No known key found for this signature in database
GPG key ID: 66D805C09F36AFA5
3 changed files with 192 additions and 177 deletions
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110
target/linux/microchipsw/dts/lan969x.dtsi → target/linux/microchipsw/dts/lan9691.dtsi
View file

@ -3,7 +3,7 @@
* Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
*/
#include <dt-bindings/clock/microchip,lan969x.h>
#include <dt-bindings/clock/microchip,lan9691.h>
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mfd/at91-usart.h>
@ -14,14 +14,9 @@
#size-cells = <1>;
model = "Microchip LAN969x";
compatible = "microchip,lan969x";
compatible = "microchip,lan9691";
interrupt-parent = <&gic>;
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
clocks {
fx100_clk: fx100-clk {
compatible = "fixed-clock";
@ -66,6 +61,11 @@
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
@ -105,18 +105,17 @@
};
flx0: flexcom@e0040000 {
compatible = "atmel,sama5d2-flexcom";
compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom";
reg = <0xe0040000 0x100>;
ranges = <0x0 0xe0040000 0x800>;
clocks = <&clks GCK_ID_FLEXCOM0>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xe0040000 0x800>;
status = "disabled";
usart0: serial@200 {
compatible = "atmel,at91sam9260-usart";
compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
<&dma AT91_XDMAC_DT_PERID(2)>;
@ -124,11 +123,12 @@
clocks = <&fabric_clk>;
clock-names = "usart";
atmel,fifo-size = <32>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
status = "disabled";
};
spi0: spi@400 {
compatible = "atmel,at91rm9200-spi";
compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi";
reg = <0x400 0x200>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
@ -136,14 +136,14 @@
dma-names = "tx", "rx";
clocks = <&fabric_clk>;
clock-names = "spi_clk";
atmel,fifo-size = <32>;
#address-cells = <1>;
#size-cells = <0>;
atmel,fifo-size = <32>;
status = "disabled";
};
i2c0: i2c@600 {
compatible = "microchip,sam9x60-i2c";
compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
@ -157,18 +157,17 @@
};
flx1: flexcom@e0044000 {
compatible = "atmel,sama5d2-flexcom";
compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom";
reg = <0xe0044000 0x100>;
ranges = <0x0 0xe0044000 0x800>;
clocks = <&clks GCK_ID_FLEXCOM1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xe0044000 0x800>;
status = "disabled";
usart1: serial@200 {
compatible = "atmel,at91sam9260-usart";
compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
<&dma AT91_XDMAC_DT_PERID(2)>;
@ -176,11 +175,12 @@
clocks = <&fabric_clk>;
clock-names = "usart";
atmel,fifo-size = <32>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
status = "disabled";
};
spi1: spi@400 {
compatible = "atmel,at91rm9200-spi";
compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi";
reg = <0x400 0x200>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
@ -188,14 +188,14 @@
dma-names = "tx", "rx";
clocks = <&fabric_clk>;
clock-names = "spi_clk";
atmel,fifo-size = <32>;
#address-cells = <1>;
#size-cells = <0>;
atmel,fifo-size = <32>;
status = "disabled";
};
i2c1: i2c@600 {
compatible = "microchip,sam9x60-i2c";
compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma AT91_XDMAC_DT_PERID(3)>,
@ -209,14 +209,14 @@
};
trng: rng@e0048000 {
compatible = "atmel,at91sam9g45-trng";
compatible = "microchip,lan9691-trng", "atmel,at91sam9g45-trng";
reg = <0xe0048000 0x100>;
clocks = <&fabric_clk>;
status = "disabled";
};
aes: crypto@e004c000 {
compatible = "atmel,at91sam9g46-aes";
compatible = "microchip,lan9691-aes", "atmel,at91sam9g46-aes";
reg = <0xe004c000 0x100>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma AT91_XDMAC_DT_PERID(12)>,
@ -228,18 +228,17 @@
};
flx2: flexcom@e0060000 {
compatible = "atmel,sama5d2-flexcom";
compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom";
reg = <0xe0060000 0x100>;
ranges = <0x0 0xe0060000 0x800>;
clocks = <&clks GCK_ID_FLEXCOM2>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xe0060000 0x800>;
status = "disabled";
usart2: serial@200 {
compatible = "atmel,at91sam9260-usart";
compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma AT91_XDMAC_DT_PERID(7)>,
<&dma AT91_XDMAC_DT_PERID(6)>;
@ -247,11 +246,12 @@
clocks = <&fabric_clk>;
clock-names = "usart";
atmel,fifo-size = <32>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
status = "disabled";
};
spi2: spi@400 {
compatible = "atmel,at91rm9200-spi";
compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi";
reg = <0x400 0x200>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma AT91_XDMAC_DT_PERID(7)>,
@ -259,16 +259,19 @@
dma-names = "tx", "rx";
clocks = <&fabric_clk>;
clock-names = "spi_clk";
atmel,fifo-size = <32>;
#address-cells = <1>;
#size-cells = <0>;
atmel,fifo-size = <32>;
status = "disabled";
};
i2c2: i2c@600 {
compatible = "microchip,sam9x60-i2c";
compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma AT91_XDMAC_DT_PERID(7)>,
<&dma AT91_XDMAC_DT_PERID(6)>;
dma-names = "tx", "rx";
clocks = <&fabric_clk>;
#address-cells = <1>;
#size-cells = <0>;
@ -277,18 +280,17 @@
};
flx3: flexcom@e0064000 {
compatible = "atmel,sama5d2-flexcom";
compatible = "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom";
reg = <0xe0064000 0x100>;
ranges = <0x0 0xe0064000 0x800>;
clocks = <&clks GCK_ID_FLEXCOM3>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xe0064000 0x800>;
status = "disabled";
usart3: serial@200 {
compatible = "atmel,at91sam9260-usart";
compatible = "microchip,lan9691-usart", "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma AT91_XDMAC_DT_PERID(9)>,
<&dma AT91_XDMAC_DT_PERID(8)>;
@ -296,11 +298,12 @@
clocks = <&fabric_clk>;
clock-names = "usart";
atmel,fifo-size = <32>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
status = "disabled";
};
spi3: spi@400 {
compatible = "atmel,at91rm9200-spi";
compatible = "microchip,lan9691-spi", "atmel,at91rm9200-spi";
reg = <0x400 0x200>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma AT91_XDMAC_DT_PERID(9)>,
@ -308,14 +311,14 @@
dma-names = "tx", "rx";
clocks = <&fabric_clk>;
clock-names = "spi_clk";
atmel,fifo-size = <32>;
#address-cells = <1>;
#size-cells = <0>;
atmel,fifo-size = <32>;
status = "disabled";
};
i2c3: i2c@600 {
compatible = "microchip,sam9x60-i2c";
compatible = "microchip,lan9691-i2c", "microchip,sam9x60-i2c";
reg = <0x600 0x200>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma AT91_XDMAC_DT_PERID(9)>,
@ -329,7 +332,7 @@
};
dma: dma-controller@e0068000 {
compatible = "microchip,sama7g5-dma";
compatible = "microchip,lan9691-dma", "microchip,sama7g5-dma";
reg = <0xe0068000 0x1000>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <16>;
@ -339,7 +342,7 @@
};
sha: crypto@e006c000 {
compatible = "atmel,at91sam9g46-sha";
compatible = "microchip,lan9691-sha", "atmel,at91sam9g46-sha";
reg = <0xe006c000 0xec>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&dma AT91_XDMAC_DT_PERID(14)>;
@ -386,10 +389,10 @@
clks: clock-controller@e00c00b4 {
compatible = "microchip,lan9691-gck";
reg = <0xe00c00b4 0x30>, <0xe00c0308 0x4>;
#clock-cells = <1>;
clocks = <&cpu_clk>, <&ddr_clk>, <&fx100_clk>;
clock-names = "cpu", "ddr", "sys";
reg = <0xe00c00b4 0x30>, <0xe00c0308 0x4>;
};
qspi0: spi@e0804000 {
@ -445,7 +448,8 @@
};
reset: reset-controller@e201000c {
compatible = "microchip,lan9691-switch-reset", "microchip,lan966x-switch-reset";
compatible = "microchip,lan9691-switch-reset",
"microchip,lan966x-switch-reset";
reg = <0xe201000c 0x4>;
reg-names = "gcb";
#reset-cells = <1>;
@ -465,25 +469,25 @@
};
mdio0: mdio@e20101a8 {
compatible = "mscc,ocelot-miim";
compatible = "microchip,lan9691-miim", "mscc,ocelot-miim";
reg = <0xe20101a8 0x24>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0xe20101a8 0x24>;
clocks = <&fx100_clk>;
status = "disabled";
};
mdio1: mdio@e20101cc {
compatible = "mscc,ocelot-miim";
compatible = "microchip,lan9691-miim", "mscc,ocelot-miim";
reg = <0xe20101cc 0x24>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0xe20101cc 0x24>;
clocks = <&fx100_clk>;
status = "disabled";
};
sgpio: gpio@e2010230 {
compatible = "microchip,sparx5-sgpio";
compatible = "microchip,lan9691-sgpio", "microchip,sparx5-sgpio";
reg = <0xe2010230 0x118>;
clocks = <&fx100_clk>;
resets = <&reset 0>;
@ -493,7 +497,8 @@
status = "disabled";
sgpio_in: gpio@0 {
compatible = "microchip,sparx5-sgpio-bank";
compatible = "microchip,lan9691-sgpio-bank",
"microchip,sparx5-sgpio-bank";
reg = <0>;
gpio-controller;
#gpio-cells = <3>;
@ -503,7 +508,8 @@
};
sgpio_out: gpio@1 {
compatible = "microchip,sparx5-sgpio-bank";
compatible = "microchip,lan9691-sgpio-bank",
"microchip,sparx5-sgpio-bank";
reg = <1>;
gpio-controller;
#gpio-cells = <3>;
@ -511,7 +517,7 @@
};
tmon: hwmon@e2020100 {
compatible = "microchip,sparx5-temp";
compatible = "microchip,lan9691-temp", "microchip,sparx5-temp";
reg = <0xe2020100 0xc>;
clocks = <&fx100_clk>;
#thermal-sensor-cells = <0>;
@ -519,19 +525,19 @@
serdes: serdes@e3410000 {
compatible = "microchip,lan9691-serdes";
reg = <0xe3410000 0x150000>;
#phy-cells = <1>;
clocks = <&fabric_clk>;
reg = <0xe3410000 0x150000>;
};
gic: interrupt-controller@e8c11000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0xe8c11000 0x1000>, /* Distributor GICD_ */
<0xe8c12000 0x2000>, /* CPU interface GICC_ */
<0xe8c14000 0x2000>, /* Virt interface control */
<0xe8c16000 0x2000>; /* Virt CPU interface */
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
};

247
target/linux/microchipsw/dts/lan9696-ev23x71a.dts
View file

@ -1,19 +1,20 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include "lan969x.dtsi"
#include "lan9691.dtsi"
/ {
model = "Microchip EV23X71A";
compatible = "microchip,ev23x71a", "microchip,lan969x";
compatible = "microchip,ev23x71a", "microchip,lan9696", "microchip,lan9691";
aliases {
serial0 = &usart0;
led-boot = &led_status;
led-failsafe = &led_status;
led-running = &led_status;
led-upgrade = &led_status;
};
chosen {
@ -32,11 +33,11 @@
#address-cells = <1>;
#size-cells = <0>;
i2c-parent = <&i2c3>;
mux-gpios = <&sgpio_out 0 1 GPIO_ACTIVE_HIGH
&sgpio_out 0 2 GPIO_ACTIVE_HIGH
&sgpio_out 0 3 GPIO_ACTIVE_HIGH>;
idle-state = <0x8>;
mux-gpios = <&sgpio_out 0 1 GPIO_ACTIVE_HIGH>,
<&sgpio_out 0 2 GPIO_ACTIVE_HIGH>,
<&sgpio_out 0 3 GPIO_ACTIVE_HIGH>;
settle-time-us = <100>;
i2c_sfp0: i2c@0 {
reg = <0x0>;
@ -62,7 +63,7 @@
leds {
compatible = "gpio-leds";
led_status: led-status {
led-status {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
gpios = <&gpio 61 GPIO_ACTIVE_LOW>;
@ -136,7 +137,6 @@
mux-controller {
compatible = "gpio-mux";
#mux-control-cells = <0>;
mux-gpios = <&sgpio_out 1 2 GPIO_ACTIVE_LOW>,
<&sgpio_out 1 3 GPIO_ACTIVE_LOW>;
};
@ -178,44 +178,6 @@
};
};
&flx0 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
status = "okay";
};
&usart0 {
pinctrl-0 = <&fc0_pins>;
pinctrl-names = "default";
status = "okay";
};
&flx2 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
status = "okay";
};
&spi2 {
pinctrl-0 = <&fc2_pins>;
pinctrl-names = "default";
cs-gpios = <&gpio 63 GPIO_ACTIVE_LOW>;
status = "okay";
};
&flx3 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
status = "okay";
};
&i2c3 {
pinctrl-0 = <&fc3_pins>;
pinctrl-names = "default";
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
i2c-sda-hold-time-ns = <1500>;
status = "okay";
};
&gpio {
emmc_sd_pins: emmc-sd-pins {
/* eMMC_SD - CMD, CLK, D0, D1, D2, D3, D4, D5, D6, D7, RSTN */
@ -263,8 +225,8 @@
usb_ulpi_pins: usb-ulpi-pins {
pins = "GPIO_30", "GPIO_31", "GPIO_32", "GPIO_33",
"GPIO_34", "GPIO_35", "GPIO_36", "GPIO_37",
"GPIO_38", "GPIO_39", "GPIO_40", "GPIO_41";
"GPIO_34", "GPIO_35", "GPIO_36", "GPIO_37",
"GPIO_38", "GPIO_39", "GPIO_40", "GPIO_41";
function = "usb_ulpi";
};
@ -294,36 +256,29 @@
};
};
&qspi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <100000000>;
#address-cells = <1>;
#size-cells = <1>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
m25p,fast-read;
};
};
&sdmmc0 {
pinctrl-0 = <&emmc_sd_pins>;
pinctrl-names = "default";
max-frequency = <100000000>;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
non-removable;
disable-wp;
&flx0 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
status = "okay";
};
&tmon {
pinctrl-0 = <&fan_pins>;
&flx2 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;
status = "okay";
};
&flx3 {
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
status = "okay";
};
&i2c3 {
pinctrl-0 = <&fc3_pins>;
pinctrl-names = "default";
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
i2c-sda-hold-time-ns = <1500>;
status = "okay";
};
&mdio0 {
@ -508,6 +463,43 @@
};
};
&otp {
nvmem-layout {
compatible = "microchip,otp-layout";
base_mac_address: base-mac-address {
#nvmem-cell-cells = <1>;
};
};
};
&qspi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <100000000>;
#address-cells = <1>;
#size-cells = <1>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
m25p,fast-read;
};
};
&sdmmc0 {
pinctrl-0 = <&emmc_sd_pins>;
pinctrl-names = "default";
max-frequency = <100000000>;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
non-removable;
disable-wp;
status = "okay";
};
&serdes {
status = "okay";
};
@ -515,7 +507,6 @@
&sgpio {
pinctrl-0 = <&sgpio_pins>;
pinctrl-names = "default";
microchip,sgpio-port-ranges = <0 1>, <6 9>;
status = "okay";
@ -527,261 +518,279 @@
};
};
&spi2 {
pinctrl-0 = <&fc2_pins>;
pinctrl-names = "default";
cs-gpios = <&gpio 63 GPIO_ACTIVE_LOW>;
status = "okay";
};
&switch {
pinctrl-0 = <&ptp_out_pins>, <&ptp_ext_pins>;
pinctrl-names = "default";
nvmem-cells = <&base_mac_address 0>;
nvmem-cell-names = "mac-address";
status = "okay";
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port0: port@0 {
reg = <0>;
microchip,bandwidth = <1000>;
phy-handle = <&phy4>;
phy-mode = "qsgmii";
phys = <&serdes 0>;
microchip,bandwidth = <1000>;
};
port1: port@1 {
reg = <1>;
microchip,bandwidth = <1000>;
phy-handle = <&phy5>;
phy-mode = "qsgmii";
phys = <&serdes 0>;
microchip,bandwidth = <1000>;
};
port2: port@2 {
reg = <2>;
microchip,bandwidth = <1000>;
phy-handle = <&phy6>;
phy-mode = "qsgmii";
phys = <&serdes 0>;
microchip,bandwidth = <1000>;
};
port3: port@3 {
reg = <3>;
microchip,bandwidth = <1000>;
phy-handle = <&phy7>;
phy-mode = "qsgmii";
phys = <&serdes 0>;
microchip,bandwidth = <1000>;
};
port4: port@4 {
reg = <4>;
microchip,bandwidth = <1000>;
phy-handle = <&phy8>;
phy-mode = "qsgmii";
phys = <&serdes 1>;
microchip,bandwidth = <1000>;
};
port5: port@5 {
reg = <5>;
microchip,bandwidth = <1000>;
phy-handle = <&phy9>;
phy-mode = "qsgmii";
phys = <&serdes 1>;
microchip,bandwidth = <1000>;
};
port6: port@6 {
reg = <6>;
microchip,bandwidth = <1000>;
phy-handle = <&phy10>;
phy-mode = "qsgmii";
phys = <&serdes 1>;
microchip,bandwidth = <1000>;
};
port7: port@7 {
reg = <7>;
microchip,bandwidth = <1000>;
phy-handle = <&phy11>;
phy-mode = "qsgmii";
phys = <&serdes 1>;
microchip,bandwidth = <1000>;
};
port8: port@8 {
reg = <8>;
microchip,bandwidth = <1000>;
phy-handle = <&phy12>;
phy-mode = "qsgmii";
phys = <&serdes 2>;
microchip,bandwidth = <1000>;
};
port9: port@9 {
reg = <9>;
microchip,bandwidth = <1000>;
phy-handle = <&phy13>;
phy-mode = "qsgmii";
phys = <&serdes 2>;
microchip,bandwidth = <1000>;
};
port10: port@10 {
reg = <10>;
microchip,bandwidth = <1000>;
phy-handle = <&phy14>;
phy-mode = "qsgmii";
phys = <&serdes 2>;
microchip,bandwidth = <1000>;
};
port11: port@11 {
reg = <11>;
microchip,bandwidth = <1000>;
phy-handle = <&phy15>;
phy-mode = "qsgmii";
phys = <&serdes 2>;
microchip,bandwidth = <1000>;
};
port12: port@12 {
reg = <12>;
microchip,bandwidth = <1000>;
phy-handle = <&phy16>;
phy-mode = "qsgmii";
phys = <&serdes 3>;
microchip,bandwidth = <1000>;
};
port13: port@13 {
reg = <13>;
microchip,bandwidth = <1000>;
phy-handle = <&phy17>;
phy-mode = "qsgmii";
phys = <&serdes 3>;
microchip,bandwidth = <1000>;
};
port14: port@14 {
reg = <14>;
microchip,bandwidth = <1000>;
phy-handle = <&phy18>;
phy-mode = "qsgmii";
phys = <&serdes 3>;
microchip,bandwidth = <1000>;
};
port15: port@15 {
reg = <15>;
microchip,bandwidth = <1000>;
phy-handle = <&phy19>;
phy-mode = "qsgmii";
phys = <&serdes 3>;
microchip,bandwidth = <1000>;
};
port16: port@16 {
reg = <16>;
microchip,bandwidth = <1000>;
phy-handle = <&phy20>;
phy-mode = "qsgmii";
phys = <&serdes 4>;
microchip,bandwidth = <1000>;
};
port17: port@17 {
reg = <17>;
microchip,bandwidth = <1000>;
phy-handle = <&phy21>;
phy-mode = "qsgmii";
phys = <&serdes 4>;
microchip,bandwidth = <1000>;
};
port18: port@18 {
reg = <18>;
microchip,bandwidth = <1000>;
phy-handle = <&phy22>;
phy-mode = "qsgmii";
phys = <&serdes 4>;
microchip,bandwidth = <1000>;
};
port19: port@19 {
reg = <19>;
microchip,bandwidth = <1000>;
phy-handle = <&phy23>;
phy-mode = "qsgmii";
phys = <&serdes 4>;
microchip,bandwidth = <1000>;
};
port20: port@20 {
reg = <20>;
microchip,bandwidth = <1000>;
phy-handle = <&phy24>;
phy-mode = "qsgmii";
phys = <&serdes 5>;
microchip,bandwidth = <1000>;
};
port21: port@21 {
reg = <21>;
microchip,bandwidth = <1000>;
phy-handle = <&phy25>;
phy-mode = "qsgmii";
phys = <&serdes 5>;
microchip,bandwidth = <1000>;
};
port22: port@22 {
reg = <22>;
microchip,bandwidth = <1000>;
phy-handle = <&phy26>;
phy-mode = "qsgmii";
phys = <&serdes 5>;
microchip,bandwidth = <1000>;
};
port23: port@23 {
reg = <23>;
microchip,bandwidth = <1000>;
phy-handle = <&phy27>;
phy-mode = "qsgmii";
phys = <&serdes 5>;
microchip,bandwidth = <1000>;
};
port24: port@24 {
reg = <24>;
microchip,bandwidth = <10000>;
phys = <&serdes 6>;
phy-mode = "10gbase-r";
sfp = <&sfp0>;
microchip,sd-sgpio = <24>;
managed = "in-band-status";
microchip,bandwidth = <10000>;
microchip,sd-sgpio = <24>;
};
port25: port@25 {
reg = <25>;
microchip,bandwidth = <10000>;
phys = <&serdes 7>;
phy-mode = "10gbase-r";
sfp = <&sfp1>;
microchip,sd-sgpio = <28>;
managed = "in-band-status";
microchip,bandwidth = <10000>;
microchip,sd-sgpio = <28>;
};
port26: port@26 {
reg = <26>;
microchip,bandwidth = <10000>;
phys = <&serdes 8>;
phy-mode = "10gbase-r";
sfp = <&sfp2>;
microchip,sd-sgpio = <32>;
managed = "in-band-status";
microchip,bandwidth = <10000>;
microchip,sd-sgpio = <32>;
};
port27: port@27 {
reg = <27>;
microchip,bandwidth = <10000>;
phys = <&serdes 9>;
phy-mode = "10gbase-r";
sfp = <&sfp3>;
microchip,sd-sgpio = <36>;
managed = "in-band-status";
microchip,bandwidth = <10000>;
microchip,sd-sgpio = <36>;
};
port29: port@29 {
reg = <29>;
microchip,bandwidth = <1000>;
phys = <&serdes 11>;
phy-handle = <&phy3>;
phy-mode = "rgmii";
rx-internal-delay-ps = <1000>;
tx-internal-delay-ps = <1000>;
phy-mode = "rgmii-id";
microchip,bandwidth = <1000>;
};
};
};
&usb {
status = "okay";
pinctrl-0 = <&usb_ulpi_pins>, <&usb_rst_pins>, <&usb_over_pins>, <&usb_power_pins>;
&tmon {
pinctrl-0 = <&fan_pins>;
pinctrl-names = "default";
};
&usart0 {
pinctrl-0 = <&fc0_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb {
pinctrl-0 = <&usb_ulpi_pins>, <&usb_rst_pins>, <&usb_over_pins>, <&usb_power_pins>;
pinctrl-names = "default";
status = "okay";
};

12
target/linux/microchipsw/patches-6.12/103-include-dt-bindings-add-LAN969x-clock-bindings.patch
View file

@ -1,4 +1,4 @@
From 7dffd83ae4ae02a43d61b15af6edb199fcc7ebb3 Mon Sep 17 00:00:00 2001
From 334fd8a6295e82c16b3120d29213ca02947d3ebb Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Tue, 5 Nov 2024 12:08:06 +0100
Subject: [PATCH] include: dt-bindings: add LAN969x clock bindings
@ -7,17 +7,17 @@ Add the required LAN969x clock bindings.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
include/dt-bindings/clock/microchip,lan969x.h | 24 +++++++++++++++++++
include/dt-bindings/clock/microchip,lan9691.h | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
create mode 100644 include/dt-bindings/clock/microchip,lan969x.h
create mode 100644 include/dt-bindings/clock/microchip,lan9691.h
--- /dev/null
+++ b/include/dt-bindings/clock/microchip,lan969x.h
+++ b/include/dt-bindings/clock/microchip,lan9691.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_CLK_LAN969X_H
+#define _DT_BINDINGS_CLK_LAN969X_H
+#ifndef _DT_BINDINGS_CLK_LAN9691_H
+#define _DT_BINDINGS_CLK_LAN9691_H
+
+#define GCK_ID_QSPI0 0
+#define GCK_ID_QSPI2 1