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realtek: mdio: RTL838x: create new SerDes phy register layout
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When a SerDes directly drives a SFP module there is no clear rule of
how to handle its register set that consists of two parts:
- c22 phy registers 0-15 live in the fiber page (2) of the SerDes
- other SerDes specific registers exist in pages before and after
The mdio bus and other SerDes functions are a wild mix of directly
looking into page 2 or just using self defined methods to access
data.
Provide a consistent phy interface that mixes the SerDes register
set like classic Realtek phys do it.
- Use register 31 as page select (already in the bus)
- Always keep the common registers 0-15 in place and read fiber page
- Map the SerDes internal registers into the upper vendor specific
registers 16-23 according to the page select register (31).
That gives a register mapping as follows:
+-----------------------+-----------------------+---------------+-------------+
| reg 0x00-0x0f | reg 0x10-0x17 | reg 0x18-0x1e | reg 0x1f |
+-----------------------+-----------------------+---------------+-------------+
| SerDes fiber page (3) | real SerDes registers | zero | SerDes page |
| registers 0 - 15 | in packages of 8 | | select reg |
+-----------------------+-----------------------+---------------+-------------+
Example to make it as clear as possible.
SerDes registers on a RTL838x show
Page / Reg | 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B ...
-------------+----------------------------------------------------------------
0 - SDS | 0C03 0F00 7060 7106 074D 0EBF 0F0F 0359 5248 0000 0F80 0000 ...
1 - SDS_EXT | 0000 0000 85FA 8C6D 5CCC 0000 20D8 0003 79AA 8C64 00C3 1482 ...
2 - FIB | 1140 6189 001C CA40 01A0 0000 0000 0004 0000 0000 0000 0000 ...
3 - FIB_EXT | 1140 6109 001C CA40 01A0 0000 0000 0004 0000 0000 0000 0000 ...
This translates to this phy layout
| SerDes fiber registers normal SerDes registers zero p.sel
Page / Reg | 0x00 0x01 0x02 0x03 ... 0x10 0x11 0x12 0x13 ... 0x18 ... 0x1f
-------------+---------------------------------------------------------------
0 | 1140 6189 001C CA40 ... 0C03 0F00 7060 7106 ... 0000 ... 0000
1 | 1140 6189 001C CA40 ... 5248 0000 0F80 0000 ... 0000 ... 0001
...
4 | 1140 6189 001C CA40 ... 0000 0000 85FA 8C6D ... 0000 ... 0004
For now just do it for RTL838x devices.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/19604
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Markus Stockhausen
Robert Marko
parent
3544a06766
commit
9dddc0bed0
1 changed files with 107 additions and 20 deletions
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@ -83,6 +83,8 @@ extern int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v);
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#define RTMDIO_ABS BIT(2)
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#define RTMDIO_PKG BIT(3)
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#define RTMDIO_838X_BASE (0xe780)
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struct p_hdr {
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uint8_t *buf;
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uint16_t reserved;
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@ -1647,7 +1649,7 @@ struct rtmdio_bus_priv {
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bool raw[RTMDIO_MAX_PORT];
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int smi_bus[RTMDIO_MAX_PORT];
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u8 smi_addr[RTMDIO_MAX_PORT];
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u32 sds_id[RTMDIO_MAX_PORT];
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int sds_id[RTMDIO_MAX_PORT];
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bool smi_bus_isc45[RTMDIO_MAX_SMI_BUS];
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bool phy_is_internal[RTMDIO_MAX_PORT];
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phy_interface_t interfaces[RTMDIO_MAX_PORT];
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@ -1655,6 +1657,8 @@ struct rtmdio_bus_priv {
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int (*write_mmd_phy)(u32 port, u32 addr, u32 reg, u32 val);
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int (*read_phy)(u32 port, u32 page, u32 reg, u32 *val);
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int (*write_phy)(u32 port, u32 page, u32 reg, u32 val);
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int (*read_sds_phy)(int sds, int page, int regnum);
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int (*write_sds_phy)(int sds, int page, int regnum, u16 val);
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};
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/*
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@ -1750,18 +1754,43 @@ int phy_port_read_paged(struct phy_device *phydev, int port, int page, u32 regnu
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/* SerDes reader/writer functions for the ports without external phy. */
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static int rtmdio_838x_read_sds(int addr, int regnum)
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{
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int offset = addr == 26 ? 0x100 : 0x0;
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/*
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* The RTL838x has 6 SerDes. The 16 bit registers start at 0xbb00e780 and are mapped directly into
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* 32 bit memory addresses. High 16 bits are always empty. A "lower" memory block serves pages 0/3
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* a "higher" memory block pages 1/2.
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*/
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return sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (regnum << 2)) & 0xffff;
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static int rtmdio_838x_reg_offset(int sds, int page, int regnum)
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{
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if (sds < 0 || sds > 5)
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return -EINVAL;
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if (page == 0 || page == 3)
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return (sds << 9) + (page << 7) + (regnum << 2);
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else if (page == 1 || page == 2)
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return 0xb80 + (sds << 8) + (page << 7) + (regnum << 2);
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return -EINVAL;
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}
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static int rtmdio_838x_write_sds(int addr, int regnum, u16 val)
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static int rtmdio_838x_read_sds_phy(int sds, int page, int regnum)
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{
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int offset = addr == 26 ? 0x100 : 0x0;
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int offset = rtmdio_838x_reg_offset(sds, page, regnum);
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sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (regnum << 2));
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if (offset < 0)
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return offset;
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return sw_r32(RTMDIO_838X_BASE + offset) & GENMASK(15, 0);
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}
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static int rtmdio_838x_write_sds_phy(int sds, int page, int regnum, u16 val)
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{
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int offset = rtmdio_838x_reg_offset(sds, page, regnum);
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if (offset < 0)
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return offset;
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sw_w32(val, RTMDIO_838X_BASE + offset);
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return 0;
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}
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@ -1950,6 +1979,58 @@ static int rtmdio_read_c45(struct mii_bus *bus, int addr, int devnum, int regnum
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return err ? err : val;
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}
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static int rtmdio_map_sds_register(int page, int regnum, int *sds_page, int *sds_regnum)
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{
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/*
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* For the SerDes PHY simulate a register mapping like common RealTek PHYs do. Always
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* keep the common registers 0x00-0x0f in place and map the SerDes registers into the
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* upper vendor specific registers 0x10-0x17 according to the page select register
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* (0x1f). That gives a register mapping as follows:
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*
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* +-----------------------+-----------------------+---------------+-----------------+
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* | reg 0x00-0x0f | reg 0x10-0x17 | reg 0x18-0x1e | reg 0x1f |
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* +-----------------------+-----------------------+---------------+-----------------+
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* | SerDes fiber page (2) | real SerDes registers | zero | SerDes page |
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* | registers 0x00-0x0f | in packages of 8 | | select register |
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* +-----------------------+-----------------------+---------------+-----------------+
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*/
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if (regnum < 16) {
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*sds_page = 2;
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*sds_regnum = regnum;
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} else if (regnum < 24) {
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*sds_page = page / 4;
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*sds_regnum = 8 * (page % 4) + (regnum - 16);
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} else
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return 0;
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return 1;
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}
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static int rtmdio_read_sds_phy(struct rtmdio_bus_priv *priv, int sds, int page, int regnum)
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{
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int ret, sds_page, sds_regnum;
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ret = rtmdio_map_sds_register(page, regnum, &sds_page, &sds_regnum);
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if (ret)
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ret = priv->read_sds_phy(sds, sds_page, sds_regnum);
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pr_debug("rd_SDS(sds=%d, pag=%d, reg=%d) = %d\n", sds, page, regnum, ret);
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return ret;
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}
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static int rtmdio_write_sds_phy(struct rtmdio_bus_priv *priv, int sds, int page, int regnum, u16 val)
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{
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int ret, sds_page, sds_regnum;
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ret = rtmdio_map_sds_register(page, regnum, &sds_page, &sds_regnum);
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if (ret)
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ret = priv->write_sds_phy(sds, sds_page, sds_regnum, val);
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pr_debug("wr_SDS(sds=%d, pag=%d, reg=%d, val=%d) err = %d\n", sds, page, regnum, val, ret);
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return ret;
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}
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static int rtmdio_83xx_read(struct mii_bus *bus, int addr, int regnum)
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{
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struct rtmdio_bus_priv *priv = bus->priv;
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@ -1961,16 +2042,18 @@ static int rtmdio_83xx_read(struct mii_bus *bus, int addr, int regnum)
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if (addr >= priv->cpu_port)
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return -ENODEV;
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if (addr >= 24 && addr <= 27 && priv->id == 0x8380)
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return rtmdio_838x_read_sds(addr, regnum);
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if (priv->family_id == RTL8390_FAMILY_ID && priv->phy_is_internal[addr])
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return rtl839x_read_sds_phy(addr, regnum);
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if (regnum == RTMDIO_PAGE_SELECT && priv->page[addr] != priv->rawpage)
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return priv->page[addr];
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priv->raw[addr] = (priv->page[addr] == priv->rawpage);
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if ((priv->phy_is_internal[addr]) && (priv->sds_id[addr] >=0)) {
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if (priv->family_id == RTL8380_FAMILY_ID)
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return rtmdio_read_sds_phy(priv, priv->sds_id[addr],
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priv->page[addr], regnum);
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else
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return rtl839x_read_sds_phy(addr, regnum);
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}
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err = (*priv->read_phy)(addr, priv->page[addr], regnum, &val);
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pr_debug("rd_PHY(adr=%d, pag=%d, reg=%d) = %d, err = %d\n",
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addr, priv->page[addr], regnum, val, err);
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@ -2042,17 +2125,19 @@ static int rtmdio_83xx_write(struct mii_bus *bus, int addr, int regnum, u16 val)
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page = priv->page[addr];
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if (addr >= 24 && addr <= 27 && priv->id == 0x8380)
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return rtmdio_838x_write_sds(addr, regnum, val);
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if (priv->family_id == RTL8390_FAMILY_ID && priv->phy_is_internal[addr])
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return rtl839x_write_sds_phy(addr, regnum, val);
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if (regnum == RTMDIO_PAGE_SELECT)
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priv->page[addr] = val;
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if (!priv->raw[addr] && (regnum != RTMDIO_PAGE_SELECT || page == priv->rawpage)) {
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priv->raw[addr] = (page == priv->rawpage);
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if (priv->phy_is_internal[addr] && priv->sds_id[addr] >=0 ) {
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if (priv->family_id == RTL8380_FAMILY_ID)
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return rtmdio_write_sds_phy(priv, priv->sds_id[addr],
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priv->page[addr], regnum, val);
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else
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return rtl839x_write_sds_phy(addr, regnum, val);
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}
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err = (*priv->write_phy)(addr, page, regnum, val);
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pr_debug("wr_PHY(adr=%d, pag=%d, reg=%d, val=%d) err = %d\n",
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addr, page, regnum, val, err);
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@ -2377,6 +2462,8 @@ static int rtl838x_mdio_init(struct rtl838x_eth_priv *priv)
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priv->mii_bus->read = rtmdio_83xx_read;
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priv->mii_bus->write = rtmdio_83xx_write;
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priv->mii_bus->reset = rtmdio_838x_reset;
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bus_priv->read_sds_phy = rtmdio_838x_read_sds_phy;
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bus_priv->write_sds_phy = rtmdio_838x_write_sds_phy;
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bus_priv->read_mmd_phy = rtmdio_838x_read_mmd_phy;
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bus_priv->write_mmd_phy = rtmdio_838x_write_mmd_phy;
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bus_priv->read_phy = rtmdio_838x_read_phy;
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