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mediatek: add basic support for the MT7987 SoC
The MT7987 is mostly a stripped-down low-pin-count version of the MT7988 without the 10GBit/s SerDes. Most existing drivers can be reused. Import to-be-sent-upstream patches doing all the groundwork for basic support for the MT7987 SoC, adding clk, pinctrl and pwm support. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
This commit is contained in:
Daniel Golle
parent
6d35edad6e
commit
911a1145a5
8 changed files with 2087 additions and 0 deletions
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@ -72,6 +72,7 @@ CONFIG_COMMON_CLK_MT7981=y
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CONFIG_COMMON_CLK_MT7981_ETHSYS=y
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CONFIG_COMMON_CLK_MT7986=y
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CONFIG_COMMON_CLK_MT7986_ETHSYS=y
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CONFIG_COMMON_CLK_MT7987=y
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CONFIG_COMMON_CLK_MT7988=y
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# CONFIG_COMMON_CLK_MT8173 is not set
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# CONFIG_COMMON_CLK_MT8183 is not set
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@ -394,6 +395,7 @@ CONFIG_PINCTRL=y
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# CONFIG_PINCTRL_MT7622 is not set
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CONFIG_PINCTRL_MT7981=y
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CONFIG_PINCTRL_MT7986=y
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CONFIG_PINCTRL_MT7987=y
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CONFIG_PINCTRL_MT7988=y
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# CONFIG_PINCTRL_MT8173 is not set
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# CONFIG_PINCTRL_MT8183 is not set
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@ -80,6 +80,7 @@ CONFIG_COMMON_CLK_MT7622_ETHSYS=y
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CONFIG_COMMON_CLK_MT7622_HIFSYS=y
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# CONFIG_COMMON_CLK_MT7981 is not set
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# CONFIG_COMMON_CLK_MT7986 is not set
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# CONFIG_COMMON_CLK_MT7987 is not set
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# CONFIG_COMMON_CLK_MT7988 is not set
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# CONFIG_COMMON_CLK_MT8173 is not set
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# CONFIG_COMMON_CLK_MT8183 is not set
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@ -384,6 +385,7 @@ CONFIG_PINCTRL=y
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CONFIG_PINCTRL_MT7622=y
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# CONFIG_PINCTRL_MT7981 is not set
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# CONFIG_PINCTRL_MT7986 is not set
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# CONFIG_PINCTRL_MT7987 is not set
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# CONFIG_PINCTRL_MT7988 is not set
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# CONFIG_PINCTRL_MT8173 is not set
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# CONFIG_PINCTRL_MT8183 is not set
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@ -80,6 +80,7 @@ CONFIG_COMMON_CLK_MT2701_VDECSYS=y
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# CONFIG_COMMON_CLK_MT7629 is not set
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# CONFIG_COMMON_CLK_MT7981 is not set
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# CONFIG_COMMON_CLK_MT7986 is not set
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# CONFIG_COMMON_CLK_MT7987 is not set
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# CONFIG_COMMON_CLK_MT7988 is not set
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# CONFIG_COMMON_CLK_MT8135 is not set
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# CONFIG_COMMON_CLK_MT8365 is not set
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@ -58,6 +58,7 @@ CONFIG_COMMON_CLK_MT7629_ETHSYS=y
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CONFIG_COMMON_CLK_MT7629_HIFSYS=y
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# CONFIG_COMMON_CLK_MT7981 is not set
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# CONFIG_COMMON_CLK_MT7986 is not set
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# CONFIG_COMMON_CLK_MT7987 is not set
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# CONFIG_COMMON_CLK_MT7988 is not set
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# CONFIG_COMMON_CLK_MT8135 is not set
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# CONFIG_COMMON_CLK_MT8365 is not set
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@ -0,0 +1,793 @@
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From e37d53fb387eb788dff33cdc4c1009543e2ccd5f Mon Sep 17 00:00:00 2001
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From: Sam Shih <sam.shih@mediatek.com>
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Date: Mon, 20 Jan 2025 19:49:34 +0800
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Subject: [PATCH 1/2] pinctrl: mediatek: add mt7987 pinctrl support
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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drivers/pinctrl/mediatek/Kconfig | 6 +
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drivers/pinctrl/mediatek/Makefile | 1 +
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drivers/pinctrl/mediatek/pinctrl-mt7987.c | 752 ++++++++++++++++++++++
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3 files changed, 759 insertions(+)
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create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7987.c
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--- a/drivers/pinctrl/mediatek/Kconfig
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+++ b/drivers/pinctrl/mediatek/Kconfig
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@@ -187,6 +187,13 @@ config PINCTRL_MT7986
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default ARM64 && ARCH_MEDIATEK
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select PINCTRL_MTK_MOORE
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+config PINCTRL_MT7987
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+ bool "Mediatek MT7987 pin control"
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+ depends on OF
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+ depends on ARM64 || COMPILE_TEST
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+ default ARM64 && ARCH_MEDIATEK
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+ select PINCTRL_MTK_MOORE
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+
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config PINCTRL_MT7988
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bool "Mediatek MT7988 pin control"
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depends on OF
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--- a/drivers/pinctrl/mediatek/Makefile
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+++ b/drivers/pinctrl/mediatek/Makefile
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@@ -27,6 +27,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl
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obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
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obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o
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obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o
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+obj-$(CONFIG_PINCTRL_MT7987) += pinctrl-mt7987.o
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obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o
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obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
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obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
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--- /dev/null
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+++ b/drivers/pinctrl/mediatek/pinctrl-mt7987.c
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@@ -0,0 +1,751 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * The MT7987 driver based on Linux generic pinctrl binding.
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+ *
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+ * Copyright (C) 2020 MediaTek Inc.
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+ * Author: Tim.Kuo <Tim.Kuo@mediatek.com>
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+ */
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+
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+#include "pinctrl-moore.h"
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+
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+enum MT7987_PINCTRL_REG_PAGE {
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+ GPIO_BASE,
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+ IOCFG_RB_BASE,
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+ IOCFG_LB_BASE,
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+ IOCFG_RT1_BASE,
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+ IOCFG_RT2_BASE,
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+ IOCFG_TL_BASE,
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+};
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+
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+#define MT7987_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
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+
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+#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
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+ _x_bits) \
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+ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
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+ _x_bits, 32, 0)
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+
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+#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
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+ _x_bits) \
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+ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
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+ _x_bits, 32, 0)
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+
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+
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+#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
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+ _x_bits) \
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+ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \
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+ _x_bits, 32, 1)
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+
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+static const struct mtk_pin_field_calc mt7987_pin_mode_range[] = {
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+ PIN_FIELD(0, 49, 0x300, 0x10, 0, 4),
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+};
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+
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+static const struct mtk_pin_field_calc mt7987_pin_dir_range[] = {
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+ PIN_FIELD(0, 49, 0x0, 0x10, 0, 1),
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+};
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+
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+static const struct mtk_pin_field_calc mt7987_pin_di_range[] = {
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+ PIN_FIELD(0, 49, 0x200, 0x10, 0, 1),
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+};
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+
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+static const struct mtk_pin_field_calc mt7987_pin_do_range[] = {
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+ PIN_FIELD(0, 49, 0x100, 0x10, 0, 1),
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+};
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+
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+static const struct mtk_pin_field_calc mt7987_pin_ies_range[] = {
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+ PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x20, 0x10, 3, 1),
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+ PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x20, 0x10, 2, 1),
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+ PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x20, 0x10, 11, 1),
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+ PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x20, 0x10, 2, 1),
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+ PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x20, 0x10, 1, 1),
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+ PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x20, 0x10, 3, 1),
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+ PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x20, 0x10, 0, 1),
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+ PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x20, 0x10, 4, 1),
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+ PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x10, 0x10, 2, 1),
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+ PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x10, 0x10, 1, 1),
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+ PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x10, 0x10, 0, 1),
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+ PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x10, 0x10, 3, 1),
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+ PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x10, 0x10, 4, 1),
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+ PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x20, 0x10, 0, 1),
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+ PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x20, 0x10, 15, 1),
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+ PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x20, 0x10, 3, 1),
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+ PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x20, 0x10, 7, 1),
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+ PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x20, 0x10, 6, 1),
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+ PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x20, 0x10, 4, 1),
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+ PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x20, 0x10, 5, 1),
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+ PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x20, 0x10, 8, 1),
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+ PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x20, 0x10, 9, 1),
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+ PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x20, 0x10, 12, 1),
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+ PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x20, 0x10, 11, 1),
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+ PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x20, 0x10, 10, 1),
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+ PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x20, 0x10, 13, 1),
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+ PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x20, 0x10, 14, 1),
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+ PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x20, 0x10, 9, 1),
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+ PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x20, 0x10, 7, 1),
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+ PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x20, 0x10, 8, 1),
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+ PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x20, 0x10, 10, 1),
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+ PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x20, 0x10, 5, 1),
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+ PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x20, 0x10, 6, 1),
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+ PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x20, 0x10, 2, 1),
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+ PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x20, 0x10, 0, 1),
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+ PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x20, 0x10, 4, 1),
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+ PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x20, 0x10, 3, 1),
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+ PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x20, 0x10, 1, 1),
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+ PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x20, 0x10, 5, 1),
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+ PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x20, 0x10, 1, 1),
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+ PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x20, 0x10, 2, 1),
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+ PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x20, 0x10, 0, 1),
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+ PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x20, 0x10, 1, 1),
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+ PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x20, 0x10, 4, 1),
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+ PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x20, 0x10, 5, 1),
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+ PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x20, 0x10, 6, 1),
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+ PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x20, 0x10, 9, 1),
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+ PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x20, 0x10, 10, 1),
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+ PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x20, 0x10, 7, 1),
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+ PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x20, 0x10, 8, 1),
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+};
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+
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+static const struct mtk_pin_field_calc mt7987_pin_smt_range[] = {
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+ PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x90, 0x10, 3, 1),
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+ PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x90, 0x10, 2, 1),
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+ PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x90, 0x10, 11, 1),
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+ PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x90, 0x10, 2, 1),
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+ PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x90, 0x10, 1, 1),
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+ PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x90, 0x10, 3, 1),
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+ PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x90, 0x10, 0, 1),
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+ PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x90, 0x10, 4, 1),
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+ PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x70, 0x10, 2, 1),
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+ PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x70, 0x10, 1, 1),
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+ PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x70, 0x10, 0, 1),
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+ PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x70, 0x10, 3, 1),
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+ PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x70, 0x10, 4, 1),
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+ PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0xA0, 0x10, 0, 1),
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+ PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0xA0, 0x10, 15, 1),
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+ PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0xA0, 0x10, 3, 1),
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+ PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0xA0, 0x10, 7, 1),
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+ PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0xA0, 0x10, 6, 1),
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+ PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0xA0, 0x10, 4, 1),
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+ PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0xA0, 0x10, 5, 1),
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+ PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0xA0, 0x10, 8, 1),
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+ PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0xA0, 0x10, 9, 1),
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+ PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0xA0, 0x10, 12, 1),
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+ PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0xA0, 0x10, 11, 1),
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+ PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0xA0, 0x10, 10, 1),
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+ PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0xA0, 0x10, 13, 1),
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+ PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0xA0, 0x10, 14, 1),
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+ PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x90, 0x10, 9, 1),
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+ PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x90, 0x10, 7, 1),
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+ PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x90, 0x10, 8, 1),
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+ PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x90, 0x10, 10, 1),
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+ PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x90, 0x10, 5, 1),
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+ PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x90, 0x10, 6, 1),
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+ PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x60, 0x10, 2, 1),
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+ PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x60, 0x10, 0, 1),
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+ PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x60, 0x10, 4, 1),
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+ PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x60, 0x10, 3, 1),
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+ PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x60, 0x10, 1, 1),
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+ PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x60, 0x10, 5, 1),
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+ PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0xA0, 0x10, 1, 1),
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+ PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0xA0, 0x10, 2, 1),
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+ PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x90, 0x10, 0, 1),
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+ PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x90, 0x10, 1, 1),
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+ PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x90, 0x10, 4, 1),
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+ PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x90, 0x10, 5, 1),
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+ PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x90, 0x10, 6, 1),
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+ PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x90, 0x10, 9, 1),
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+ PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x90, 0x10, 10, 1),
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+ PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x90, 0x10, 7, 1),
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+ PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x90, 0x10, 8, 1),
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+};
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+
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+static const struct mtk_pin_field_calc mt7987_pin_pu_range[] = {
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+ PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x40, 0x10, 2, 1),
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+ PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x40, 0x10, 0, 1),
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+ PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x40, 0x10, 4, 1),
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+ PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x40, 0x10, 3, 1),
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+ PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x40, 0x10, 1, 1),
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+ PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x40, 0x10, 5, 1),
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+};
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+
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+static const struct mtk_pin_field_calc mt7987_pin_pd_range[] = {
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+ PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x30, 0x10, 2, 1),
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+ PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x30, 0x10, 0, 1),
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+ PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x30, 0x10, 4, 1),
|
||||
+ PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x30, 0x10, 3, 1),
|
||||
+ PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x30, 0x10, 1, 1),
|
||||
+ PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x30, 0x10, 5, 1),
|
||||
+};
|
||||
+
|
||||
+static const struct mtk_pin_field_calc mt7987_pin_drv_range[] = {
|
||||
+ PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x0, 0x10, 9, 3),
|
||||
+ PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x0, 0x10, 6, 3),
|
||||
+ PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x10, 0x10, 3, 3),
|
||||
+ PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x0, 0x10, 6, 3),
|
||||
+ PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x0, 0x10, 3, 3),
|
||||
+ PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x0, 0x10, 9, 3),
|
||||
+ PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x0, 0x10, 0, 3),
|
||||
+ PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x0, 0x10, 12, 3),
|
||||
+ PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x0, 0x10, 6, 3),
|
||||
+ PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x0, 0x10, 3, 3),
|
||||
+ PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x0, 0x10, 0, 3),
|
||||
+ PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x0, 0x10, 9, 3),
|
||||
+ PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x0, 0x10, 12, 3),
|
||||
+ PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x0, 0x10, 0, 3),
|
||||
+ PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x10, 0x10, 15, 3),
|
||||
+ PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x0, 0x10, 9, 3),
|
||||
+ PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x0, 0x10, 21, 3),
|
||||
+ PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x0, 0x10, 18, 3),
|
||||
+ PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x0, 0x10, 12, 3),
|
||||
+ PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x0, 0x10, 15, 3),
|
||||
+ PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x0, 0x10, 24, 3),
|
||||
+ PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x0, 0x10, 27, 3),
|
||||
+ PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x10, 0x10, 6, 3),
|
||||
+ PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x10, 0x10, 3, 3),
|
||||
+ PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x10, 0x10, 0, 3),
|
||||
+ PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x10, 0x10, 9, 3),
|
||||
+ PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x10, 0x10, 12, 3),
|
||||
+ PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x0, 0x10, 27, 3),
|
||||
+ PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x0, 0x10, 21, 3),
|
||||
+ PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x0, 0x10, 24, 3),
|
||||
+ PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x10, 0x10, 0, 3),
|
||||
+ PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x0, 0x10, 15, 3),
|
||||
+ PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x0, 0x10, 18, 3),
|
||||
+ PIN_FIELD_BASE(33, 33, IOCFG_LB_BASE, 0x0, 0x10, 6, 3),
|
||||
+ PIN_FIELD_BASE(34, 34, IOCFG_LB_BASE, 0x0, 0x10, 0, 3),
|
||||
+ PIN_FIELD_BASE(35, 35, IOCFG_LB_BASE, 0x0, 0x10, 12, 3),
|
||||
+ PIN_FIELD_BASE(36, 36, IOCFG_LB_BASE, 0x0, 0x10, 9, 3),
|
||||
+ PIN_FIELD_BASE(37, 37, IOCFG_LB_BASE, 0x0, 0x10, 3, 3),
|
||||
+ PIN_FIELD_BASE(38, 38, IOCFG_LB_BASE, 0x0, 0x10, 15, 3),
|
||||
+ PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x0, 0x10, 3, 3),
|
||||
+ PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x0, 0x10, 6, 3),
|
||||
+ PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x0, 0x10, 0, 3),
|
||||
+ PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x0, 0x10, 3, 3),
|
||||
+ PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x0, 0x10, 12, 3),
|
||||
+ PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x0, 0x10, 15, 3),
|
||||
+ PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x0, 0x10, 18, 3),
|
||||
+ PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x0, 0x10, 27, 3),
|
||||
+ PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x10, 0x10, 0, 3),
|
||||
+ PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x0, 0x10, 21, 3),
|
||||
+ PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x0, 0x10, 24, 3),
|
||||
+};
|
||||
+
|
||||
+static const struct mtk_pin_field_calc mt7987_pin_pupd_range[] = {
|
||||
+ PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x30, 0x10, 3, 1),
|
||||
+ PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x30, 0x10, 2, 1),
|
||||
+ PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x30, 0x10, 11, 1),
|
||||
+ PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x30, 0x10, 2, 1),
|
||||
+ PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x30, 0x10, 1, 1),
|
||||
+ PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x30, 0x10, 3, 1),
|
||||
+ PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x30, 0x10, 0, 1),
|
||||
+ PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x30, 0x10, 4, 1),
|
||||
+ PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x20, 0x10, 2, 1),
|
||||
+ PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x20, 0x10, 1, 1),
|
||||
+ PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x20, 0x10, 0, 1),
|
||||
+ PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x20, 0x10, 3, 1),
|
||||
+ PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x20, 0x10, 4, 1),
|
||||
+ PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x30, 0x10, 0, 1),
|
||||
+ PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x30, 0x10, 15, 1),
|
||||
+ PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x30, 0x10, 3, 1),
|
||||
+ PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x30, 0x10, 7, 1),
|
||||
+ PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x30, 0x10, 6, 1),
|
||||
+ PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x30, 0x10, 4, 1),
|
||||
+ PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x30, 0x10, 5, 1),
|
||||
+ PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x30, 0x10, 8, 1),
|
||||
+ PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x30, 0x10, 9, 1),
|
||||
+ PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x30, 0x10, 12, 1),
|
||||
+ PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x30, 0x10, 11, 1),
|
||||
+ PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x30, 0x10, 10, 1),
|
||||
+ PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x30, 0x10, 13, 1),
|
||||
+ PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x30, 0x10, 14, 1),
|
||||
+ PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x30, 0x10, 9, 1),
|
||||
+ PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x30, 0x10, 7, 1),
|
||||
+ PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x30, 0x10, 8, 1),
|
||||
+ PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x30, 0x10, 10, 1),
|
||||
+ PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x30, 0x10, 5, 1),
|
||||
+ PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x30, 0x10, 6, 1),
|
||||
+
|
||||
+ PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x30, 0x10, 1, 1),
|
||||
+ PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x30, 0x10, 2, 1),
|
||||
+ PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x30, 0x10, 0, 1),
|
||||
+ PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x30, 0x10, 1, 1),
|
||||
+ PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x30, 0x10, 4, 1),
|
||||
+ PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x30, 0x10, 5, 1),
|
||||
+ PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x30, 0x10, 6, 1),
|
||||
+ PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x30, 0x10, 9, 1),
|
||||
+ PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x30, 0x10, 10, 1),
|
||||
+ PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x30, 0x10, 7, 1),
|
||||
+ PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x30, 0x10, 8, 1),
|
||||
+};
|
||||
+
|
||||
+static const struct mtk_pin_field_calc mt7987_pin_r0_range[] = {
|
||||
+ PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x40, 0x10, 3, 1),
|
||||
+ PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x40, 0x10, 2, 1),
|
||||
+ PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x40, 0x10, 11, 1),
|
||||
+ PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x40, 0x10, 2, 1),
|
||||
+ PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x40, 0x10, 1, 1),
|
||||
+ PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x40, 0x10, 3, 1),
|
||||
+ PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x40, 0x10, 0, 1),
|
||||
+ PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x40, 0x10, 4, 1),
|
||||
+ PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x30, 0x10, 2, 1),
|
||||
+ PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x30, 0x10, 1, 1),
|
||||
+ PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x30, 0x10, 0, 1),
|
||||
+ PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x30, 0x10, 3, 1),
|
||||
+ PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x30, 0x10, 4, 1),
|
||||
+ PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x40, 0x10, 0, 1),
|
||||
+ PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x40, 0x10, 15, 1),
|
||||
+ PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x40, 0x10, 3, 1),
|
||||
+ PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x40, 0x10, 7, 1),
|
||||
+ PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x40, 0x10, 6, 1),
|
||||
+ PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x40, 0x10, 4, 1),
|
||||
+ PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x40, 0x10, 5, 1),
|
||||
+ PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x40, 0x10, 8, 1),
|
||||
+ PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x40, 0x10, 9, 1),
|
||||
+ PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x40, 0x10, 12, 1),
|
||||
+ PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x40, 0x10, 11, 1),
|
||||
+ PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x40, 0x10, 10, 1),
|
||||
+ PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x40, 0x10, 13, 1),
|
||||
+ PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x40, 0x10, 14, 1),
|
||||
+ PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x40, 0x10, 9, 1),
|
||||
+ PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x40, 0x10, 7, 1),
|
||||
+ PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x40, 0x10, 8, 1),
|
||||
+ PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x40, 0x10, 10, 1),
|
||||
+ PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x40, 0x10, 5, 1),
|
||||
+ PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x40, 0x10, 6, 1),
|
||||
+
|
||||
+ PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x40, 0x10, 1, 1),
|
||||
+ PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x40, 0x10, 2, 1),
|
||||
+ PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x40, 0x10, 0, 1),
|
||||
+ PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x40, 0x10, 1, 1),
|
||||
+ PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x40, 0x10, 4, 1),
|
||||
+ PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x40, 0x10, 5, 1),
|
||||
+ PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x40, 0x10, 6, 1),
|
||||
+ PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x40, 0x10, 9, 1),
|
||||
+ PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x40, 0x10, 10, 1),
|
||||
+ PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x40, 0x10, 7, 1),
|
||||
+ PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x40, 0x10, 8, 1),
|
||||
+};
|
||||
+
|
||||
+static const struct mtk_pin_field_calc mt7987_pin_r1_range[] = {
|
||||
+ PIN_FIELD_BASE(0, 0, IOCFG_RT2_BASE, 0x50, 0x10, 3, 1),
|
||||
+ PIN_FIELD_BASE(1, 1, IOCFG_RT2_BASE, 0x50, 0x10, 2, 1),
|
||||
+ PIN_FIELD_BASE(2, 2, IOCFG_RT2_BASE, 0x50, 0x10, 11, 1),
|
||||
+ PIN_FIELD_BASE(3, 3, IOCFG_TL_BASE, 0x50, 0x10, 2, 1),
|
||||
+ PIN_FIELD_BASE(4, 4, IOCFG_TL_BASE, 0x50, 0x10, 1, 1),
|
||||
+ PIN_FIELD_BASE(5, 5, IOCFG_TL_BASE, 0x50, 0x10, 3, 1),
|
||||
+ PIN_FIELD_BASE(6, 6, IOCFG_TL_BASE, 0x50, 0x10, 0, 1),
|
||||
+ PIN_FIELD_BASE(7, 7, IOCFG_TL_BASE, 0x50, 0x10, 4, 1),
|
||||
+ PIN_FIELD_BASE(8, 8, IOCFG_RB_BASE, 0x40, 0x10, 2, 1),
|
||||
+ PIN_FIELD_BASE(9, 9, IOCFG_RB_BASE, 0x40, 0x10, 1, 1),
|
||||
+ PIN_FIELD_BASE(10, 10, IOCFG_RB_BASE, 0x40, 0x10, 0, 1),
|
||||
+ PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x40, 0x10, 3, 1),
|
||||
+ PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x40, 0x10, 4, 1),
|
||||
+ PIN_FIELD_BASE(13, 13, IOCFG_RT1_BASE, 0x50, 0x10, 0, 1),
|
||||
+ PIN_FIELD_BASE(14, 14, IOCFG_RT1_BASE, 0x50, 0x10, 15, 1),
|
||||
+ PIN_FIELD_BASE(15, 15, IOCFG_RT1_BASE, 0x50, 0x10, 3, 1),
|
||||
+ PIN_FIELD_BASE(16, 16, IOCFG_RT1_BASE, 0x50, 0x10, 7, 1),
|
||||
+ PIN_FIELD_BASE(17, 17, IOCFG_RT1_BASE, 0x50, 0x10, 6, 1),
|
||||
+ PIN_FIELD_BASE(18, 18, IOCFG_RT1_BASE, 0x50, 0x10, 4, 1),
|
||||
+ PIN_FIELD_BASE(19, 19, IOCFG_RT1_BASE, 0x50, 0x10, 5, 1),
|
||||
+ PIN_FIELD_BASE(20, 20, IOCFG_RT1_BASE, 0x50, 0x10, 8, 1),
|
||||
+ PIN_FIELD_BASE(21, 21, IOCFG_RT1_BASE, 0x50, 0x10, 9, 1),
|
||||
+ PIN_FIELD_BASE(22, 22, IOCFG_RT1_BASE, 0x50, 0x10, 12, 1),
|
||||
+ PIN_FIELD_BASE(23, 23, IOCFG_RT1_BASE, 0x50, 0x10, 11, 1),
|
||||
+ PIN_FIELD_BASE(24, 24, IOCFG_RT1_BASE, 0x50, 0x10, 10, 1),
|
||||
+ PIN_FIELD_BASE(25, 25, IOCFG_RT1_BASE, 0x50, 0x10, 13, 1),
|
||||
+ PIN_FIELD_BASE(26, 26, IOCFG_RT1_BASE, 0x50, 0x10, 14, 1),
|
||||
+ PIN_FIELD_BASE(27, 27, IOCFG_RT2_BASE, 0x50, 0x10, 9, 1),
|
||||
+ PIN_FIELD_BASE(28, 28, IOCFG_RT2_BASE, 0x50, 0x10, 7, 1),
|
||||
+ PIN_FIELD_BASE(29, 29, IOCFG_RT2_BASE, 0x50, 0x10, 8, 1),
|
||||
+ PIN_FIELD_BASE(30, 30, IOCFG_RT2_BASE, 0x50, 0x10, 10, 1),
|
||||
+ PIN_FIELD_BASE(31, 31, IOCFG_TL_BASE, 0x50, 0x10, 5, 1),
|
||||
+ PIN_FIELD_BASE(32, 32, IOCFG_TL_BASE, 0x50, 0x10, 6, 1),
|
||||
+
|
||||
+ PIN_FIELD_BASE(39, 39, IOCFG_RT1_BASE, 0x50, 0x10, 1, 1),
|
||||
+ PIN_FIELD_BASE(40, 40, IOCFG_RT1_BASE, 0x50, 0x10, 2, 1),
|
||||
+ PIN_FIELD_BASE(41, 41, IOCFG_RT2_BASE, 0x50, 0x10, 0, 1),
|
||||
+ PIN_FIELD_BASE(42, 42, IOCFG_RT2_BASE, 0x50, 0x10, 1, 1),
|
||||
+ PIN_FIELD_BASE(43, 43, IOCFG_RT2_BASE, 0x50, 0x10, 4, 1),
|
||||
+ PIN_FIELD_BASE(44, 44, IOCFG_RT2_BASE, 0x50, 0x10, 5, 1),
|
||||
+ PIN_FIELD_BASE(45, 45, IOCFG_RT2_BASE, 0x50, 0x10, 6, 1),
|
||||
+ PIN_FIELD_BASE(46, 46, IOCFG_TL_BASE, 0x50, 0x10, 9, 1),
|
||||
+ PIN_FIELD_BASE(47, 47, IOCFG_TL_BASE, 0x50, 0x10, 10, 1),
|
||||
+ PIN_FIELD_BASE(48, 48, IOCFG_TL_BASE, 0x50, 0x10, 7, 1),
|
||||
+ PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x50, 0x10, 8, 1),
|
||||
+};
|
||||
+
|
||||
+static const unsigned int mt7987_pull_type[] = {
|
||||
+ MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/
|
||||
+ MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/
|
||||
+ MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/
|
||||
+ MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/
|
||||
+ MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/
|
||||
+ MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/
|
||||
+ MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/
|
||||
+ MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/
|
||||
+ MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/
|
||||
+ MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/
|
||||
+ MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/
|
||||
+ MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/
|
||||
+ MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/
|
||||
+ MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/
|
||||
+ MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/
|
||||
+ MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/
|
||||
+ MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PU_PD_TYPE,/*33*/
|
||||
+ MTK_PULL_PU_PD_TYPE,/*34*/ MTK_PULL_PU_PD_TYPE,/*35*/
|
||||
+ MTK_PULL_PU_PD_TYPE,/*36*/ MTK_PULL_PU_PD_TYPE,/*37*/
|
||||
+ MTK_PULL_PU_PD_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/
|
||||
+ MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/
|
||||
+ MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/
|
||||
+ MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/
|
||||
+ MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/
|
||||
+ MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/
|
||||
+};
|
||||
+
|
||||
+static const struct mtk_pin_reg_calc mt7987_reg_cals[] = {
|
||||
+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7987_pin_mode_range),
|
||||
+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7987_pin_dir_range),
|
||||
+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7987_pin_di_range),
|
||||
+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7987_pin_do_range),
|
||||
+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7987_pin_smt_range),
|
||||
+ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7987_pin_ies_range),
|
||||
+ [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7987_pin_pu_range),
|
||||
+ [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7987_pin_pd_range),
|
||||
+ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7987_pin_drv_range),
|
||||
+ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7987_pin_pupd_range),
|
||||
+ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7987_pin_r0_range),
|
||||
+ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7987_pin_r1_range),
|
||||
+};
|
||||
+
|
||||
+static const struct mtk_pin_desc mt7987_pins[] = {
|
||||
+ MT7987_PIN(0, "GPIO_WPS"),
|
||||
+ MT7987_PIN(1, "GPIO_RESET"),
|
||||
+ MT7987_PIN(2, "SYS_WATCHDOG"),
|
||||
+ MT7987_PIN(3, "JTAG_JTDO"),
|
||||
+ MT7987_PIN(4, "JTAG_JTDI"),
|
||||
+ MT7987_PIN(5, "JTAG_JTMS"),
|
||||
+ MT7987_PIN(6, "JTAG_JTCLK"),
|
||||
+ MT7987_PIN(7, "JTAG_JTRST_N"),
|
||||
+ MT7987_PIN(8, "PCM_DTX_I2S_DOUT"),
|
||||
+ MT7987_PIN(9, "PCM_DRX_I2S_DIN"),
|
||||
+ MT7987_PIN(10, "PCM_CLK_I2S_BCLK"),
|
||||
+ MT7987_PIN(11, "PCM_FS_I2S_LRCK"),
|
||||
+ MT7987_PIN(12, "PCM_MCK_I2S_MCLK"),
|
||||
+ MT7987_PIN(13, "PWM0"),
|
||||
+ MT7987_PIN(14, "USB_VBUS"),
|
||||
+ MT7987_PIN(15, "SPI0_CLK"),
|
||||
+ MT7987_PIN(16, "SPI0_MOSI"),
|
||||
+ MT7987_PIN(17, "SPI0_MISO"),
|
||||
+ MT7987_PIN(18, "SPI0_CS"),
|
||||
+ MT7987_PIN(19, "SPI0_HOLD"),
|
||||
+ MT7987_PIN(20, "SPI0_WP"),
|
||||
+ MT7987_PIN(21, "SPI1_CLK"),
|
||||
+ MT7987_PIN(22, "SPI1_MOSI"),
|
||||
+ MT7987_PIN(23, "SPI1_MISO"),
|
||||
+ MT7987_PIN(24, "SPI1_CS"),
|
||||
+ MT7987_PIN(25, "SPI2_CLK"),
|
||||
+ MT7987_PIN(26, "SPI2_MOSI"),
|
||||
+ MT7987_PIN(27, "SPI2_MISO"),
|
||||
+ MT7987_PIN(28, "SPI2_CS"),
|
||||
+ MT7987_PIN(29, "SPI2_HOLD"),
|
||||
+ MT7987_PIN(30, "SPI2_WP"),
|
||||
+ MT7987_PIN(31, "UART0_RXD"),
|
||||
+ MT7987_PIN(32, "UART0_TXD"),
|
||||
+ MT7987_PIN(33, "PCIE_PERESET_N_0"),
|
||||
+ MT7987_PIN(34, "PCIE_CLK_REQ_0"),
|
||||
+ MT7987_PIN(35, "PCIE_WAKE_N_0"),
|
||||
+ MT7987_PIN(36, "PCIE_PERESET_N_1"),
|
||||
+ MT7987_PIN(37, "PCIE_CLK_REQ_1"),
|
||||
+ MT7987_PIN(38, "PCIE_WAKE_N_1"),
|
||||
+ MT7987_PIN(39, "SMI_MDC"),
|
||||
+ MT7987_PIN(40, "SMI_MDIO"),
|
||||
+ MT7987_PIN(41, "GBE_INT"),
|
||||
+ MT7987_PIN(42, "GBE_RESET"),
|
||||
+ MT7987_PIN(43, "I2C_SCLK"),
|
||||
+ MT7987_PIN(44, "I2C_SDATA"),
|
||||
+ MT7987_PIN(45, "2P5G_LED0"),
|
||||
+ MT7987_PIN(46, "UART1_RXD"),
|
||||
+ MT7987_PIN(47, "UART1_TXD"),
|
||||
+ MT7987_PIN(48, "UART1_CTS"),
|
||||
+ MT7987_PIN(49, "UART1_RTS"),
|
||||
+};
|
||||
+
|
||||
+/* watchdog */
|
||||
+static int mt7987_watchdog_pins[] = {2};
|
||||
+static int mt7987_watchdog_funcs[] = {1};
|
||||
+
|
||||
+/* jtag */
|
||||
+static int mt7987_jtag_pins[] = {3, 4, 5, 6, 7};
|
||||
+static int mt7987_jtag_funcs[] = {1, 1, 1, 1, 1};
|
||||
+
|
||||
+/* i2s */
|
||||
+static int mt7987_i2s_pins[] = { 8, 9, 10, 11, 12 };
|
||||
+static int mt7987_i2s_funcs[] = { 1, 1, 1, 1, 1 };
|
||||
+
|
||||
+/* pcm */
|
||||
+static int mt7987_pcm_pins[] = { 8, 9, 10, 11 };
|
||||
+static int mt7987_pcm_funcs[] = { 1, 1, 1, 1 };
|
||||
+
|
||||
+/* uart */
|
||||
+static int mt7987_uart0_pins[] = {31, 32};
|
||||
+static int mt7987_uart0_funcs[] = {1, 1};
|
||||
+
|
||||
+static int mt7987_uart1_0_pins[] = {3, 4, 5, 6};
|
||||
+static int mt7987_uart1_0_funcs[] = {3, 3, 3, 3};
|
||||
+
|
||||
+static int mt7987_uart1_0_lite_pins[] = {3, 4};
|
||||
+static int mt7987_uart1_0_lite_funcs[] = {3, 3};
|
||||
+
|
||||
+static int mt7987_uart1_1_pins[] = {21, 22, 23, 24};
|
||||
+static int mt7987_uart1_1_funcs[] = {3, 3, 3, 3};
|
||||
+
|
||||
+static int mt7987_uart1_2_pins[] = {46, 47, 48, 49};
|
||||
+static int mt7987_uart1_2_funcs[] = {1, 1, 1, 1};
|
||||
+
|
||||
+static int mt7987_uart2_0_pins[] = {8, 9, 10, 11};
|
||||
+static int mt7987_uart2_0_funcs[] = {2, 2, 2, 2};
|
||||
+
|
||||
+static int mt7987_uart2_1_pins[] = {25, 26, 27, 28};
|
||||
+static int mt7987_uart2_1_funcs[] = {2, 2, 2, 2};
|
||||
+
|
||||
+/* pwm */
|
||||
+static int mt7987_pwm0_pins[] = {13};
|
||||
+static int mt7987_pwm0_funcs[] = {1};
|
||||
+
|
||||
+static int mt7987_pwm1_0_pins[] = {7};
|
||||
+static int mt7987_pwm1_0_funcs[] = {3};
|
||||
+
|
||||
+static int mt7987_pwm1_1_pins[] = {43};
|
||||
+static int mt7987_pwm1_1_funcs[] = {2};
|
||||
+
|
||||
+static int mt7987_pwm2_0_pins[] = {12};
|
||||
+static int mt7987_pwm2_0_funcs[] = {2};
|
||||
+
|
||||
+static int mt7987_pwm2_1_pins[] = {44};
|
||||
+static int mt7987_pwm2_1_funcs[] = {2};
|
||||
+
|
||||
+/* vbus */
|
||||
+static int mt7987_drv_vbus_p1_pins[] = {14};
|
||||
+static int mt7987_drv_vbus_p1_funcs[] = {1};
|
||||
+
|
||||
+static int mt7987_drv_vbus_pins[] = {48};
|
||||
+static int mt7987_drv_vbus_funcs[] = {3};
|
||||
+
|
||||
+/* 2p5gbe_led */
|
||||
+static int mt7987_2p5gbe_led0_pins[] = {45};
|
||||
+static int mt7987_2p5gbe_led0_funcs[] = {1};
|
||||
+
|
||||
+static int mt7987_2p5gbe_led1_0_pins[] = {13};
|
||||
+static int mt7987_2p5gbe_led1_0_funcs[] = {2};
|
||||
+
|
||||
+static int mt7987_2p5gbe_led1_1_pins[] = {49};
|
||||
+static int mt7987_2p5gbe_led1_1_funcs[] = {3};
|
||||
+
|
||||
+/* mdc, mdio */
|
||||
+static int mt7987_2p5g_ext_mdc_mdio_pins[] = {23, 24};
|
||||
+static int mt7987_2p5g_ext_mdc_mdio_funcs[] = {4, 4};
|
||||
+
|
||||
+static int mt7987_mdc_mdio_pins[] = {39, 40};
|
||||
+static int mt7987_mdc_mdio_funcs[] = {1, 1};
|
||||
+
|
||||
+/* spi */
|
||||
+static int mt7987_spi0_pins[] = {15, 16, 17, 18};
|
||||
+static int mt7987_spi0_funcs[] = {1, 1, 1, 1};
|
||||
+
|
||||
+static int mt7987_spi0_wp_hold_pins[] = {19, 20};
|
||||
+static int mt7987_spi0_wp_hold_funcs[] = {1, 1};
|
||||
+
|
||||
+static int mt7987_spi1_pins[] = {21, 22, 23, 24};
|
||||
+static int mt7987_spi1_funcs[] = {1, 1, 1, 1};
|
||||
+
|
||||
+static int mt7987_spi1_1_pins[] = {46, 47, 48, 49};
|
||||
+static int mt7987_spi1_1_funcs[] = {2, 2, 2, 2};
|
||||
+
|
||||
+static int mt7987_spi2_pins[] = {25, 26, 27, 28};
|
||||
+static int mt7987_spi2_funcs[] = {1, 1, 1, 1};
|
||||
+
|
||||
+static int mt7987_spi2_wp_hold_pins[] = {29, 30};
|
||||
+static int mt7987_spi2_wp_hold_funcs[] = {1, 1};
|
||||
+
|
||||
+/* emmc */
|
||||
+static int mt7987_emmc_45_pins[] = {14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24};
|
||||
+static int mt7987_emmc_45_funcs[] = {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2};
|
||||
+
|
||||
+/* sd */
|
||||
+static int mt7987_sd_pins[] = {15, 16, 17, 18, 23, 24};
|
||||
+static int mt7987_sd_funcs[] = {2, 2, 2, 2, 2, 2};
|
||||
+
|
||||
+/* i2c */
|
||||
+static int mt7987_i2c0_0_pins[] = {29, 30};
|
||||
+static int mt7987_i2c0_0_funcs[] = {2, 2};
|
||||
+
|
||||
+static int mt7987_i2c0_1_pins[] = {39, 40};
|
||||
+static int mt7987_i2c0_1_funcs[] = {2, 2};
|
||||
+
|
||||
+static int mt7987_i2c0_2_pins[] = {43, 44};
|
||||
+static int mt7987_i2c0_2_funcs[] = {1, 1};
|
||||
+
|
||||
+/* pcie */
|
||||
+static int mt7987_pcie0_pereset_pins[] = {33};
|
||||
+static int mt7987_pcie0_pereset_funcs[] = {1};
|
||||
+
|
||||
+static int mt7987_pcie0_clkreq_pins[] = {34};
|
||||
+static int mt7987_pcie0_clkreq_funcs[] = {1};
|
||||
+
|
||||
+static int mt7987_pcie0_wake_pins[] = {35};
|
||||
+static int mt7987_pcie0_wake_funcs[] = {1};
|
||||
+
|
||||
+static int mt7987_pcie1_pereset_pins[] = {36};
|
||||
+static int mt7987_pcie1_pereset_funcs[] = {1};
|
||||
+
|
||||
+static int mt7987_pcie1_clkreq_pins[] = {37};
|
||||
+static int mt7987_pcie1_clkreq_funcs[] = {1};
|
||||
+
|
||||
+static int mt7987_pcie1_wake_pins[] = {38};
|
||||
+static int mt7987_pcie1_wake_funcs[] = {1};
|
||||
+
|
||||
+static int mt7987_pcie_phy_i2c_pins[] = {43, 44};
|
||||
+static int mt7987_pcie_phy_i2c_funcs[] = {3, 3};
|
||||
+
|
||||
+static const struct group_desc mt7987_groups[] = {
|
||||
+ PINCTRL_PIN_GROUP("watchdog", mt7987_watchdog),
|
||||
+ PINCTRL_PIN_GROUP("jtag", mt7987_jtag),
|
||||
+ PINCTRL_PIN_GROUP("i2s", mt7987_i2s),
|
||||
+ PINCTRL_PIN_GROUP("pcm", mt7987_pcm),
|
||||
+ PINCTRL_PIN_GROUP("uart0", mt7987_uart0),
|
||||
+ PINCTRL_PIN_GROUP("uart1_0", mt7987_uart1_0),
|
||||
+ PINCTRL_PIN_GROUP("uart1_0_lite", mt7987_uart1_0_lite),
|
||||
+ PINCTRL_PIN_GROUP("uart1_1", mt7987_uart1_1),
|
||||
+ PINCTRL_PIN_GROUP("uart1_2", mt7987_uart1_2),
|
||||
+ PINCTRL_PIN_GROUP("uart2_0", mt7987_uart2_0),
|
||||
+ PINCTRL_PIN_GROUP("uart2_1", mt7987_uart2_1),
|
||||
+ PINCTRL_PIN_GROUP("pwm0", mt7987_pwm0),
|
||||
+ PINCTRL_PIN_GROUP("pwm1_0", mt7987_pwm1_0),
|
||||
+ PINCTRL_PIN_GROUP("pwm1_1", mt7987_pwm1_1),
|
||||
+ PINCTRL_PIN_GROUP("pwm2_0", mt7987_pwm2_0),
|
||||
+ PINCTRL_PIN_GROUP("pwm2_1", mt7987_pwm2_1),
|
||||
+ PINCTRL_PIN_GROUP("drv_vbus_p1", mt7987_drv_vbus_p1),
|
||||
+ PINCTRL_PIN_GROUP("drv_vbus", mt7987_drv_vbus),
|
||||
+ PINCTRL_PIN_GROUP("2p5gbe_led0", mt7987_2p5gbe_led0),
|
||||
+ PINCTRL_PIN_GROUP("2p5gbe_led1_0", mt7987_2p5gbe_led1_0),
|
||||
+ PINCTRL_PIN_GROUP("2p5gbe_led1_1", mt7987_2p5gbe_led1_1),
|
||||
+ PINCTRL_PIN_GROUP("2p5g_ext_mdc_mdio", mt7987_2p5g_ext_mdc_mdio),
|
||||
+ PINCTRL_PIN_GROUP("mdc_mdio", mt7987_mdc_mdio),
|
||||
+ PINCTRL_PIN_GROUP("spi0", mt7987_spi0),
|
||||
+ PINCTRL_PIN_GROUP("spi0_wp_hold", mt7987_spi0_wp_hold),
|
||||
+ PINCTRL_PIN_GROUP("spi1", mt7987_spi1),
|
||||
+ PINCTRL_PIN_GROUP("spi1_1", mt7987_spi1_1),
|
||||
+ PINCTRL_PIN_GROUP("spi2", mt7987_spi2),
|
||||
+ PINCTRL_PIN_GROUP("spi2_wp_hold", mt7987_spi2_wp_hold),
|
||||
+ PINCTRL_PIN_GROUP("emmc_45", mt7987_emmc_45),
|
||||
+ PINCTRL_PIN_GROUP("sd", mt7987_sd),
|
||||
+ PINCTRL_PIN_GROUP("i2c0_0", mt7987_i2c0_0),
|
||||
+ PINCTRL_PIN_GROUP("i2c0_1", mt7987_i2c0_1),
|
||||
+ PINCTRL_PIN_GROUP("i2c0_2", mt7987_i2c0_2),
|
||||
+ PINCTRL_PIN_GROUP("pcie0_pereset", mt7987_pcie0_pereset),
|
||||
+ PINCTRL_PIN_GROUP("pcie0_clkreq", mt7987_pcie0_clkreq),
|
||||
+ PINCTRL_PIN_GROUP("pcie0_wake", mt7987_pcie0_wake),
|
||||
+ PINCTRL_PIN_GROUP("pcie1_pereset", mt7987_pcie1_pereset),
|
||||
+ PINCTRL_PIN_GROUP("pcie1_clkreq", mt7987_pcie1_clkreq),
|
||||
+ PINCTRL_PIN_GROUP("pcie1_wake", mt7987_pcie1_wake),
|
||||
+ PINCTRL_PIN_GROUP("pcie1_pcie_phy_i2c", mt7987_pcie_phy_i2c),
|
||||
+};
|
||||
+
|
||||
+static const char *const mt7987_audio_groups[] = {"i2s", "pcm",};
|
||||
+static const char *const mt7987_wdt_groups[] = {"watchdog",};
|
||||
+static const char *const mt7987_jtag_groups[] = {"jtag",};
|
||||
+static const char *const mt7987_uart_groups[] = {"uart0", "uart1_0",
|
||||
+ "uart1_0_lite", "uart1_1",
|
||||
+ "uart1_2", "uart2_0",
|
||||
+ "uart2_1",};
|
||||
+static const char *const mt7987_pwm_groups[] = {"pwm0", "pwm1_0", "pwm1_1", "pwm2_0",
|
||||
+ "pwm2_1",};
|
||||
+static const char *const mt7987_usb_groups[] = {"drv_vbus_p1", "drv_vbus",};
|
||||
+static const char *const mt7987_led_groups[] = {"2p5gbe_led0", "2p5gbe_led1_0",
|
||||
+ "2p5gbe_led1_1",};
|
||||
+static const char *const mt7987_ethernet_groups[] = {"2p5g_ext_mdc_mdio", "mdc_mdio",};
|
||||
+static const char *const mt7987_spi_groups[] = {"spi0", "spi0_wp_hold", "spi1",
|
||||
+ "spi1_1", "spi2", "spi2_wp_hold",};
|
||||
+static const char *const mt7987_flash_groups[] = {"emmc_45", "sd",};
|
||||
+static const char *const mt7987_i2c_groups[] = {"i2c0_0", "i2c0_1", "i2c0_2",};
|
||||
+static const char *const mt7987_pcie_groups[] = {"pcie_phy_i2c", "pcie0_pereset",
|
||||
+ "pcie0_clkreq", "pcie0_wake",
|
||||
+ "pcie1_pereset", "pcie1_clkreq",
|
||||
+ "pcie1_wake",};
|
||||
+
|
||||
+
|
||||
+static const struct function_desc mt7987_functions[] = {
|
||||
+ { {"audio", mt7987_audio_groups, ARRAY_SIZE(mt7987_audio_groups)}, NULL },
|
||||
+ { {"wdt", mt7987_wdt_groups, ARRAY_SIZE(mt7987_wdt_groups)}, NULL },
|
||||
+ { {"jtag", mt7987_jtag_groups, ARRAY_SIZE(mt7987_jtag_groups)}, NULL },
|
||||
+ { {"uart", mt7987_uart_groups, ARRAY_SIZE(mt7987_uart_groups)}, NULL },
|
||||
+ { {"pwm", mt7987_pwm_groups, ARRAY_SIZE(mt7987_pwm_groups)}, NULL },
|
||||
+ { {"usb", mt7987_usb_groups, ARRAY_SIZE(mt7987_usb_groups)}, NULL },
|
||||
+ { {"led", mt7987_led_groups, ARRAY_SIZE(mt7987_led_groups)}, NULL },
|
||||
+ { {"eth", mt7987_ethernet_groups, ARRAY_SIZE(mt7987_ethernet_groups)}, NULL },
|
||||
+ { {"spi", mt7987_spi_groups, ARRAY_SIZE(mt7987_spi_groups)}, NULL },
|
||||
+ { {"flash", mt7987_flash_groups, ARRAY_SIZE(mt7987_flash_groups)}, NULL },
|
||||
+ { {"i2c", mt7987_i2c_groups, ARRAY_SIZE(mt7987_i2c_groups)}, NULL },
|
||||
+ { {"pcie", mt7987_pcie_groups, ARRAY_SIZE(mt7987_pcie_groups)}, NULL },
|
||||
+};
|
||||
+
|
||||
+static const struct mtk_eint_hw mt7987_eint_hw = {
|
||||
+ .port_mask = 7,
|
||||
+ .ports = 7,
|
||||
+ .ap_num = ARRAY_SIZE(mt7987_pins),
|
||||
+ .db_cnt = 16,
|
||||
+};
|
||||
+
|
||||
+static const char * const mt7987_pinctrl_register_base_names[] = {
|
||||
+ "gpio", "iocfg_rb", "iocfg_lb", "iocfg_rt1", "iocfg_rt2", "iocfg_tl",
|
||||
+};
|
||||
+
|
||||
+static struct mtk_pin_soc mt7987_data = {
|
||||
+ .reg_cal = mt7987_reg_cals,
|
||||
+ .pins = mt7987_pins,
|
||||
+ .npins = ARRAY_SIZE(mt7987_pins),
|
||||
+ .grps = mt7987_groups,
|
||||
+ .ngrps = ARRAY_SIZE(mt7987_groups),
|
||||
+ .funcs = mt7987_functions,
|
||||
+ .nfuncs = ARRAY_SIZE(mt7987_functions),
|
||||
+ .eint_hw = &mt7987_eint_hw,
|
||||
+ .gpio_m = 0,
|
||||
+ .ies_present = false,
|
||||
+ .base_names = mt7987_pinctrl_register_base_names,
|
||||
+ .nbase_names = ARRAY_SIZE(mt7987_pinctrl_register_base_names),
|
||||
+ .bias_disable_set = mtk_pinconf_bias_disable_set,
|
||||
+ .bias_disable_get = mtk_pinconf_bias_disable_get,
|
||||
+ .bias_set = mtk_pinconf_bias_set,
|
||||
+ .bias_get = mtk_pinconf_bias_get,
|
||||
+ .pull_type = mt7987_pull_type,
|
||||
+ .bias_set_combo = mtk_pinconf_bias_set_combo,
|
||||
+ .bias_get_combo = mtk_pinconf_bias_get_combo,
|
||||
+ .drive_set = mtk_pinconf_drive_set_rev1,
|
||||
+ .drive_get = mtk_pinconf_drive_get_rev1,
|
||||
+ .adv_pull_get = mtk_pinconf_adv_pull_get,
|
||||
+ .adv_pull_set = mtk_pinconf_adv_pull_set,
|
||||
+};
|
||||
+
|
||||
+static const struct of_device_id mt7987_pinctrl_of_match[] = {
|
||||
+ {
|
||||
+ .compatible = "mediatek,mt7987-pinctrl",
|
||||
+ },
|
||||
+ {}
|
||||
+};
|
||||
+
|
||||
+static int mt7987_pinctrl_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ return mtk_moore_pinctrl_probe(pdev, &mt7987_data);
|
||||
+}
|
||||
+
|
||||
+static struct platform_driver mt7987_pinctrl_driver = {
|
||||
+ .driver = {
|
||||
+ .name = "mt7987-pinctrl",
|
||||
+ .of_match_table = mt7987_pinctrl_of_match,
|
||||
+ },
|
||||
+ .probe = mt7987_pinctrl_probe,
|
||||
+};
|
||||
+
|
||||
+static int __init mt7987_pinctrl_init(void)
|
||||
+{
|
||||
+ return platform_driver_register(&mt7987_pinctrl_driver);
|
||||
+}
|
||||
+arch_initcall(mt7987_pinctrl_init);
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,54 @@
|
|||
From e924479ebc284f591e90049c03aeef6da7786318 Mon Sep 17 00:00:00 2001
|
||||
From: Daniel Golle <daniel@makrotopia.org>
|
||||
Date: Mon, 15 Sep 2025 12:05:06 +0100
|
||||
Subject: [PATCH] tty: serial: 8250_mtk: enable baud clock
|
||||
|
||||
Some MediaTek SoCs got a gated UART baud clock, which currently gets
|
||||
disabled as the clk subsystem believes it would be unused. This results in
|
||||
the uart freezing right after "clk: Disabling unused clocks" on those
|
||||
platforms.
|
||||
|
||||
To fix this request the baud clock to be prepared and enabled during probe,
|
||||
and also prepare and enable the baud clock when resume the port while
|
||||
disabling and unpreparing it when suspending.
|
||||
|
||||
Fixes: e32a83c70cf9 ("serial: 8250-mtk: modify mtk uart power and clock management")
|
||||
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||
---
|
||||
drivers/tty/serial/8250/8250_mtk.c | 6 ++++--
|
||||
1 file changed, 4 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/tty/serial/8250/8250_mtk.c
|
||||
+++ b/drivers/tty/serial/8250/8250_mtk.c
|
||||
@@ -435,6 +435,7 @@ static int __maybe_unused mtk8250_runtim
|
||||
while
|
||||
(serial_in(up, MTK_UART_DEBUG0));
|
||||
|
||||
+ clk_disable_unprepare(data->uart_clk);
|
||||
clk_disable_unprepare(data->bus_clk);
|
||||
|
||||
return 0;
|
||||
@@ -445,6 +446,7 @@ static int __maybe_unused mtk8250_runtim
|
||||
struct mtk8250_data *data = dev_get_drvdata(dev);
|
||||
|
||||
clk_prepare_enable(data->bus_clk);
|
||||
+ clk_prepare_enable(data->uart_clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -475,13 +477,13 @@ static int mtk8250_probe_of(struct platf
|
||||
int dmacnt;
|
||||
#endif
|
||||
|
||||
- data->uart_clk = devm_clk_get(&pdev->dev, "baud");
|
||||
+ data->uart_clk = devm_clk_get_enabled(&pdev->dev, "baud");
|
||||
if (IS_ERR(data->uart_clk)) {
|
||||
/*
|
||||
* For compatibility with older device trees try unnamed
|
||||
* clk when no baud clk can be found.
|
||||
*/
|
||||
- data->uart_clk = devm_clk_get(&pdev->dev, NULL);
|
||||
+ data->uart_clk = devm_clk_get_enabled(&pdev->dev, NULL);
|
||||
if (IS_ERR(data->uart_clk)) {
|
||||
dev_warn(&pdev->dev, "Can't get uart clock\n");
|
||||
return PTR_ERR(data->uart_clk);
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
From 7f4532a2bffdb0aebcabc2a672c4b97670e002a5 Mon Sep 17 00:00:00 2001
|
||||
From: Sam Shih <sam.shih@mediatek.com>
|
||||
Date: Mon, 3 Mar 2025 14:33:33 +0800
|
||||
Subject: [PATCH] add pwm reg-v3 support for mt7987
|
||||
|
||||
---
|
||||
drivers/pwm/pwm-mediatek.c | 20 ++++++++++++++++++++
|
||||
1 file changed, 20 insertions(+)
|
||||
|
||||
--- a/drivers/pwm/pwm-mediatek.c
|
||||
+++ b/drivers/pwm/pwm-mediatek.c
|
||||
@@ -64,6 +64,10 @@ static const unsigned int mtk_pwm_reg_of
|
||||
0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
|
||||
};
|
||||
|
||||
+static const unsigned int mtk_pwm_reg_offset_v3[] = {
|
||||
+ 0x0100, 0x0200, 0x0300, 0x0400, 0x0500, 0x600, 0x700, 0x0800
|
||||
+};
|
||||
+
|
||||
static inline struct pwm_mediatek_chip *
|
||||
to_pwm_mediatek_chip(struct pwm_chip *chip)
|
||||
{
|
||||
@@ -350,6 +354,13 @@ static const struct pwm_mediatek_of_data
|
||||
.reg_offset = mtk_pwm_reg_offset_v1,
|
||||
};
|
||||
|
||||
+static const struct pwm_mediatek_of_data mt7987_pwm_data = {
|
||||
+ .num_pwms = 3,
|
||||
+ .pwm45_fixup = false,
|
||||
+ .has_ck_26m_sel = false,
|
||||
+ .reg_offset = mtk_pwm_reg_offset_v3,
|
||||
+};
|
||||
+
|
||||
static const struct pwm_mediatek_of_data mt7988_pwm_data = {
|
||||
.num_pwms = 8,
|
||||
.pwm45_fixup = false,
|
||||
@@ -387,6 +398,7 @@ static const struct of_device_id pwm_med
|
||||
{ .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
|
||||
{ .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data },
|
||||
{ .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
|
||||
+ { .compatible = "mediatek,mt7987-pwm", .data = &mt7987_pwm_data },
|
||||
{ .compatible = "mediatek,mt7988-pwm", .data = &mt7988_pwm_data },
|
||||
{ .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
|
||||
{ .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },
|
||||
Loading…
Add table
Reference in a new issue