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octeon: fix octeon build with CONFIG_KERNEL_WERROR

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Add a patch fixing a bunch of missing prototype errors, scattered all over the
tree.

Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
This commit is contained in:
Rui Salvaterra 2025-08-05 12:55:24 +01:00
parent b3eac6dca5
commit 673b48a674
4 changed files with 134 additions and 9 deletions
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116
target/linux/octeon/patches-6.12/000-fix-octeon-kernel-build.patch Normal file
View file

@ -0,0 +1,116 @@
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -15,6 +15,7 @@
#include <linux/libfdt.h>
#include <asm/octeon/octeon.h>
+#include <asm/octeon/octeon-platform.h>
#include <asm/octeon/cvmx-helper-board.h>
#ifdef CONFIG_USB
--- a/arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-interrupt-decodes.c
@@ -34,6 +34,7 @@
#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-interrupt-decodes.h>
#include <asm/octeon/cvmx-gmxx-defs.h>
#include <asm/octeon/cvmx-pcsx-defs.h>
#include <asm/octeon/cvmx-pcsxx-defs.h>
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c
@@ -39,6 +39,8 @@
#include <asm/octeon/cvmx-helper-jtag.h>
+#include <asm/octeon/cvmx-helper-errata.h>
+
/**
* Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
* 1 doesn't work properly. The following code disables 2nd order
--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
@@ -92,6 +92,8 @@ static irqreturn_t mailbox_interrupt(int
return IRQ_HANDLED;
}
+void octeon_send_ipi_single(int cpu, unsigned int action);
+
/*
* Cause the function described by call_data to be executed on the passed
* cpu. When the function has finished, increment the finished field of
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -16,6 +16,7 @@
#include <asm/bcache.h>
#include <asm/bootinfo.h>
+#include <asm/c-octeon.h>
#include <asm/cacheops.h>
#include <asm/cpu-features.h>
#include <asm/cpu-type.h>
--- /dev/null
+++ b/arch/mips/include/asm/c-octeon.h
@@ -0,0 +1,9 @@
+#ifndef __C_OCTEON_H__
+#define __C_OCTEON_H__
+
+extern int register_co_cache_error_notifier(struct notifier_block *nb);
+extern int unregister_co_cache_error_notifier(struct notifier_block *nb);
+extern void cache_parity_error_octeon_recoverable(void);
+extern void cache_parity_error_octeon_non_recoverable(void);
+
+#endif
--- /dev/null
+++ b/drivers/watchdog/octeon-wdt-main.h
@@ -0,0 +1,5 @@
+#ifdef CONFIG_OCTEON_WDT
+
+extern void octeon_wdt_nmi_stage3(u64 reg[32]);
+
+#endif
--- a/drivers/watchdog/octeon-wdt-main.c
+++ b/drivers/watchdog/octeon-wdt-main.c
@@ -64,6 +64,8 @@
#include <asm/octeon/cvmx-ciu2-defs.h>
#include <asm/octeon/cvmx-rst-defs.h>
+#include "octeon-wdt-main.h"
+
/* Watchdog interrupt major block number (8 MSBs of intsn) */
#define WD_BLOCK_NUMBER 0x01
--- a/arch/mips/include/asm/octeon/pci-octeon.h
+++ b/arch/mips/include/asm/octeon/pci-octeon.h
@@ -24,6 +24,12 @@
*/
#define CVMX_PCIE_BAR1_RC_BASE (1ull << 41)
+extern int octeon_pci_pcibios_map_irq(const struct pci_dev *dev, u8 slot,
+ u8 pin);
+
+extern int octeon_pcie_pcibios_map_irq(const struct pci_dev *dev, u8 slot,
+ u8 pin);
+
/*
* pcibios_map_irq() is defined inside pci-octeon.c. All it does is
* call the Octeon specific version pointed to by this variable. This
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-interrupt-decodes.h
@@ -0,0 +1,6 @@
+#ifndef __CVMX_INTERRUPT_DECODES_H__
+#define __CVMX_INTERRUPT_DECODES_H__
+
+extern void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block);
+
+#endif
--- /dev/null
+++ b/arch/mips/include/asm/octeon/octeon-platform.h
@@ -0,0 +1,6 @@
+#ifndef __OCTEON_PLATFORM_H__
+#define __OCTEON_PLATFORM_H__
+
+extern void octeon_fill_mac_addresses(void);
+
+#endif

2
target/linux/octeon/patches-6.12/130-add_itus_support.patch
View file

@ -1,6 +1,6 @@
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -775,7 +775,7 @@ int __init octeon_prune_device_tree(void
@@ -776,7 +776,7 @@ int __init octeon_prune_device_tree(void
if (fdt_check_header(initial_boot_params))
panic("Corrupt Device Tree.");

2
target/linux/octeon/patches-6.12/150-ubnt_usg_support.patch
View file

@ -18,7 +18,7 @@
ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_ITUS_SHIELD)
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -636,6 +636,7 @@ static void __init octeon_rx_tx_delay(in
@@ -637,6 +637,7 @@ static void __init octeon_rx_tx_delay(in
}
break;
case CVMX_BOARD_TYPE_UBNT_E100:

23
target/linux/octeon/patches-6.12/400-ubnt_dts_pruning.patch
View file

@ -17,7 +17,7 @@ Date: Tue Jun 17 13:58:19 2025 +0200
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -1133,6 +1133,41 @@ end_led:
@@ -1134,6 +1134,41 @@ end_led:
}
#endif
@ -61,14 +61,14 @@ Date: Tue Jun 17 13:58:19 2025 +0200
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -1168,6 +1168,7 @@ void __init prom_free_prom_memory(void)
}
}
@@ -43,6 +43,7 @@
#include <asm/time.h>
+int __init ubnt_prune_device_tree(void);
void __init octeon_fill_mac_addresses(void);
#include <asm/octeon/octeon.h>
+#include <asm/octeon/octeon-platform.h>
#include <asm/octeon/pci-octeon.h>
#include <asm/octeon/cvmx-rst-defs.h>
void __init device_tree_init(void)
@@ -1207,6 +1208,9 @@ void __init device_tree_init(void)
octeon_prune_device_tree();
pr_info("Using internal Device Tree.\n");
@ -79,3 +79,12 @@ Date: Tue Jun 17 13:58:19 2025 +0200
if (fill_mac)
octeon_fill_mac_addresses();
unflatten_and_copy_device_tree();
--- a/arch/mips/include/asm/octeon/octeon-platform.h
+++ b/arch/mips/include/asm/octeon/octeon-platform.h
@@ -2,5 +2,6 @@
#define __OCTEON_PLATFORM_H__
extern void octeon_fill_mac_addresses(void);
+extern int ubnt_prune_device_tree(void);
#endif