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mediatek: dts: mt7981: fix spi clocks
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Fix spi1 sel-clk source and add missing assigned-clocks.

Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/21108
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Shiji Yang 2026-01-19 22:26:09 +08:00 • committed by Hauke Mehrtens
parent 3462789923
commit 46129bbbf5
1 changed files with 53 additions and 0 deletions
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53
target/linux/mediatek/patches-6.12/187-arm64-dts-mediatek-fix-mt7981-spim-clock.patch Normal file
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@ -0,0 +1,53 @@
From 0c74ae06ed6b6c9627712a74ecee4e61bbd4092d Mon Sep 17 00:00:00 2001
From: developer <developer@mediatek.com>
Date: Mon, 19 Jan 2026 21:42:29 +0800
Subject: [PATCH] arm64: dts: mediatek: fix mt7981 spim clock
1) Add spi0/1/2 clock parent setting
2) Fix spi1 clock_sel to CLK_TOP_SPIM_MST_SEL
Link: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/836034ca0baad57e4c287a62ccc5677c60be0e18
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
---
arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi
@@ -248,6 +248,10 @@
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_SPI2_CK>,
<&infracfg CLK_INFRA_SPI2_HCK_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI2_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
+ <&topckgen CLK_TOP_SPI_SEL>;
clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
#address-cells = <1>;
#size-cells = <0>;
@@ -262,6 +266,10 @@
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_SPI0_CK>,
<&infracfg CLK_INFRA_SPI0_HCK_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
+ <&topckgen CLK_TOP_SPI_SEL>;
clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
#address-cells = <1>;
#size-cells = <0>;
@@ -273,9 +281,13 @@
reg = <0 0x1100b000 0 0x1000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_CB_M_D2>,
- <&topckgen CLK_TOP_SPI_SEL>,
+ <&topckgen CLK_TOP_SPIM_MST_SEL>,
<&infracfg CLK_INFRA_SPI1_CK>,
<&infracfg CLK_INFRA_SPI1_HCK_CK>;
+ assigned-clocks = <&topckgen CLK_TOP_SPIM_MST_SEL>,
+ <&infracfg CLK_INFRA_SPI1_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
+ <&topckgen CLK_TOP_SPIM_MST_SEL>;
clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
#address-cells = <1>;
#size-cells = <0>;